JP3081346B2 - Digital fade circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital fade circuit and, more particularly, to an A / D converter for outputting an output signal from, for example, a CCD.
The present invention relates to a digital fade circuit in a video camera that converts a digital signal into a digital signal by a converter and processes the digital signal.

[0002]

2. Description of the Related Art In a conventional consumer analog signal processing camera, when fade-out or fade-in is performed, the output image of the camera gradually becomes white, or a white fade gradually changes from white to a subject image, and the output image gradually becomes black. There is a black fade that gradually changes from black to a subject image gradually from black.

[0003]

With the widespread use of video cameras, there are various demands from users for fade processing such as splicing. On the other hand, the conventional consumer analog processing camera as described above can perform only white fading or black fading, and cannot meet such a demand.

[0004] Therefore, a main object of the present invention is to provide a digital fade circuit capable of easily performing various fade processes by utilizing characteristics in digital signal processing.

[0005]

According to the present invention, there is provided a video signal processing means for YC-separating an output signal from an image sensor and outputting a first video signal, and a first video signal output from the video signal processing means. Synchronizing signal adding means for adding and outputting a horizontal synchronizing signal and a vertical synchronizing signal, address counter means for specifying an address position on a display screen based on the horizontal synchronizing signal and the vertical synchronizing signal, Area setting means for setting a mask area by designating an address position at a position, changing the address position specified by the area setting means with time, and changing the size of the mask area; a video signal supply means for supplying a different second video signal from said first video signal to the mask region set by the region setting means, said video signal processing means and the synchronizing signal Is provided between the pressurizing means, the address position of the mask area and selecting the second video signal when specifying said address counter means and said first image when specifying the address location other than the mask area Selecting means for selecting a signal and outputting the selected signal to the synchronizing signal adding means.

[0006]

Normally, the first video signal from the video signal processing means is output.
Is selected by the selection means and output to the synchronization signal addition circuit for display.
Display on the screen. Mask area is set by area setting means
If the video signal is
No. selection means to select the second video signal that will be supplied from the supply means
And outputs it to the synchronization signal adding means.

When this mask area is set, the first image
The display on the display screen based on the signal is masked. Therefore
Specify the address position of the mask area specified by the area setting means.
By changing the area, the mask area can be changed freely.
You can change the size and fade in and out.
You can do it.

[0008] Further , the video signal supply means is provided in the mask area.
As a second video signal to be supplied, a predetermined video is used.
Alternatively, an external input image can be supplied.

[0009]

According to the present invention, it is possible to perform various fade processes which cannot be performed by a conventional analog signal processing camera, by simply adding a simple circuit.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Digital signal processing camera 10 shown in FIG.
Is an A / D converter that receives an output signal from a CCD (not shown) serving as an image sensor from which reset noise has been removed by a correlated double sampling circuit (not shown) and converts it into a digital signal (data). And a vessel 12. This A
The digital signal from the / D converter 12 is applied to the YC separation circuit 1
4 given. The luminance signal (Y
Signal) is applied to the Y process circuit 16 and the color signal (C signal) is applied to the C process circuit 18. The Y signal processed by the Y process circuit 16 is supplied to a selection circuit 20 as selection means, and the (RY) signal and the (BY) signal output from the C process circuit 18 are output to the selection circuit 22.
Given to.

The aforementioned A / D converter 12, YC separation circuit 1
4Y processing circuit 16 and the C process circuit 18, the onset
Video signal processing means, and the Y signal and (R-
The (Y) signal and the (BY) signal correspond to the first video signal.
You.

The output of the selection circuit 24 is further provided to the selection circuit 20, and the output of the selection circuit 30 is further provided to the selection circuit 22. The selection circuit 24 selects one of the mask Y level output from the CPU 32 and the Y signal set from an appropriate external input and supplies the selected signal to the selection circuit 20. Select circuit 30 receives the outputs of select circuits 26 and 28. The selection circuit 26 selects one of a mask (RY) level set by the CPU 32 and a (RY) signal given by an appropriate external input and supplies the selected signal to the selection circuit 30. The selection circuit 28 One of the mask (BY) level set and the (BY) signal set by an appropriate external input is selected and applied to the selection circuit 30.

Therefore, the selection circuit 30 includes the CPU 32
(R-Y) level set by an external input or a (RY) signal set by an external input or CPU
A mask (BY) level set by 32 or a (BY) signal set by an external input is selected and given to the selection circuit 22. The selection circuits 20 and 22 receive the upper input, that is, the Y process circuit 1 by the window pulse from the window pulse generation circuit 34, respectively.
6 and (R−
(Y) signal and (BY) signal or the Y level from the selection circuit 24 and the (RY) signal or (BY) signal from the selection circuit 30 are selected.

Here, the window pulse generating circuit 34 serving as the area setting means will be described in detail. The window pulse generation circuit 34 generates position data VOPN, VCLS, HOPN and H set by the CPU 32.
A comparator 38 receiving CLS as one of its inputs;
40, 42 and 44.

The position data VOPN is data indicating a position defining the vertical start of the window area shown in FIG. 2, and the position data VCLS is data indicating a position defining the vertical end thereof. Similarly, the position data HOPN and HCLS are data respectively indicating the horizontal start and end positions of the window area shown in FIG.

The other input of comparators 38 and 40 receives the V address from address counter 36, and the other input of comparators 42 and 44 receives the H address from address counter 36. That is, the address counter 36 receives the vertical synchronizing signal VD and the horizontal synchronizing signal HD, counts them, and outputs the above-described V address and H address indicating the vertical position and the horizontal position on the screen. Where CP
U32 corresponds to the area changing means of the present invention.

Accordingly, the comparator 38 compares the vertical start position data set by the CPU 32 with the vertical position data (V address) on the screen output from the address counter 36, and when they match, the high level is high. Outputs a signal that becomes a level. The comparator 40 is a CPU 32
And the vertical end position data VCLS provided from the address counter 36 with the vertical position (V address) on the screen provided from the address counter 36, and outputs a high level signal when they match.

Similarly, comparators 42 and 44 provide C
Start position HOP in the horizontal direction set by PU32
N and HCLS and the horizontal position (H address) on the screen output from the address counter 36 are compared with each other, and a signal which goes to a high level when they match is output.

The outputs of comparators 38 and 40 are applied to VW pulse generation circuit 46, and the outputs of comparators 42 and 44 are applied to HW pulse generation circuit 48. The VW pulse generation circuit 46 outputs a VW pulse (FIG. 3) that goes high from the trailing edge of the high-level signal output from the comparator 38 to the trailing edge of the high-level signal output from the comparator 40. And receives the horizontal synchronization signal HD as its clock input. Further, the HW pulse generation circuit 48 outputs an HW pulse (FIG. 3) which is at a high level from the trailing edge of the high level signal output from the comparator 42 to the trailing edge of the high level signal output from the comparator 44, A clock CLK corresponding to one pixel on the screen is received as the clock input.

In this manner, the VW pulse and the HW pulse shown in FIG. 3 are output from VW pulse generation circuit 46 and HW pulse generation circuit 48, respectively, and supplied to AND gate 50. Therefore, the AND gate 50
Then, the VW pulse and the HW pulse are AND-processed, and a window pulse (W pulse) as shown in FIG. 3 is output.

However, the W pulse from the AND gate 50 is further applied to an exclusive OR gate 52. As another input of the exclusive OR gate 52, a window inversion signal output from a window inversion switch (not shown) provided in the camera 10 is provided. The window inversion signal is set to "0" when a video signal from a CCD (not shown) is output to a window area (FIG. 2) defined by the preceding position data VOPN, VCLS, HOPN and HCLS. It becomes "1" when the mask level set by the CPU 32 or an appropriate external input is displayed in the area.

That is, when a window inversion switch (not shown) is operated, the exclusive OR gate 5 is activated.
2 outputs an inverted signal of the W pulse shown in FIG.
When the window inversion switch is not operated, the exclusive OR gate 52 outputs the W pulse shown in FIG. 3 as it is.

As described above, the output from the exclusive OR gate 52 of the window pulse generating circuit 34 defines the window area and the mask area shown in FIG.

The selection circuit 20 outputs a Y signal output from the Y process circuit 16 in the window area, and outputs a mask Y level supplied from the selection circuit 24 in the mask area.

The mask Y level is, as described above,
It is set by the CPU 32 or by an appropriate external input. Similarly, the selection circuit 22
In the window area, the (RY) signal and the (BY) signal obtained from the C process circuit 18 are output alternately,
In the mask area, a mask (R
-Y) level and mask (BY) level are output alternately.

That is, from the C process circuit 18,
Since the (RY) signal and the (BY) signal are output dot-sequentially, the selection circuit 30 responds accordingly to the mask (R
-Y) level and mask (BY) level are output alternately.

Thus, the selection circuits 20 and 22
Thus, the video signal in the window area and the video signal in the mask area are selected according to the W pulse from the window pulse generation circuit 34, and the selected video signal is supplied to the synchronization signal adding circuit 56.
The synchronizing signal adding circuit adds a synchronizing signal to the signals output from the selecting circuits 20 and 22 to add a Y signal and (R−
Y) and (BY) signals. However,
The (RY) signal and the (BY) signal are converted into a C signal by the encoder 58 and output.

In the embodiment shown in FIG. 1, since the mask levels can be set by the CPU 32, the brightness and the color tone in the mask area shown in FIG. 2 can be arbitrarily changed.
Also, appropriate external inputs are connected to selection circuits 24, 26 and 28.
, The subject image can be output to the window area and the external input image can be output to the mask area, or vice versa.

The CPU 32 for outputting a mask level
And the selection circuits 24, 26, 28, 30
It corresponds to the signal supply means, and from the selection circuits 24 and 30
The output signal corresponds to the second video signal of the present invention.

If the CPU 32 changes the positions VOPN, VCLS, HOPN, and HCLS defining the square on the screen for each field, the window area shown in FIG. 2 is expanded, narrowed, or moved for each field. It is possible.

That is, in the fade processing shown in FIG. 4, in the case of a fade-out of a rightward arrow, the window area is reduced in the field order, and finally, all become mask areas. Conversely, in the case of the fade-in of the left-pointing arrow shown in FIG.

In the case shown in FIG. 5, the CPU 32
Only the vertical start position VOPN shown in FIG. In this case, the vertical end position is constant, and the horizontal start and end positions are also constant. That is, in the case of the fade-out indicated by the rightward arrow in FIG. 5, for example, the mask area is sequentially expanded from the upper side of the screen to the field, and eventually becomes the mask area. In the case of the fade-in indicated by the leftward arrow in FIG. 5, the window area is sequentially enlarged from the lower side from the state where the entire area is the mask area.

The fade processing of FIG. 6 is the reverse of FIG.
U32 is a case where only the horizontal start position HOPN (FIG. 2) is changed and set in the field order. That is, in the case of the fade-out indicated by the rightward arrow in FIG. 6, the mask area is sequentially enlarged from the left end, and eventually becomes the mask area. In the case of the fade-in indicated by the leftward arrow in FIG. 6, the window area is sequentially expanded from the right end to the field from the state of the mask area.

As described above, according to the embodiment shown in FIG.
A variety of fade-in or fade-out processes can be performed by changing at least one piece of position data that defines a rectangle on the screen for each field by the CPU 32. However, it is needless to say that the position data from the CPU 32 does not necessarily need to be changed every field, but may be changed every arbitrary number of fields.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an illustrative view showing a window area and a mask area, a horizontal start and end position, and a vertical start and end position in the embodiment of FIG. 1;

FIG. 3 is a timing chart showing an operation of the window pulse generation circuit in the embodiment of FIG. 1;

FIG. 4 is an illustrative view showing a fade-in or fade-out achieved by the embodiment of FIG. 1;

FIG. 5 is an illustrative view showing a fade-in or fade-out achieved by the embodiment of FIG. 1;

FIG. 6 is an illustrative view showing a fade-in or fade-out achieved by the embodiment of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Digital signal processing camera 12 ... A / D converter 16 ... Y process circuit 18 ... C process circuit 20, 22, 24, 26, 28, 30 ... Selection circuit 32 ... CPU 34 ... Window pulse generation circuit 36 ... Address counter

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Seiji Kawakami 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-64-62086 (JP, A) JP-A-62-112194 (JP, A) JP-A-2-128474 (JP, A) JP-A-63-299688 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5 / 262-5/275

Claims (1)

(57) [Claims] 1. An output signal from an image sensor is separated by YC.
Video signal processing means for outputting a first video signal; synchronization signal adding means for adding and outputting a horizontal synchronization signal and a vertical synchronization signal to the first video signal output from the video signal processing means; Address counter means for designating an address position on a display screen based on a vertical synchronization signal; area setting means for designating an address position at an arbitrary position on the display screen to set a mask area; An address change unit that changes the designated address position over time to change the size of the mask area; and the first area is added to the mask area set by the area setting unit.
A video signal supply means for supplying a different second video signal from the video signal, the synchronizing signal adding hand and said video signal processing means
Is provided between the stages, the address position of the mask area and selecting the second video signal when specifying said address counter means and said first video signal when specifying the address location other than the mask area And a selecting means for selecting and outputting to the synchronizing signal adding means.