JPH04176277A - Picture mute circuit - Google Patents

Picture mute circuit

Info

Publication number
JPH04176277A
JPH04176277A JP30512290A JP30512290A JPH04176277A JP H04176277 A JPH04176277 A JP H04176277A JP 30512290 A JP30512290 A JP 30512290A JP 30512290 A JP30512290 A JP 30512290A JP H04176277 A JPH04176277 A JP H04176277A
Authority
JP
Japan
Prior art keywords
video
picture
signal
mute
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30512290A
Other languages
Japanese (ja)
Inventor
Tadashi Yamada
忠 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP30512290A priority Critical patent/JPH04176277A/en
Publication of JPH04176277A publication Critical patent/JPH04176277A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To enable the switching of video without noises or synchronization disturbance by switching signals while taking video mute during the vertical blanking period of the former video signal and releasing the video mute during the vertical blanking after the next picture signal is stabilized. CONSTITUTION:At the time of picture switching input, a mute command signal (d) is inputted to a picture mute circuit 1 by a key/remote control processing part 2. Simultaneously, a picture changeover signal (b) is outputted to a picture selection circuit 3 by delaying some 10m sec, and the input signal is switched. The picture selection circuit 3 outputs a post selection signal (a) to a picture output circuit 4, and transmits a vertical synchronizing pulse (c) to a picture mute circuit 1 at all times. The picture mute release is released after 100 to 200m sec after the picture changeover, and a picture mute output pulse (f) and a vertical synchronizing pulse (c) are synchronized to be released after the release. Thus, the quality at the time of switching the picture which is often overlooked can be improved during the advancement of technology in sound and image quality.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、映像信号の信号切換え時の映像ミコート回路
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video micort circuit for switching video signals.

従来の技術 一般にテレビのチャンネル切換え時には、チューナの同
調電圧が安定するまでの数10〜百数10m5ecの開
信号がなくなりノイズや同期の流れた画面が現われてし
まっている。また、テレビジョン放送信号の同期は各局
で異なり、また、テレビ、■TR,ビデオディスク等の
同期も各機器で異なるのが普通であり、信号切換え時に
一瞬同期の乱れた画面が見えたりしている。
BACKGROUND OF THE INVENTION Generally, when switching TV channels, the open signal for several tens to hundreds of m5ec is lost until the tuning voltage of the tuner stabilizes, and a screen with noise and synchronization appears. In addition, the synchronization of television broadcast signals differs for each station, and the synchronization of TVs, TRs, video discs, etc. also differs for each device, so when switching signals, you may see a momentary out-of-sync screen. There is.

また、従来、信号切換え時に映像ミューI〜をかけてい
る場合に於いても、一画面の途中でミュートの開始や終
わり部分が見えていた。
Furthermore, conventionally, even when video muting is applied at the time of signal switching, the start and end of muting could be seen in the middle of one screen.

発明が解決しようとする課題 このような従来の映像ミュート回路においては、同期の
異なる映像信号を切換える場合には一画面の途中でミュ
ートの開始や終り部分についてミュートがかからないこ
とがあった。
Problems to be Solved by the Invention In such conventional video mute circuits, when switching between video signals with different synchronization, muting may not be applied at the start or end of a screen in the middle of one screen.

本発明はこのような問題点を解決するもので、同期部れ
や、ノイズを解消し信号切換え時の画像の品質を向上さ
せることができる映像ミュート回路を提供することを目
的とするものである。
The present invention is intended to solve these problems, and it is an object of the present invention to provide a video mute circuit that can eliminate synchronization error and noise and improve image quality when switching signals. .

課題を解決するための手段 本発明は、」二記目的を達成するために、前映像信号の
垂直ブランキング期間中に映像ミュートをかけて信号を
切換え、次の映像信号が安定した後、垂直ブランキング
期間中に映像ミューI−を解除するように回路を構成し
たものである。
Means for Solving the Problems In order to achieve the second object, the present invention mutes the video signal during the vertical blanking period of the previous video signal to switch the signal, and after the next video signal becomes stable, the vertical blanking period The circuit is configured to release the video mu I- during the blanking period.

作用 本発明は上記した構成により、従来の信号切換え時のノ
イズや、同期部れや、従来の映像ミュートをかけている
場合に於いても画面上にミュートの開始や終わり部分が
見えていたのが、全て解消された品位の高い信月切換え
ができるものである。
The present invention has the above-mentioned configuration, which eliminates the noise caused by conventional signal switching, synchronization errors, and the fact that the beginning and end of muting can be seen on the screen even when muting the conventional video. However, it is possible to perform a high-quality Shingetsu switch that eliminates all of these problems.

実施例 以下、本発明の一実施例を第1図、第2図、第3図を参
照しながら説明する。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1, 2, and 3.

第1図は、本発明の映像ミュート回路1を示し、映像ミ
ュート発生部1−1へは、信号切換え時にミューI・指
令信号dが入り、映像ミュー1−パルスeを発生させ、
同期部1−2は、垂直同期パルスCに同期させて、映像
ミュート出力パルスfを発生ずるように構成している。
FIG. 1 shows a video mute circuit 1 of the present invention, in which the video mute generator 1-1 receives a mu I command signal d at the time of signal switching, generates a video mu 1 pulse e,
The synchronization section 1-2 is configured to generate a video mute output pulse f in synchronization with the vertical synchronization pulse C.

第2図は、本発明の映像ミュート回路1を含む全体回路
を示しており、第3図は、第2図の入出力線の垂直レー
1−でのタイミングを示している。
FIG. 2 shows the entire circuit including the video mute circuit 1 of the present invention, and FIG. 3 shows the timing of the input/output lines of FIG. 2 in the vertical line 1-.

以下、第2図を第3図のタイミング図と合せて説明する
。なお、第2図の入出力線と第3図のタイミング図の番
号とを同一にして示しである。
Below, FIG. 2 will be explained together with the timing diagram of FIG. 3. Note that the input/output lines in FIG. 2 and the timing chart in FIG. 3 are shown with the same numbers.

まず、キーやリモコンによる映像切換え人ノコが入った
とき、キー/リモコン処理部2によりミュート指令信号
dを映像ミュート回路1に入れるとともに、数10m5
ecの遅延をさせて映像切換え信号すを映像選択回路3
へ出力し、入力信号の切換えをしている。映像選択回路
3は選択後信号aを映像出力回路4に出力するととにも
、常に映像ミュート回路1へ垂直同期パルスCを送出す
るようにしている。
First, when a video switching power saw is input using a key or remote control, the key/remote control processing unit 2 inputs a mute command signal d to the video mute circuit 1, and at the same time, several tens of m5
The video selection circuit 3 delays the ec and outputs the video switching signal.
output to the input signal and switch the input signal. The video selection circuit 3 outputs the selected signal a to the video output circuit 4, and also always sends a vertical synchronization pulse C to the video mute circuit 1.

また、映像ミューI・解除は、映像切換え後100〜2
00m5ec後に解除するようにしており、解除後にも
映像ミュート出力パルスfは垂直同期パルスCに同期さ
せて解除するよう構成している。
Also, video mu I/cancellation is 100~2 after video switching.
The video mute output pulse f is configured to be released in synchronization with the vertical synchronization pulse C even after release.

以上の映像ミュート出力パルスfを映像出力回路4に加
えることにより映像出力波形は第3図gからもわかるよ
うにノイズや同期部れのない映像の切換えを行なうこと
ができる。
By applying the above-described video mute output pulse f to the video output circuit 4, the video output waveform can be switched without noise or synchronization deviation, as can be seen from FIG. 3g.

なお、第2図の5の部分はマイクロコンピュータ等を使
用して行なうことができる。
Note that the part 5 in FIG. 2 can be performed using a microcomputer or the like.

発明の効果 以上の実施例から明らかなように、本発明の映像ミュー
ト回路は簡単なタイミング処理を入れることにより、高
音質、高画質化の技術動向の中、見落とされがちな映像
切換え時の品位を高めることができ、同期信号の異なる
映像信号の切換えにおいても、同期の乱れや、ミュート
がかからない期間等の不都合が発生しない映像ミュート
回路を提供できる。
Effects of the Invention As is clear from the above embodiments, the video mute circuit of the present invention incorporates simple timing processing to improve the quality of video switching, which is often overlooked amid technological trends toward higher sound quality and higher image quality. It is possible to provide a video muting circuit that can increase the performance of video signals and that does not cause problems such as disturbances in synchronization or periods in which muting is not applied even when switching between video signals with different synchronization signals.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の映像ミュート回路の構成図、第2図は
第1図の映像ミュート回路を含む全体構成図、第3図は
各入出力端子のタイミング図である。 1・・・・・・映像ミュート回路、1−1・・・・・・
映像ミュート発生部、1−2・・・・・・同期部、C・
・・・・・垂直同期パルス、d・・・・・・ミュート指
令信号、e・・・・・・映像ミュートパルス、r・・・
・・・映像ミュート出力パルス。
FIG. 1 is a block diagram of the video mute circuit of the present invention, FIG. 2 is a diagram of the entire configuration including the video mute circuit of FIG. 1, and FIG. 3 is a timing diagram of each input/output terminal. 1...Video mute circuit, 1-1...
Video mute generation section, 1-2...Synchronization section, C.
...Vertical synchronization pulse, d...Mute command signal, e...Video mute pulse, r...
...Video mute output pulse.

Claims (4)

【特許請求の範囲】[Claims] (1)テレビジョン受信機のチャンネル切換え時に映像
ミュート信号を出力する映像ミュート信号発生手段と、
上記映像ミュート信号を垂直同期信号と同期させるため
の同期手段とを備えたことを特徴とする映像ミュート回
路。
(1) video mute signal generating means for outputting a video mute signal when switching channels of a television receiver;
A video mute circuit comprising: synchronization means for synchronizing the video mute signal with a vertical synchronization signal.
(2)映像ミュート信号の立上りが、映像信号の垂直ブ
ランキング期間であることを特徴とする請求項1記載の
映像ミュート回路。
(2) The video mute circuit according to claim 1, wherein the rising edge of the video mute signal occurs during a vertical blanking period of the video signal.
(3)映像ミュート信号の立下りが、映像信号の垂直ブ
ランキング期間であることを特徴とする請求項1記載の
映像ミュート回路。
(3) The video mute circuit according to claim 1, wherein the falling edge of the video mute signal is a vertical blanking period of the video signal.
(4)同期の異なる映像信号を切換える場合に、切換え
前の映像信号の垂直ブランキング期間に映像ミュート信
号が立上り、切換え後の映像信号の垂直ブランキング期
間に映像ミュート信号が立下るようにしたことを特徴と
する請求項1記載の映像ミュート回路。
(4) When switching video signals with different synchronization, the video mute signal rises during the vertical blanking period of the video signal before switching, and falls during the vertical blanking period of the video signal after switching. The video mute circuit according to claim 1, characterized in that:
JP30512290A 1990-11-09 1990-11-09 Picture mute circuit Pending JPH04176277A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30512290A JPH04176277A (en) 1990-11-09 1990-11-09 Picture mute circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30512290A JPH04176277A (en) 1990-11-09 1990-11-09 Picture mute circuit

Publications (1)

Publication Number Publication Date
JPH04176277A true JPH04176277A (en) 1992-06-23

Family

ID=17941368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30512290A Pending JPH04176277A (en) 1990-11-09 1990-11-09 Picture mute circuit

Country Status (1)

Country Link
JP (1) JPH04176277A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06149181A (en) * 1992-11-02 1994-05-27 Nippondenso Co Ltd Video displaying device
JPH09219843A (en) * 1996-02-09 1997-08-19 Matsushita Electric Ind Co Ltd Television picture display device
JPH11202834A (en) * 1998-01-08 1999-07-30 Sony Corp Liquid crystal display device
JP2000078487A (en) * 1998-08-31 2000-03-14 Matsushita Electric Ind Co Ltd Video signal switching device
JP2012505488A (en) * 2008-10-13 2012-03-01 アップル インコーポレイテッド Seamless display transition

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5535508A (en) * 1978-09-05 1980-03-12 Hitachi Ltd Bright line erasing signal generating circuit at channel switch-over time
JPS59153387A (en) * 1983-02-21 1984-09-01 Sony Corp Channel selecting circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5535508A (en) * 1978-09-05 1980-03-12 Hitachi Ltd Bright line erasing signal generating circuit at channel switch-over time
JPS59153387A (en) * 1983-02-21 1984-09-01 Sony Corp Channel selecting circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06149181A (en) * 1992-11-02 1994-05-27 Nippondenso Co Ltd Video displaying device
JPH09219843A (en) * 1996-02-09 1997-08-19 Matsushita Electric Ind Co Ltd Television picture display device
JPH11202834A (en) * 1998-01-08 1999-07-30 Sony Corp Liquid crystal display device
JP2000078487A (en) * 1998-08-31 2000-03-14 Matsushita Electric Ind Co Ltd Video signal switching device
JP2012505488A (en) * 2008-10-13 2012-03-01 アップル インコーポレイテッド Seamless display transition
JP2013225330A (en) * 2008-10-13 2013-10-31 Apple Inc Seamless display migration

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