JPH04130281A - Memory ic tester - Google Patents

Abstract

PURPOSE:To enable entire region of a ROM to be tested with one operation by providing a switching means for selecting between a ROM data reading mode and a ROM test mode. CONSTITUTION:A value is set to an address and both final address registers of a ROM control signal generation circuit 15 depending on the type of ROM for test. When a ROM data reading mode is selected, a switching circuit 9 turns on an address bus of a master ROM 2 and a control signal line 6 and the ROM 2 data is stored in a memory for ROM data 12. Then, when it is detected that values of a lower address bus and a control signal line 10 and contents of a final address register of the circuit 15 are equal by a comparator circuit, test mode is selected. After that, the address bus of the ROM 2 and the line 6 are turned off by the circuit 9, the address bus of the ROM 1 for test and a control signal line 5 are turned on, data is transferred to a data comparator circuit 14 through a data bus 3 from the ROM 1 and is compared with data which is transferred from the memory 12 through a bus for data 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to IC testing) and relates to a memory IC tester that tests the entire area of a large capacity ROM with 4 IK less memory for ROM data.

[Conventional technology]

Conventional memory IC testers cannot test in - times unless they have a ROM data memory with the same amount of data as the test ROM, so they divide the master ROM data according to the size of the ROM data memory. The conventional methods were to download and test the data, or to assess the master ROM and test ROM at the same time and compare the data.

[Problem to be solved by the invention]

In the conventional memory IC tester division method described above, the ROM test is performed by downloading data according to the capacity of the tester's ROM data memory, but since only the downloaded area can be tested, after testing that area, another There was a problem that it was necessary to download the data of the area and perform the ROM test several times over and over again, and the test took a long time.

Furthermore, if the capacity of the tester's ROM data memory is increased so as not to be divided, the ROM data memory is expensive, resulting in a very expensive memory IC tester. Furthermore, in the method of comparing with the master ROM,
Even if an attempt was made to determine the limit of C4I characteristics, there was a problem in that it could not be measured because the master ROM also had a similar limit.

[Means to solve the problem]

The memory IC tester of the present invention includes a signal line for accessing all addresses of the master ROM and test ROM, a switching circuit connected to this signal line for switching the signal lines of the master ROM and test ROM, and It comprises a ROM set area, a ROM data memory smaller in data capacity than the test ROM, and a switching means for switching between a ROM data download mode and a ROM test mode.

[Effect]

In the present invention, a master ROM is used, and R
Add an address higher than the OM data memory and use the RO
By having a switching means that can switch between the M data download mode and the test mode, even if the ROM data memory is small, the entire ROM area can be tested with -1 operations.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, 1 is a test ROM, 2 is a data downloading master ROM, and this master ROM 2 has a master ROM set area. 3 is RO for testing
M1 data bus, 4 is master ROM for data downloading
2 is a data bus, 5 is an address bus and control signal line of the test ROM 1, and 6 is an address bus and control signal line of the master ROM 2.

7 is a control unit (control circuit) of the memory IC tester, 8 is a signal line that controls each function of the tester;
constitutes a switching means for switching between a ROM data downloading mode and a ROM test mode. 9 is RO for testing
This switching circuit 9 switches the address bus and control signal line of M1 and master ROM2, and this switching circuit 9 is configured to switch the signal line of master ROM2 and test ROM1.

10 is a lower address bus and a control signal line (address bus), 11 is this lower address bus and a control signal line 1
0 upper address bus (address bus), which constitute a signal line for accessing all addresses of the master ROM 2 and the test ROM 1. 12 is a memory for ROM data whose data capacity is smaller than the data capacity of the test ROM 1, 13 is a data path stored in this ROM data memory 12, 14 is a data comparison circuit between the test ROM 1 and the ROM data memory 12, and 15 is an address. and R.O.
In the M control signal generation circuit, the start address register and R
It has a final address register for the OM data memory, a final address register for the test ROM, and a comparison circuit for both final address registers.

16 is a signal line for sending the result of the data comparison circuit 14 to the control circuit 7 which is a control section of the memory IC tester; 1T is the memory IC tester; 18 is a test end signal line.

Figure 2 is a flowchart for explaining the operation of Figure 1.
In each step 101 to 110, a predetermined process is executed.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

First, the control unit (control circuit) T of the memory IC tester 1T sets the start address register of the address and ROM control signal generation circuit 15 to the data siphoning start address "0" of the master ROM 2 (step 101).
), set values in both the address and final address registers of the ROM control signal generation circuit 15 by a program according to the type of test ROM, and set the values in the R shown in step 102.
When the OM data download mode is set, the address bus and control signal line switching circuit 9 of the test ROM and master ROM turns on the address bus and control signal line 6 of the master ROM 2, and when counting up from the start address, the master ROM The data in the ROM 2 passes through the data bus 4 and is stored in the ROM data memory 12 (
(See steps 103 and 104).

When the comparison circuit detects that the values of the lower address bus and control signal line 10 are the same as the address and the contents of the final address register of the ROM data memory of the ROM control signal generation circuit 15 (see step 105), the test mode is entered. The start address register of the sear address and ROM control signal generation circuit 15 becomes "0".

After that, the address bus and control signal line 6 of the master ROM 2 are turned OFF by the switching circuit 9 that switches the address and control signal lines, and the address bus and control signal line 5 of the test ROM 1 are turned ON, thereby starting the ROM test. When you start and count up from the start address,
From the test ROM1 through the data bus 3 to the test RO
Data comparison circuit 14 between M1 and ROM data memory 12
The data is transferred to and tested by comparing it with the data transferred from the ROM data memory 12 through the data bus 13, and the value and address of the lower address bus 10 and the ROM data of the ROM control signal generation circuit 15 are tested. When the comparison circuit detects that the contents of the final address registers of the test memory are the same (see step 108), if the test result is not a bus (see step 109), it is determined to be a defective product, and an end signal is sent through the test end signal line 18. is sent to the control section (control circuit) 7 of the memory IC tester, and the test is completed.

Next, as a result of the test, the address bus 10 of the bus
When the comparison circuit detects that the values of the address bus 11 and the contents of the final address register of the test ROM of the ROM control signal generation circuit 15 are the same (see step 109), the entire area of the ROM has been tested. The completion signal memory I is passed through the test completion signal line 18.
The test is completed and the product is determined to be non-defective.

Additionally, the address bus and ROM control signal generation circuit 15
If the content is different from the final address register of the test ROM, when the ROM control signal generation circuit 15 counts up the address, the address bus 10 and the address bus 11 are logically continuous, so the address bus 1
1 is counted up and the address value is set as the start address (see step 110).

Therefore, the test area of the test ROM 1 is changed.

However, the address bus 11 is connected to the ROM data memory 12.
Therefore, the data downloaded from the i-star ROM 2 is transferred to the ROM data memory 12, the data is rewritten, and a ROM test is performed.

Then, the ROM test is performed until the final address of the test ROM 1 is reached by repeating the same process.

〔Effect of the invention〕

As explained above, the present invention utilizes a master ROM,
Furthermore, by adding an address higher than the ROM data memory and having a switching means that can switch between the ROM data download mode and the test mode, even if the ROM data memory is small, the entire ROM area can be accessed with just one operation. This has the effect of realizing an inexpensive memory IC tester that can perform tests.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation of FIG. 1...Test ROM, 2...Master ROM for data download, 8...Signal line to control each function of the tester, 9...1 Test and master ROM address bus and control. Signal line switching circuit, 10...
Lower address bus and control signal line, 11... Upper address bus of lower address bus and control signal line, L
2...Memory for ROM data. Patent applicant: NEC Corporation

Claims (1)

[Claims] a signal line for accessing all addresses of the master ROM and the test ROM; a switching circuit connected to this signal line for switching the signal lines of the master ROM and the test ROM; a set area of the master ROM; A memory IC tester comprising a ROM data memory smaller than the data capacity of the ROM, and a switching means for switching between a ROM data download mode and a ROM test mode.