JPH04111032A - Multiplexed storage device - Google Patents

Abstract

PURPOSE:To return to normal multiplexed configuration without stopping access performed by a CPU by performing access to a memory by the CPU and access to the memory for maintaining the multiplexed configuration by using first and second independent ports. CONSTITUTION:The CPU accesses and processes data in a tripled storage device 1. This tripled storage device 1 is equipped with three memories 2-4, read majority circuit 5 and memory comparison/correction circuit 8. The three memories respectively have first ports 21, 31 and 41 and second ports 22, 32 and 42 and access from the port is respectively independently performed. When the majority circuit 5 detects an erroneous data, the memory comparison/correction circuit 6 writes a data in the address of the other memory to the address of the memory. Thus, there is no adverse influence upon the processing time of the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to a multiplexed storage device in which storage devices are multiplexed for a computer system.

(Prior Art) As a method of increasing system reliability, multiplexing is used to increase redundancy by arranging identical functional units in multiple ways. This method includes redundancy, which detects failures by arranging the same functional units in duplicate and comparing the outputs of each functional unit, and arranging the same functional units in triplicate, which detects failures by comparing the outputs of each functional unit. There is triplexing, which masks a failure in one functional unit and detects a failed functional unit by outputting . Of these, triplexing is widely used because redundancy makes it impossible to identify a failed functional unit.

In the triplexing of storage devices in computer systems, memories are arranged in triplicate, and when a central processing unit (CPU) performs a data write operation, a write block is written into three memories at the same time. Also, during a read operation, data is read from three memories at the same time, these three data are compared by majority vote, and a large number of data as a result of comparison, that is, three
Two or more of the same pieces of data that have been read out are transferred to a central processing unit (CPU) as correct storage contents. Furthermore, a memory from which a small number of data is read in the comparison based on the majority decision, that is, data different from the other two memories, is considered to be a faulty memory.

If a failure occurs in one of the memories, it is possible to continue processing based on the storage contents of the other two memories, but the configuration is equivalent to duplication, so if the two read data are different, It becomes impossible to continue processing, and the computer system will stop. Therefore, in order to prevent the computer system from stopping, it is necessary to immediately return to the triplex configuration after a failure occurs.

However, in conventional triplex storage devices, when a fault occurs in one of the three memories, in order to return to the triplex configuration, it is necessary to replace the faulty memory with the other two.
It is necessary to perform a restoration operation by copying the contents of normal memory. In order to perform this operation, it was necessary to prohibit read/write operations to the storage device by the central processing unit.

(Problems to be Solved by the Invention) As described above, in the conventional multiplexed storage device, if a failure in one memory is detected by data comparison when reading from the CPU, the operation of the CPU is stopped. Since the correct data is written to the memory, there is a drawback that the processing time of the CPU is significantly delayed.

Therefore, an object of the present invention is to provide a multiplexed storage device that does not adversely affect the processing time of the CPU by providing means for comparing and correcting the stored contents of these memories independently of access by the CPU. be.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides at least three memories sequentially assigned the same address, a first access port for accessing these memories by a CPU, a second access port for accessing the memory for error detection;
an error detection means for detecting erroneous data by reading data at the same address in the memory from the second access port and comparing the contents by majority vote; The present invention is characterized by comprising an error correction means for writing data of the address in another memory to the address.

Further, in the present invention, there is provided an error position recording means for recording the memory and address where the error data was detected by the error correction means, and the error detection means again records the address of the memory recorded in the error position recording means. The apparatus is equipped with a failure detection means that notifies that a failure has occurred in the memory when erroneous data is detected, and erases the contents of the error position recording means when no erroneous data is detected. .

(Function) According to the present invention, access to the storage device by the central processing unit and access to the storage device for maintaining the multiplexed configuration are performed using the first and second independent ports, respectively. Therefore, access for maintaining the multiplexed configuration does not interfere with access by the central processing unit. Therefore, it is possible to maintain the memory multiplex configuration without reducing the processing capacity of the computer system.

In addition, when a memory failure occurs, the contents of memory in the alternate memory are restored by treating all the contents of the alternate memory as errors and correcting them according to the contents of other normal memories. There is no need to perform any action.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. This embodiment will be explained using a triplexed storage device as an example.

FIG. 1 is an overall configuration diagram of a computer system, in which a CPU accesses data from a triplexed storage device 1 to perform processing.

FIG. 2 is a detailed block diagram of the triplex storage device 1. As shown in FIG.

Here, the triplexed storage device (1) has three memories (2)
(3) It is composed of (4), a read majority circuit (5), a storage comparison/correction circuit (6), an address counter (7), and an error position recording memory (8).

The three memories each have a first memory for writing and reading.
Boat (21) (31) (41) and second port (
22), (32), and (42), and access from the first port and the second port can be performed independently.

When the central processing unit writes data to the triplex storage device (1), the same data is written to the memory (2) (3).
For (4), the first boat of each memory (21) (31)
(41) Write simultaneously. In addition, the central processing unit reads data from the triplex storage device using the ports (21) (31) of the memory (2) (3) (4).
The data read from (41) is given to the read majority circuit (5), and in this read majority circuit, 3
The value based on the majority vote of the two data is returned to the central processing unit as the stored content.

The following configuration requirements exist as those that operate independently of these.

First, the address counter counts from the first address to the last address of the memory (2), (3), and (4) under the control of the memory comparison and correction circuit (6), and after reaching the last address, the counting is repeated from the first address.

The error position recording memory (8) is the memory (2> (3)
It has an address space of the same size as (4), and records whether or not an error has occurred at each address and the memory in which the error has occurred. FIG. 3 is a diagram showing an example of the recorded contents.

The memory comparison and correction circuit (6) selects the second ports (22) of the three memories according to the address indicated by the address counter (7).
(32) Load data from (42) and
It is checked by referring to the error memory recording memory (8) whether there is any memory in which an error has occurred at this address in the past. Compare the three read data, and if all data are the same, there is no error,
The fact that there is no memory in which an error has occurred is recorded in the error position recording memory (8). Further, when two pieces of data that are the same and one piece of data that is different are read, these two pieces of data are treated as correct data, and the other piece of data is treated as error data. If an error has occurred in the past in the memory from which the error data was read, or if it is recorded in the error location recording memory (8), the user is notified that this memory is a faulty memory.

(The user follows this notification and replaces the memory with a new memory. During this time, the CPU accesses the other two memories.) If no errors have occurred in the past, write correct data to this memory and correct it. At the same time, the fact that an error has occurred in this memory is recorded in the error position recording memory.

When making a correction, the data at the corresponding address is read from the other two normal memories and written to the corresponding address in the error memory.

After this, the address counter (7) is counted up,
Repeat the comparison/correction operation for the next address.

If no error data is detected for a certain period of time in a memory in which an error has occurred and is recorded in the error location recording memory, the error contents of the error location recording memory are erased.

When the faulty memory is replaced with a substitute memory, all the stored contents of the substitute memory are deemed to be errors by the subsequent comparison operation of the memory comparison and correction circuit (6>), and are all corrected by the above-mentioned correction operation. As a result, after the value of the address counter (7) has gone around once, the restoration of the stored contents in the alternative memory is completed.

Although the present invention has been described using three memories, the present invention can also be applied to four or more memories. In this case, an odd number such as 5 or 7 is preferable because it facilitates error detection by majority vote.

[Effects of the Invention] According to the present invention, even if error data or a failure is detected in a specific memory in a multiplexed storage device, it is possible to restore the normal multiplexed configuration without stopping access by the CPU. Therefore, the processing power of the computer system can be greatly improved.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a computer system, FIG. 2 is a configuration diagram of a multiplexed storage device according to an embodiment of the present invention, and FIG. 3 is a diagram showing the contents of an error position recording memory. DESCRIPTION OF SYMBOLS 1... Triple storage device, 2.3.4... Memory, 21, 31.41... 1st port, 22, 82.42... 2nd port, 5... Read majority circuit, 6... Memory comparison/correction circuit, 7... Address counter, 8... Error position recording memory.

Claims (3)

[Claims] (1) At least three memories each having the same address, a first access port for accessing these memories from the CPU, and a first access port for accessing the memories for error detection. 2 access ports,
an error detection means for detecting erroneous data by reading data at the same address in the memory from the second access port and comparing the contents based on a majority decision; 1. A multiplexed storage device comprising: error correction means for writing data at an address in another memory into an address. (2) error position recording means for recording the memory and address where the error data was detected by the error correction means; and error data detected again by the error detection means in the memory recorded in the error position recording means; 2. The multiplexed storage device according to claim 1, further comprising failure detection means for notifying that a failure has occurred in said memory when a failure occurs in said memory. (3) The failure detection means erases the contents of the error position recording means if no error data is detected by the error detection means for a certain period of time in the memory recorded in the error position recording means. 3. The multiplexed storage device according to claim 2.