JPH0390283U

JPH0390283U -

Info

Publication number: JPH0390283U
Application number: JP15132889U
Authority: JP
Priority date: 1989-12-28
Filing date: 1989-12-28
Publication date: 1991-09-13

Description

[Brief explanation of drawings]

第１図は本考案に係るテスト信号発生装置の第
１の構成を示すブロツク図、第２図は第１図の主
要部の信号波形図、第３図は本考案の第２の構成
を示すブロツク図、第４図および第５図は第２の
構成を主要部の信号波形図、第６図は本考案の第
３の構成を示すブロツク図、第７図および第８図
は第２の構成の主要部の信号波形図、第９図は本
考案のテスト信号発生装置の使用態様を説明する
ブロツク図、第１０図は一般的なパソコンの構成
を示す概略図である。１……パソコン本体、３……画像表示装置（Ｃ
ＲＴデイスプレイ装置）、７……基準信号発生回
路（発振器）、９，２９……水平同期信号作成回
路、１１，３７，５７……垂直同期信号作成回路
、１３，１７，３１〜３９，５９〜６３……分周
器、１５，１９〜２３，４３，４５，５３，５５
，６７〜７１……デユーテイー変換回路、２５，
４７〜５１，７３〜７７……ＡＮＤ回路、２７，
４１，６５……テスト信号作成回路、７９……信
号ライン、８１……同期信号検出回路、８３……
切換え回路、Ａ……テスト信号発生装置。 FIG. 1 is a block diagram showing the first configuration of the test signal generator according to the present invention, FIG. 2 is a signal waveform diagram of the main part of FIG. 1, and FIG. 3 is a second configuration of the present invention. 4 and 5 are signal waveform diagrams of the main parts of the second configuration, FIG. 6 is a block diagram showing the third configuration of the present invention, and FIGS. 7 and 8 are diagrams of the second configuration. FIG. 9 is a block diagram illustrating how the test signal generator of the present invention is used, and FIG. 10 is a schematic diagram showing the configuration of a general personal computer. 1...PC body, 3...Image display device (C
RT display device), 7... Reference signal generation circuit (oscillator), 9, 29... Horizontal synchronization signal generation circuit, 11, 37, 57... Vertical synchronization signal generation circuit, 13, 17, 31-39, 59- 63... Frequency divider, 15, 19 to 23, 43, 45, 53, 55
, 67-71...Duty conversion circuit, 25,
47-51, 73-77...AND circuit, 27,
41, 65...Test signal generation circuit, 79...Signal line, 81...Synchronization signal detection circuit, 83...
Switching circuit, A...Test signal generator.

Claims

[Claims for Utility Model Registration] (1) A reference signal generation circuit that generates a reference signal; a horizontal synchronization signal generation circuit that divides the frequency of the reference signal to generate a horizontal synchronization signal; a vertical synchronization signal generation circuit that creates a vertical synchronization signal using the horizontal and vertical synchronization signal generation circuits, and creates horizontal and vertical blanking periods from the frequency-divided signals in the horizontal and vertical synchronization signal generation circuits, and generates a test video signal during periods other than these blanking periods. A test signal generating device comprising: a test signal generating circuit for generating; (2) a reference signal generation circuit that generates a reference signal; and a circuit that divides the reference signal by different division numbers to output a plurality of divided signals, and outputs a plurality of divided signals by dividing the frequency by the maximum division number. a horizontal synchronization signal creation circuit that creates a horizontal synchronization signal; a vertical synchronization signal creation circuit that divides the frequency of the reference signal to create a vertical synchronization signal; and a maximum frequency division signal of the horizontal synchronization signal creation circuit and the vertical synchronization signal. Creating horizontal and vertical blanking periods from the frequency-divided signals of the creation circuit, and in periods other than these blanking periods and the ON or OFF period of each of the plurality of frequency-divided signals from the horizontal synchronization signal creation circuit, A test signal generation device comprising: a test signal generation circuit that generates a test video signal for each of the plurality of frequency-divided signals. (3) a reference signal generation circuit that generates a reference signal; a horizontal synchronization signal generation circuit that divides the frequency of the reference signal to create a horizontal synchronization signal; a vertical synchronization signal generation circuit that outputs a frequency division signal and creates a vertical synchronization signal with a frequency division signal divided by a maximum frequency division number; a maximum frequency division signal of the vertical synchronization signal generation circuit and the horizontal synchronization signal; Creating vertical and horizontal blanking periods from the frequency-divided signals of the creation circuit, and turning on each of these blanking periods and the plurality of frequency-divided signals from the vertical synchronization signal creation circuit.
Alternatively, a test signal generation device comprising: a test signal generation circuit that generates a test video signal for each of the plurality of frequency-divided signals during a period other than the OFF period.