JPS60142860U - Time base correction circuit - Google Patents
Time base correction circuitInfo
- Publication number
- JPS60142860U JPS60142860U JP2964484U JP2964484U JPS60142860U JP S60142860 U JPS60142860 U JP S60142860U JP 2964484 U JP2964484 U JP 2964484U JP 2964484 U JP2964484 U JP 2964484U JP S60142860 U JPS60142860 U JP S60142860U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- delay elements
- response delay
- human
- correction circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
- H04N5/93—Regeneration of the television signal or of selected parts thereof
- H04N5/95—Time-base error compensation
- H04N5/953—Time-base error compensation by using an analogue memory, e.g. a CCD shift register, the delay of which is controlled by a voltage controlled oscillator
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Signal Processing For Recording (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来の時間軸補正回路を示す図、第２図は、
本考案の一実施例を示す図、第３図は、クロックの波形
を示す図、第４図、第５図および第６図は、第２図の実
施例の動作を説明するための波形図である。
主要部分の符号の説明、３．９，１０・・・・・・ＣＣ
Ｄ、４・・・・・・ＶＣｏ、 ５・・・・・・タイム
ベースエラー検出器、６・・・・・・ビデオ検波器、７
・・曲オーディオ検波器、８・・・・・・時間軸補正回
路、１１・・曲切換スイッチ、１２・・・・・・インバ
ータ。Figure 1 is a diagram showing a conventional time axis correction circuit, and Figure 2 is a diagram showing a conventional time axis correction circuit.
A diagram showing one embodiment of the present invention, FIG. 3 is a diagram showing clock waveforms, and FIGS. 4, 5, and 6 are waveform diagrams for explaining the operation of the embodiment of FIG. 2. It is. Explanation of symbols of main parts, 3.9, 10...CC
D, 4... VCo, 5... Time base error detector, 6... Video detector, 7
... Song audio detector, 8 ... Time axis correction circuit, 11 ... Song selection switch, 12 ... Inverter.
Claims (2)
記第１人力信号と同一のタイムベースエラーを有しかつ
前記第１人力信号の周波数帯域における最高周波数の１
７２以下の最高周波数を含む第２人力信号とを時間軸補
正する間開軸補正回路であって、前記第１人力信号が供
給されるそれぞれＮ段の第１および第２クロツク応答遅
延素子と、第２人力信号が供給されるＮ段の第３クロツ
ク応答遅延素子と、第１、第２および第３クロツク応答
遅延素子に供給されるクロックパルスを発生する１個の
クロック発生器と、前記第１および第２クロツク応答遅
延素子を等測的に前記クロック発生器の発生するクロッ
クパルスの周波数の２倍の周波数のクロックパルスで駆
動させる駆動手段とを備えたことを特徴とする時間軸補
正回路。(1) a first human-powered signal having a time base error; and one having the same time-base error as the first human-powered signal and having the highest frequency in the frequency band of the first human-powered signal.
an open-axis correction circuit for time-base correcting a second human input signal having a highest frequency of 72 or less, each of N stages of first and second clock response delay elements to which the first human input signal is supplied; N stages of third clock response delay elements supplied with a second human input signal; one clock generator generating clock pulses supplied to the first, second and third clock response delay elements; and a driving means for driving the first and second clock response delay elements equimetrically with a clock pulse having a frequency twice that of the clock pulse generated by the clock generator. .
ックパルスを反転して前記第１および第２クロツク応答
遅延素子の一方に供給するインバータと、前記クロック
発生器からのクロックパルスにより制御され前記第１お
よび第２クロツク応答遅延素子の出力を交互に切換える
切換スイッチとにより構成したことを特徴とする実用新
案登録請求の範囲第１項に記載の時間軸補正回路。(2) The drive means is controlled by an inverter that inverts a clock pulse from the clock generator and supplies it to one of the first and second clock response delay elements; 2. The time base correction circuit according to claim 1, further comprising a changeover switch that alternately switches the outputs of the first and second clock response delay elements.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2964484U JPS60142860U (en) | 1984-02-29 | 1984-02-29 | Time base correction circuit |
| DE19853506960 DE3506960A1 (en) | 1984-02-29 | 1985-02-27 | TIME BASE CORRECTION |
| GB08505170A GB2156626A (en) | 1984-02-29 | 1985-02-28 | Time base correction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2964484U JPS60142860U (en) | 1984-02-29 | 1984-02-29 | Time base correction circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60142860U true JPS60142860U (en) | 1985-09-21 |
Family
ID=12281800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2964484U Pending JPS60142860U (en) | 1984-02-29 | 1984-02-29 | Time base correction circuit |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS60142860U (en) |
| DE (1) | DE3506960A1 (en) |
| GB (1) | GB2156626A (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7210324A (en) * | 1972-07-26 | 1974-01-29 | ||
| US4090215A (en) * | 1976-10-01 | 1978-05-16 | Basf Aktiengesellschaft | Electronic time base error correction methods and arrangements |
| JPS57197982A (en) * | 1981-05-29 | 1982-12-04 | Pioneer Video Corp | Time base correcting device for recorded information reproducing device |
-
1984
- 1984-02-29 JP JP2964484U patent/JPS60142860U/en active Pending
-
1985
- 1985-02-27 DE DE19853506960 patent/DE3506960A1/en not_active Ceased
- 1985-02-28 GB GB08505170A patent/GB2156626A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| DE3506960A1 (en) | 1985-10-03 |
| GB8505170D0 (en) | 1985-04-03 |
| GB2156626A (en) | 1985-10-09 |
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