JPH0381180B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a memory control method for controlling memory connected to a bus of a central processing unit (CPU).

Conventional configuration and its problems FIG. 1 shows an example of a typical conventional memory configuration connected to a CPU bus. In FIG. 1, 1 is a CPU, 2 is a memory, and 3 is a chip selection circuit. A chip selection signal for selecting memory 2 is normally generated from the upper bits of the address bus signal output from CPU 1. When memory 2 is selected by chip selection circuit 3, CPU 1
A specific address in memory 2 is selected by the address bus signal output by the
When R/W=0 due to write signal R/W,
The contents of the data bus signal output from CPU1 are
Write. When R/W=1, the contents of the selected address in memory 2 are output onto the data bus of CPU 1, and CPU 1 reads them.

In the configuration of this conventional example, the capacity of the memory 2 is determined by the memory capacity required by the device. On the other hand, with the rapid development of the semiconductor field, the capacity of memory elements is increasing. In order to reduce the number of pins of a package that houses a memory element, each address is made up of one bit, and the capacity increases in the direction of the address. For example, if eight memory elements each having 64K addresses and each address consists of 1 bit (expressed as 64K x 1) are used in parallel, a memory with a capacity of 64K bytes (64K x 8) can be realized. However, in many cases, terminal devices and the like do not require a memory capacity of 64K bytes. or
It is desirable to be able to expand the capacity in relatively small units of 8K bytes. However, it is difficult to use a memory element having a large capacity in the address direction with the conventional configuration.

Purpose of the Invention The present invention uses a memory element that has a relatively large capacity in the address direction, such as (64K x 1), and each address consists of 1 bit.
The purpose of this is to reduce the number of elements by using it as a 8×8) memory.

Structure of the Invention The present invention provides a parallel-to-serial converter for writing and a serial-to-parallel converter for reading between the CPU bus and the memory.
x8) or (16K x 4).

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings. In Figure 2, 20 is the CPU,
21 is a memory, 23 is a chip selection circuit, 24 is a timing generator, 25 is an external address generator, 2
6 is a CPU clock generator, 27 is a parallel-serial converter, 28 is a serial-parallel converter, 29 is a bus control circuit A, and 30 is a bus control circuit B. The data bus signal of the CPU 20 is 8 bits in parallel (D0 to D7), and the address bus signal is
Assume that it is composed of parallel 16 bits A0 to A15.

The operation when the CPU 20 writes data to the memory 21 will be explained. Upper bits A13 to A of the address bus signal output from the CPU 20
15 is determined by the chip selection circuit 23, and the memory 21
Determine whether you have selected If the address signal indicates a predetermined address for the memory 21, the chip selection circuit 2
3 is a selection signal sent to the timing generator 24.
Output SEL. The timing generator 24 generates a load signal to the parallel-to-serial converter (8-bit configuration in this case) 27 based on the selection signal SEL.
LD and writes the data bus signal (write data) output by the CPU 20 to the parallel-serial converter 27. In the memory 21,
Address bus signals A0 to A12 of the CPU 20 and an external address signal (3 bits) of the external address generator 25 are added as address signals.
Since the external address signal is reset by the load signal LD, its initial value is 0. Next, the timing generator 24 outputs a chip selection signal MCS to the memory 21. CPU20 is read/
Write signal R/W to write mode (R/W=
φ). Therefore, the contents of the output WD of the parallel-to-serial converter 27 are written to the address indicated by the address signal applied to the memory 21. Output WD of parallel-serial converter 27
The LSB is out. In this state, the output WD
corresponds to the data bus signal Dφ of the CPU 20.

Next, the timing generator 24 outputs the count-up signal CPU to the external address generator 25,
Advance the external address signal by one. Subsequently, the timing generator 24 outputs the shift signal SHP to the parallel-serial converter 27. shift signal
When SHP is added, parallel-to-serial converter 2
The contents of 7 are each shifted one bit from the MSB towards the LSB. Therefore, the output WD is
It corresponds to D1 of the data bus signal of the CPU 20. In this state, the address signal of the memory 21 is advanced by one by the external address signal, and the output WD of the parallel-serial converter 27 is written at the address indicated by the address signal. In this way, the timing generator 24 adds the count-up signal CUP to the external address generator 25, advances the external address signal one by one, and causes the shift signal SHP to advance.
By adding to the parallel-serial converter 27, the output WD is changed to the higher-order content by 1 bit,
Write to memory 21. WD this write operation
The output of the CPU 20 becomes the content of the data bus signal D7 of the CPU 20, and the content of the data bus signal of the CPU 20 is written to the memory 21 by repeating the process until the output WD is written to the memory 21.

FIG. 3 shows a timing chart in a write operation.

Next, the operation when the CPU 20 reads data from the memory 21 will be described.

Similar to the write operation, the upper bits A13~ of the address bus signal output from the CPU 20
A15 is determined by the chip selection circuit 23, and the memory 2
Determine whether 1 is selected. If selected, the chip selection circuit 23 outputs a selection signal SEL to the timing generation section 24. The read/write signal R/W of the CPU 20 is in read mode (R/W=1). The timing generator 24 outputs a load signal LD to the external address generator 25 in response to the selection signal SEL,
Reset external address signal.

Next, the timing generator 24 outputs a chip selection signal MCS to the memory 21. The memory 21 is set to read/write by the chip selection signal MCS.
Since the write signal R/W is in the read mode, the contents of the address indicated by the address signal are output as output data RD. The output data RD is output from the serial-parallel converter 28 (8-bit configuration in this case).
It is connected to the input terminal of the timing generator 24, and is taken into the MSB of the serial-to-parallel converter 28 by the shift signal SHP of the timing generator 24. When this operation is completed, the timing generator 24 outputs the count-up signal CUP to the external address generator 25, and advances the external address signal by one. memory 21
Since the address signal added to advances by one, the contents of the next address are output as output data RD. Subsequently, the timing generator 24 outputs the shift signal SHP to the serial-parallel converter 28.
The parallel-to-serial converter 28 converts the shift signal
When SHP is added, the output data is shifted by one bit from MSB to LSB, and at the same time, the output data is
Import the contents of RD into MSB. In this read operation, the external address signal is set to 7, and the output data RD at that address is the MSB of the serial-parallel converter 28.
Repeat until it is incorporated. When this operation is completed, the contents of the serial-to-parallel converter 28 have the same bit positions as the contents written from the data bus signal of the CPU 20 to the parallel-to-serial converter 27 during the write operation. (CPU2
The contents of the data bus signal D7 of 0 correspond to the MSB of each of the parallel-serial converter 27 and the serial-parallel converter 28. ) In the memory configuration of the present invention, when the CPU reads/writes the memory, it reads/writes the memory element multiple times, so within the period of the CPU clock _φ2 ,
The operation does not end. To solve this problem, we will discuss the case of using Motorola's MC6800 series CPU with an external clock.

In Figure 4, φ ₁ and φ ₂ are CPU clocks,
φ ₁ S and φ ₂ S are the reference clock cycles of the CPU.

In FIG. 2, when the CPU 20 performs a read/write operation on the memory 21, the timing generator 24 outputs a phase control signal FC to the CPU clock generator 26. CPU clock generator 26
is the CPU clock _φ2 due to the phase control signal FC.
is a continuous waveform until the next φ ₂ S, and φ ₁ is not output while φ ₂ is valid. Phase control of φ ₁ and φ ₂ is performed for a period required for read/write operations of the memory 21, and it is also possible to further widen the pulse width of φ ₂ .

For MC6800 series CPUs, the period in which the CPU uses the bus and the period in which it releases it is determined by the CPU's clock _φ2 . Therefore, during a period when the CPU releases the bus (a period other than φ ₂ ), a device other than the CPU (for example, a CRT control element) may use the bus. Moreover, devices other than the CPU,
When it is necessary to use the bus at regular intervals, when reading/writing memory as described above, the CPU
If the pulse width of the clock _φ2 changes, this will cause a disturbance. In order to solve this problem, in Figure 2,
The bus control circuit A29 uses the CPU reference clock _φ2S .
and read/write signal R/W, the CPU operates to use the data bus only during the period φ ₂ S.
The bus control circuit B30 transfers the data read from the memory 21 to the serial-parallel converter 28.
This signal is sent to the data bus for a period of φ ₂ S, and is controlled by the enable signal EN output from the timing generator 24 so that it is in a tri-state state during periods other than φ ₂ S.
During read operation of memory 21, CPU clock _φ2
includes a plurality of φ ₂ S signals, but since the CPU captures the data bus signal at the falling edge of φ ₂ , it does not malfunction.

In the embodiment, the serial-to-parallel converter and the parallel-to-serial converter are each set as one set, but it is clear that the read/write time of the memory can be shortened by preparing two or more sets.

Effects of the Invention The present invention has the above configuration, and according to the present invention, the following effects can be obtained.

1 By using a parallel-to-serial converter and a serial-to-parallel converter to add an address from the outside and read/write multiple times in the address direction of the memory element, the missing number of bits in the word direction can be compensated for. By using a memory element having a large capacity in the address direction, it is possible to configure a memory whose capacity in the address direction is smaller than that of the memory element, and it is possible to realize miniaturization of the device.

2. Since it has a bus control function, devices other than the CPU will not malfunction even if they are connected to the same bus.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing a conventional memory control method, FIG. 2 is a block diagram schematically showing a memory control method according to an embodiment of the present invention, and FIG.
FIG. 4 is an explanatory diagram of the operation of the same embodiment. 20... Central processing unit (CPU), 21... Memory, 23... Chip selection circuit, 24... Timing generator, 25... External address generator, 26...
...Clock generator, 27...Parallel-to-serial converter, 28...Serial-to-parallel conversion, 2
9, 30...Bus control circuit.

Claims (1)

[Scope of Claims] 1. When writing information from the central processing unit 20 to the memory 21, multiple bits of information sent from the central processing unit 20 are converted from parallel to serial, and written to the address sent from the central processing unit 20. The information is stored in the memory 21 using an address to which an external address is added, and when reading information from the memory 21 to the central processing unit 20, the external address added at the time of writing and the address sent from the central processing unit 20 are used. This is a memory control method that reads information from the memory 21, performs serial-parallel conversion, and restores it to multiple bits required by the central processing unit 20. The bus is connected to the central processing unit 20, the bus is disconnected from the central processing unit 20 during the period when the first clock is at a low level, and when the central processing unit 20 accesses the memory 21, the bus is disconnected from the central processing unit 20. The phase of the second clock is controlled so that the leading and trailing ends of the high-level period of the second clock input to the central processing unit 20 overlap with different high-level periods of the first clock. When writing information to the memory 21, the information from the central processing unit 20 is transferred to the parallel-to-serial converter during a period in which the first clock is at a high level at the front end of a period in which the second clock is at a high level. 27 and writes information to the memory 21 while the second clock is at a high level. When reading information from the memory 21 to the central processing unit 20, the second clock is at a high level. Information is read from the memory 21 during the period , and information is read from the serial-to-parallel converter 28 to the central processing unit 20 during the period when the first clock is at the high level at the end of the period when the second clock is at the high level. and other devices connected to the bus other than the central processing unit 20 use the bus at a constant cycle while the first clock is at a low level.