JPH03233740A - Memory access device - Google Patents

Abstract

PURPOSE:To attain the output of packets with the order of input pakets kept as it is by providing plural memory access means, a packet queue means, a distribution control means, and a collection control means. CONSTITUTION:Each of memory access means 111, 113 and 115 performs an access based on the memory access information included in a 1st packet X and outputs a modified 3rd packet Z. The 2nd packets Y including the transfer identification information are successively inputted to a packet queue means 102 and then outputted in the same order as the input order. A distribution control means 101 receives the packets X and Y and gives the packet X to one of those memory access means based on a prescribed distribution rule and gives the packet Y to the means 102. A collection control means 103 receives successively the packets Y from the means 102 and collects the packets Z from the memory access means that are designated by the transfer identification information included in the packets Y. Then the means 103 outputs these collected packets Z. Thus the packets are outputted with their input order kept as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a memory access device, and in particular to a memory access device in a data flow type system in which data flows in synchronization with pulses and processing is performed as the data moves. Relating to access devices.

[Prior Art] FIG. 3 is a block diagram showing the configuration of a conventional memory access device in a data flow type system.

In FIG. 3, packets are input to the memory access circuit 201 via a packet input line 211. The memory access circuit 201 starts memory access to the memory main body 202 based on the input packet, determines the memory data within the packet transfer time, and outputs the packet from the packet output line 212. This method requires high-speed static random access memory (SRAM) because it is necessary to determine memory data within the transfer time.

Furthermore, when using a low-speed memory in the conventional method described above, it is necessary to intentionally delay the output of packets and output the packets after memory access is completed.

FIG. 4 is a diagram for explaining input and output of packets when a low-speed memory is used in a conventional memory access device in a data flow type system.

In FIG. 4, A, B, C, and D indicate packets, and a
is an input packet, and b is an output packet.

Using slower memory in the traditional method above results in
Packet A at the time interval Tl shown in FIG.

Even if B, C, and D are input in order, the memory access time is longer than the packet interval, so packet A is output.
, B, C, and D, the time interval T2 becomes wider. When the time interval T2 between output packets increases in this way, the processing speed of the system decreases.

In order to improve this point, a method has been proposed in which memory accesses are performed in parallel by interleaving.

FIG. 5 is a block diagram showing the configuration of a conventional memory access device that performs memory access using an interleave method in a data flow type system. This memory access device is disclosed in Japanese Patent Laid-Open No. 62-34253 and Japanese Patent Laid-Open No. 62-34254.

According to this memory access device, data can be distributed and written to each memory one after another without synchronizing the memories.

The memory access device shown in FIG. 5 uses packet data consisting of two words. The first word packet includes address information and read/write designation information, and the second word packet includes write data. A plurality of such two-word packet data are asynchronously transferred onto the transmission path and given to the register 1. If the register l is writable, the register control unit 2 outputs the permission slang word AKo to the transmission line. This register control unit 2 is given pulse slang C6 from a transmission line. The register control unit 2 writes packet data to the register 1 when the pulse slang C6 is given. The packet data written to register 1 is
The signal is given to the branch control unit 3.

This branch control unit 3 branches packet data sequentially written to the register 1 asynchronously. The branch control unit 3 stores the packet data sequentially written in the register 1.
Memory bank 100 according to the address information in the packet
, 200. Sort into 300 or 400.

Registers 41, 42, 43.44 and register control units 51.52, 53.54 are provided on the input side corresponding to each memory bank 100, 200, 300, 400. The register control units 51, 52, 53, and 54 control the corresponding memory banks 100, 200, 300, and 400, respectively.
When data can be written to or read from, the permission slang is sent to the transmission line via the branch control section 3 and the register control section 2. Then, the register control units 51, 52, 53, and 54 transfer each packet data branched by the branch control unit 3 to the register 41 when data can be written to or read from the corresponding memory bank. Write in ゜42, 43, and 44 respectively. The packet data written to each register 41.42, 43.44 is stored in memory banks 100, 200, 30.
Given at 0°400.

Each memory bank 100, 200, 300, 400 writes or reads data based on the address information and read/write designation information included in the packet data written in the registers 41, 42, 43, 44, respectively. Registers 61 . 62.
63. 64, and register control units 71, 72, 7
3.74 is provided. Register control unit 71. 72.
73 and 74 write new packet data read from memory banks 100, 200, 300 and 400, respectively, into registers 61, 62 and 63, 64.

The new packet data written in each register 61, 62, 63, 64 is given to the merging control section 9. The merging control unit 9 merges new packet data in a predetermined order. The combined packet data is given to register 10. Register control unit 1 in relation to register 10
1 is provided. When the register control unit 1 is given permission slang UK2 indicating that packet data can be transmitted to the transmission path on the output side, it writes the packet data output from the merging control unit 9 to the register IO, and transmits the packet data on the output side. transmission path.

When the memory access device described above performs memory access, it is possible to output packets at the same time interval Tl while maintaining the time interval T1 of input packets, as shown in FIG.

[Problems to be Solved by the Invention] However, in the above conventional memory access device,
Because the processing time differs for each packet during parallel processing,
As shown in FIG. 6, there is a possibility that the packets are not output in the same order as the input packets.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory access device that employs an interleaving method for memory access at high throughput and is capable of outputting packets while maintaining the order of input packets.

[Means for Solving the Problems] A memory access device according to the present invention is a memory access device that performs memory access based on a first packet containing memory access information and a second packet containing transfer identification information, the memory access device comprising: It includes a plurality of memory access means, packet queue means, distribution control means, and collection control means. Each of the plurality of memory access means performs memory access based on memory access information included in the input first packet, and outputs a third packet processed by the memory access. Second packets containing transfer identification information are sequentially input to the packet queue means, and the second packets are output in the same order as the input order. The distribution control means receives the t-th packet and the second packet, provides the first packet to one of the plurality of memory access means according to a predetermined distribution rule, and provides the second packet to the packet queue means. . The collection control means sequentially receives the second packets output from the packet queue means, collects and outputs a third packet from the memory access means specified by the transfer identification information included in the second packet.

[Function] The memory access device according to the present invention employs an interleave method that performs memory access at high throughput, and outputs packets processed by memory access while maintaining the manual order of input packets. I can do it.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

The upper figure is a block diagram showing the configuration of a memory access device according to an embodiment of the present invention.

In FIG. 1, a packet input line 211 is connected to the distribution control circuit 101. The distribution control circuit 101 receives a t-th packet containing memory access information (hereinafter referred to as packet X) and a second packet containing transfer identification information (hereinafter referred to as packet Y) via a packet input line 211. is input. Packet Y output from distribution control circuit 101 is supplied to packet queue circuit 102 via packet transfer line 121. The packet X output from the distribution control circuit 101 is transferred to the packet transfer line 122,1.
Memory access circuit 1 via either 23 or 124
11, 113, or 115.

A device Y consisting of a packet queue circuit 102 is supplied to a collection control circuit 103 via a packet transfer line ↓3. Memory access circuit 111.113.11
5 performs memory access to the memory bodies 112, 114, and 116, respectively, based on the input packet X. Memory access circuit 111, 113.115
The packet containing memory access information output from
The data are supplied to the collection control circuit 103 via packet transfer lines 132, 133, and 134, respectively. Collection control circuit 10
3 supplies transfer permission information to one of the memory access circuits 111, 113, and 115 via one of the transfer control lines 141, 142, and 143. The collection control circuit 103 also includes memory access circuits 111, 113, and 115.
packets supplied from either packet output line 2
Output via process 2.

Next, the operation of this embodiment will be explained.

When a memory access packet consisting of a packet X and a packet Y is input to the distribution control circuit 101 via the packet input line 211, the packet
2, 123, and 124 to any of the memory access circuits 111, 113, and 115.

1st TI! In J, packet X is sent to memory access circuit 1.
11 is shown. A certain arbitrary distribution rule includes, for example, a rule for distributing data to a plurality of memory access circuits based on the value of the lower n bits of an address, the value of the upper n bits of an address, the value of an operation code, etc.

Meanwhile, at the same time as the above operation, packet Y including transfer identification information is supplied to the packet queue circuit 102 via the packet transfer line 121. In this case, the transfer identification information specifies the memory access circuit 111.

Packets Y are stored in the packet queue circuit 102 in the same input order and are supplied to the collection control circuit 103 via the packet transfer line 131 in the same order as the input order.

Based on the transfer identification information included in packet Y, collection control circuit 103 can recognize from which memory access circuit the packet should be collected next. In the example of FIG. 1, the collection control circuit 103 can recognize from the memory access circuit 111 that the packet should be collected next. Therefore, collection control circuit 103 provides transfer permission slang to memory access circuit 111 via transfer control line 141.

The memory access circuit 111 to which the packet X is input,
Based on the memory access information included in packet X,
After accessing the memory main body 112 through input or output operations, a packet processed by the memory access (hereinafter referred to as packet 2) is placed on standby. However, if you don't need memory access,
The memory access circuit does not perform any access. When the memory access circuit 111 receives the transfer permission slang via the transfer control line 141, it outputs packet 2 to the transfer control circuit 103 via the packet transfer line 132.

Collection control circuit 103 processes packet 2 received via packet control circuit 132 and then outputs the packet via packet output line 212.

FIG. 2 is a diagram for explaining the time intervals between packets input and packets output in the memory access device of FIG. 1.

In FIG. 2, A, B, C, and D indicate packets, a indicates an input packet, and b indicates an output packet. According to the memory access device shown in FIG.
As shown in the figure, even if packets are input one after another at time intervals T1, these packets A, B, C, and D are each processed in parallel in an interleave manner within the memory access circuit.

Therefore, as shown in FIG. 2, packet A.

B, C, and D can be output at time intervals T1. Moreover, since the packet queue circuit 102 stores the input order of packets, the packets can be output from the collection control circuit 103 in the same order as the input order.

[Effects of the Invention] As described above, 1. According to the present invention, memory access is performed at high throughput using the interleave method,
In addition, packets can be output while maintaining the order of input packets.

[Brief explanation of drawings]

FIG. 3 is a block diagram showing the configuration of a memory access device according to an embodiment of the present invention. FIG. 2 is a diagram for explaining the operation of the memory access device of FIG. 1.
The figure is a block diagram showing the configuration of a conventional memory access device. FIG. 4 is a diagram for explaining the operation of the memory access device of FIG. 3. FIG. 5 is a block diagram showing the configuration of a conventional memory access device using an interleave method. FIG. 6 is a diagram for explaining the operation of the memory access device of FIG. 5. In the figure, 101 is a distribution control circuit, 102 is a packet queue circuit, 103 is a collection control circuit, 1↓1, 113,
115. is a memory access circuit, 112.114,11
6 is the memory main body, 12t. 122.123,124,131,132,133.1
34 is a packet transfer line, 14L, 142 and 143 are transfer control lines, 211 is a packet input line, and 212 is a packet output line. Note that the same words in each figure indicate the same or equivalent parts.

Claims (1)

[Scope of Claim] A memory access device that performs memory access based on a first packet containing memory access information and a second packet containing transfer identification information, the memory included in the input first packet. A plurality of memory access means performs memory access based on access information and outputs third packets processed by the memory access; second packets are input in sequence; packet queue means for outputting; receiving the first packet and the second packet; providing the first packet to any of the plurality of memory access means according to a predetermined distribution rule; distribution control means for providing to the packet queue means;
and collection control means for sequentially receiving the second packets output from the packet queue means and collecting and outputting the third packets from the memory access means specified by the transfer identification information included in the second packets. Memory access device with