SU1686450A1 - Input-output operations checker - Google Patents

Abstract

The invention relates to computing and can be used in multi-machine computing systems, to which the predictions are increased requirements to the reliability of the obtained results of calculations. The aim of the invention is to increase the reliability of control by providing masking of failures in the ignored segments of data and command words. For this purpose, a group of N comparison blocks and a masking module are entered into a device containing two address registers, two data registers, a comparison block, an AND element, two OR elements, a failure detection block, a failure trigger, a failure trigger, and a no failure trigger. 2 hp f-ly, 3 ill.

Description

The invention relates to computing and can be used in multi-machine computing systems to which increased requirements are placed on the reliability of the obtained calculation results.

The aim of the invention is to increase the reliability of control by providing masking of failures in the ignored segments of data and command words.

FIG. 1 shows a functional diagram of an apparatus for controlling input-output operations; in fig. 2 - functional block failure detection circuit; Fig 3 is a functional diagram of the account node of this block.

The device (Fig. 1) contains the registers 1 and 2 of the address, the registers 3 and 4 of the data, block 5 of comparison, group 6 of block of comparison, module (A) of masking, consisting of block 7 of memory of masks, group 8 of elements OR and group 9 prohibition elements, element 10,

elements OR 11 and 12, failure detection unit 13, failure malfunction trigger 14, failure fault trigger 15, fault fault trigger 1b and has confirmation input 17, first 18 and second 19 information inputs, synchronization inputs group 20, masking input 21, write input 22 - masks readings, condition code input 23, write input 24, clock input 25, setup input 26, resolution output 27, fault presence 28, failure output 29, block installation input 30, count input 31 of block 13, information input 32 block 13, the input 33 of the recording block 13, the clock input 34 of the block 13, the output 35 of the block 13.

Moreover, the comparison output of the comparison block 5 is connected to the first input of the element 10, the output of which is connected to the single input of the trigger 14, the output of the latter is the output 27 of the device resolution. The non-comparison output of the comparison unit 5 is connected to the first input of the element OR 11, the output of which is connected to the zero input.

about

00

about

Ј

ate about

trigger 14, a single input trigger 15, and a gate input 31 of block 13. whose output 35 is connected to a single input of trigger 16, the output of which is the device fault output 29. Information input 32 of block 13 is input 23 of the condition code of the device. Record input 33 of block 13 is device record 24. The clock input 34 of unit 13 is a clock input 25 of the device. The input 26 of the initial installation of the device is connected to the zero input of the trigger 16, the second input of the element OR 12 and the input 30 of the initial installation of the block 13.

The first input of the element OR 12 is the input 17 of the device confirmation. The output of the element OR 12 is connected to the zero input of the trigger 15. The output of which is the output 28 of the presence of device faults. Information inputs of registers 1 and 3 are connected to information input 18 of the device. Information inputs 2 and 4 are connected to information input 19 of the device. The output of register 1 is connected to the first information input of the comparison unit 5, the second information input of which is connected to the output of the register 2 and the address input of memory block 7 of module A. The information input and write-read input of memory block 7 of module A are respectively the masking input 21 and an input 22 to write and read the device masks. The output N-ro bit of memory block 7 is connected to the inverse input N-ro of the prohibition element of group 9 and the first input of the N-ro element OR group 8 of module A. The second input of N-ro element OR group 8 of module A is connected to the output of comparison N The -ro comparison unit of group 6 of the device. The non-comparison output N-ro of the comparison unit of group 6 of the device is connected to the direct input of the N-th prohibition element of group 9 of module A.

The outputs from the first to the Nth elements of OR group 8 of module A are connected to the inputs of the second to (N + 1) -u elements of the device AND 10, respectively. The outputs from the first to the Nth elements of the prohibition of group 9 of module A are connected to the inputs of the second to (N + 1) -n elements of the device OR 11, respectively. The first information input of the N-ro comparison unit of group 6 is connected to the output of the N-ro data word segment of data register 3. The second information input of the N-ro comparison unit of group 6 is connected to the output of the N-ro word segment of the data register 4. The resolutions of the comparison block 5 and the comparison blocks of group 6 are interconnected and together with the write inputs of registers 1-4 form a group of 20 synchronization inputs of the device.

Failure detection unit 13 (FIG. 2) contains an account node 36, an OR element 37, an account node 38, a count input 39 and has installation 40 and information 41 inputs, an input

42 records, the output 43 of the node 36 of the account, the counting 44 and the installation of 45 inputs, information input 46, the input 47 of the record and the output 48 of the node 38 of the account. Moreover, the counting input 39 of node 36 is a clock input 34 of block 13, the installation input 40 of node 36 is connected to the first input of the OR element 37 and is input 30 of the installation of block 13. Information inputs 41 and 46, respectively, nodes 36 and 38 are interconnected and are

5, the information input 32 of block 13. The inputs 42 and 47 of the recording, respectively, of nodes 36 and 38 are interconnected and are the input 33 of record of block 13. The counting input 44 of the node 38 is the counting input 31 of the block

0 13, the output 48 of the node 38 is the output 35 of the unit 13, the output 43 of the node 36 is connected to the second input of the OR element 37. The output of which is connected to the installation input 45 of the node 38.

5Count 36 (38) contains element 49

delays, the element OR 50, the registers 51 and 52, the counter 53, the element NOT 54, the element 55 of the comparison, the element OR 56 Moreover, the counting input of the counter 53 is connected to the input

0 of the element is NO 54, the entry of the first register 51 and is the counting input 39 (44) of node 36 (38). The first input of the element OR 50, the information input and the input of the register entry 52 are respectively the installation input 40 (45), the information input 41 (46) and the input 42 (47) of the recording of the account 36 (38). The output of the delay element 49 is connected to the second input of the OR element 50, the output of which is connected to the installation input of the counter 53, the output of which is connected to the first information input of the comparison element 55. The second information input element 55 is connected to the output of the register 51, the information

5 whose input is connected to the output of register 52. The output of the NOT element 54 is connected to the enabling input of the comparison element 55, the first and second outputs of which are connected respectively to the first and second inputs of the OR element 56, the output of which is connected to the input of the delay element 49 and is the output 43 (48) node 36 (38) comparison.

The device works as follows.

Previously, the input 25 of the device and, accordingly, the input 34 of the block 13 are supplied with a sequence of clock pulses, the number of which in the block 13 determines the length of the time interval

Then, at the device input 26, the initial installation signal performs the initial installation of the trigger 16. Block 13 (at input 30) and the trigger 15 (via the OR element 12). Thereafter, through the input 23 of the device at the input 32 of the block 13, the failure condition code (which generally includes the number of failures code and the time interval code in which the number of failures is counted) is cleared. By a positive difference of the voltage at the input 24 of the device and, accordingly, at the input 33 of the block 13, this code is loaded into the block 13. In addition, the block 7 of the module A loads mask codes, in bits of which 1 corresponds to the masking the corresponding segment of the data word is closed, and O is the absence of masking.

Download codes masks as follows.

Register 2 loads the corresponding address by supplying the address code to the device input 19 and then the write signal to the device input 20.4. A mask code is input to the device input 21, then a high level recording signal is fed to the device input 22, which loads the mask code into the cell of the module 7 memory module A (with the address stored in register 2). The first information input 18 of the device is supplied with the address codes and data of the first computer, and the second information input 19 contains the codes of the address and data from the address and data of the second computer line. Register 1 and register 3 of data and respectively register of address 2 and register 4 of data are loaded with addresses and data of identical exchange cycles through the trunk of the first and second computers respectively. Moreover, the address and data of the first computer are written into registers 1 and 3 respectively on inputs 20.2 and 20.3, and recording the address and data of the second computer in registers 2 and 4, respectively, on inputs 20.4 and 20.5. After that, the input 20.1 is given a signal, which permits the operation of the comparison block 5 and the comparison blocks of group 6 to enable the latter.

The address from the output of register 2 is fed to the address input of memory block 7 of module A, the low level signal presenting the write-read input, which determines the reading mode of memory block 7 of module A, and triggers the appearance at the output of the last corresponding mask code. The unit signals of the mask bits from the output of block 7 of memory module A pass through the corresponding elements OR group 8 module A to the inputs of the device element AND 10, opening the latter through the corresponding inputs. At the same time, single bit signals

masks close the corresponding prohibition elements of group 9 of module A by inverse inputs, preventing signals from corresponding data segments of the same name from the comparison outputs of the same name comparison blocks of group 6 (through the OR element 11) to the corresponding inputs of the trigger 14 and 15 and the block 13.

Comparison unit 5 compares the addresses generated by the first and second computers recorded in registers 1 and 2, respectively. Comparison units of group 6 compare the same-name (with comparison units of group 6) segments of identical data words generated by the first and second computers recorded in registers 3 and 4, respectively.

In the case of coincidence of addresses and data words of identical exchange cycles generated by the first and second computers, signals that passed through the same-named elements of OR of group 8 of module A and the element of AND 10 appear at the outputs of the comparison of the comparison block 5 and the comparison blocks of group 6, set the trigger 14 for the failure of the one state if the trigger 14 was in the zero state, and confirm the one state if the trigger 14 was in the single state. After that, at output 27 of the device, a signal appears enabling the operation of both computers.

In the case of a mismatch of addresses or at least one pair of unmasked segments, or both, generated by the first and second computers in identical exchange cycles, the output of element And 10 is set to a low level signal.

A high level signal from one of the outputs of non-comparison of either comparison block 5, or comparison blocks of group b, with the same name as unmasked data word segments stored in registers 3 and 4, passing through the device element OR 11 (and in the case of comparison blocks of group 6, pre-pass through the same open prohibition elements of group 9, module A) resets trigger 14 for no failures to the zero state. This leads to the disappearance of the signal at the output 27 of the device and the termination of the system according to a given program of two controlled computers. Failure trigger 15 is set to one, and a signal appears at device output 28, signifying the presence of a fault in the system of two computers. This signal from the output of the element OR 11 is used to transfer the failure detection unit 13 on input 31 to the next state, which fixes the total number of failures in the system. Signal

From device output 28, each of the two computers is transferred to a crash interrupt handler program, which returns the computer to the place in the work program after which the crash occurred. Going to the interrupt handler, the computer system generates a confirmation signal, which is fed to input 17 and, after passing through the OR element 12, resets to the zero state of the failure trigger 15.

Having returned to the place in the work program that preceded the failure, each of the two computers continues its work from cycle to cycle in the mainframe address-data of the computer. The operation of the device is repeated as indicated. In the case when the total number of failures detected by the failure detection unit 13 exceeds the condition specified in the code and stored in block 13, a signal appears at the output 35 of the latter, which sets the failure trigger 16 to one. At device output 29, a signal appears, alerting the system of the failure of a controlled pair of computers. This signal can alert either the operator or act on the system as a high priority interrupt signal, at which the system should reach the appropriate fault interrupt handling program.

Selection of masked segments can be carried out according to the following principle. In a traditional architecture computer, there is no separation in the addressing of commands and data, i.e. In a cell with an address that is set by the processor, both the command and the data can be stored. Therefore, in such computers, both commands and data read from the memory are transmitted via the data bus. The identification of commands and data is determined by the fact that in the first cycle of accessing the memory, the computer processor always reads the command. In subsequent cycles, data alternates with commands. The order is determined by the program.

It is natural to assume that the violation of the command code changes the computer operation algorithm. At the same time, the violation of the data code can significantly change the algorithm of the computer operation only after performing certain operations (for example, comparison operations). Based on this, it is possible to mask some segments of commands. These segments can include command segments containing data or parts of data segments, for example, lower data bits. More specifically, masked segments are defined by the instruction formats of computer processors.

The device allows you to speed up the processing of information in the presence of failures in the system, at the same time preserving the accuracy of the algorithm. Individual data failures in the case of the control algorithm can be smoothed by inertial actuators.

Claims (3)

1. A device for controlling I / O operations containing two address registers, two data registers, a comparison unit, an AND element, two OR elements, a fault detection block, a failure trigger, a failure trigger, and no failure trigger, and the information inputs of the first address register and the first data register form a group of device inputs to connect 0 to the address and information outputs of the first computer, the information inputs of the second address register and the second data register constitute a group of device inputs for connecting to the address and information outputs of the second computer, the outputs of the first and second address registers are connected to the first and second information inputs of the comparison unit, respectively Comparison output is connected to 0 to the first input of the element AND, the output of the element AND is connected to the single input of the no-fault trigger, the zero input of which is connected to the output of the first element OR, the single input of the failure trigger and the counting input of the failure detection unit, the output of the failure detection unit is connected to the single input of the failure trigger, the output of which is the output of the device for connecting the first and second computers to the fault input, the first input of the second OR element is the device input for connecting to the confirmation outputs of the first and second computers, and the second input is connected to the installation input of the detection unit 5 failure, the zero input of the failure trigger and is the input of the device for connecting to the outputs of the initial installation of the first and second computers, the output of the second OR element is connected to the zero input of the failure trigger, 0, the information input and the write input of the failure detection unit are the device inputs for connecting respectively to the outputs of the condition code and the outputs of writing the condition code of the first and second computers, outputs 5 triggers no faults and triggers faults are the outputs of the device for connecting respectively to the enable inputs and the presence of faults of the first and second computers; the enabling input of the comparator is the input of the device for connecting to the first sync outputs of the first and second computers; the non-matching output of the comparator is connected to the first the input of the first element OR, the recording entries of the first register of the address and the first data register are the inputs of the device for connection respectively to the second and third sync outputs of the first computer, The records of the second address register and the second data register are inputs of the device for connecting the second and second sync outputs of the second computer, respectively, in order to increase the reliability of control by providing masking of failures in the ignored segments of data words and commands, it contains a group of N comparison blocks and a masking module whose address input is connected to the output of the second address register, and the information input and write-read input of the masking module are device inputs to connect respectively to the output of the masks and the write-read output of the masks of the first and second computers; the first information input of the N-ro group comparison unit is connected to the output of the N-th data segment of the first data register; the second information input of the N-ro group comparison unit is connected to the output of the N-ro segment of the data word of the second data register, the comparison outputs and incomparison of the N-ro comparison block of the group are connected to the same inputs of the masking module, the outputs of the first through Nth first and second groups of which are connected to the inputs from the second for (N + 1) -u respectively first OR and AND gates to allow all inputs of the comparator group are connected to the enabling input of comparator unit, and a clock input failure detecting unit is the input of the device for connection to the clock outputs of the first and second computers. 2. Device pop. 1, distinguishing 5 through the fact that the masking module contains a mask storage unit, a group of N elements OR, a group of N prohibition elements, the informational, address input and the write-read input of the mask storage unit are of the same name as the module's inputs, the 1st bit of the output of the mask storage unit (1 i Ј N) is connected to the inverse input of the 1st element of the group prohibition and the first input of the 1st element of the OR group, the second input of the 1st element of the OR group is the lth input of the module comparison, the direct input of the 1st prohibition element the group is the 1st input of the module mismatch, the output of the 1st prohibition element of the group is the 1st output of the first 0 group of the module, the output of the i-element of the OR group is the ith output of the second group of the module. 3. Device pop. 1, characterized in that the failure detection unit co5 holds two counting nodes and an OR element, the counting input of the first counting node being the clock input of the block, and the output of the first counting node is connected to the first input of the OR element, the second input of which 0 is connected to the installation input of the first account node and is the installation input of the block; the output of the OR element is connected to the installation input of the second account node, whose information input together with 5, the information inputs of the first counting node form the same input of the block, the inputs of the recording of the counting nodes are interconnected and form the record entry of the block, the counting input of the second counting node is the counting input of the block, and the output of the second counting node is the output of the block. 39 (M) C ; 5J WM) 50 w L 52 T V 51 55 56 W48) eight Fig.Z