JPH03207080A - Multiport memory - Google Patents

Abstract

PURPOSE:To accelerate drawing and to shorten access time by making data for one line in a RAM corresponding to a two-dimensional rectangular area on a display screen and drawing longitudinal and lateral lines in this page by one time access. CONSTITUTION:When a row address is inputted and one row is selected by a row decoder 2, picture elements for one page are selected. When the data for one page are transferred to a serial port for CRT display, a column address to designate the first line of the page is inputted to a horizontal column decoder 3. The data of bit lines B1-B32 belonging to the first line of the page are transferred through column select transfer gates T1-T32 to data lines D0-D31 and inputted to a serial data register 4. Thus, a graphic over longitudinal lines or more than two scanning lines in the page is drawn at high speed and the access time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is used for raster scan graphics display, and includes a random port for changing display contents by access from a CPU, and outputting data for display to a display. The present invention relates to a multi-port memory having a serial port.

BACKGROUND OF THE INVENTION Multi-port memory based on DRAM appeared in the 64K bit era as a frame buffer for bitmap display systems.

This includes serial access memory (SA) in addition to random access memory (RAM) consisting of DRAM memory cells.
M), so that data for one word line of RAM can be transferred to SAM at once. Once S
The data transferred to AM is output as display data from a serial port independent of the random port, so even while display data is being output, the CPU accesses the RAM via the random port and redraws the display contents. be able to. When the frame buffer was configured with conventional general-purpose DRAM, access for drawing from the CPU {all was possible only during the display blanking period, but with the advent of this multi-port memory, Access for drawing can now be made at any time except during the data transfer period to the SAM, resulting in a significant improvement in drawing efficiency.

With the increase in the density of general-purpose DRAM, multi-port memory has also expanded from 64K bits to 256K bits, and even further to IM.
Items with high bits and high density began to appear. At the same time as this generation change due to increased integration, functions such as real-time data transfer function, pointer function, write mask function, arithmetic write function, block write function, and flash write function were added.

However, the basic structure of transferring data for one word line from RAM to SAM in a data transfer cycle remains unchanged.

An example of such a conventional multiport memory is shown in FIG. Figure 4 shows the main parts of a 256K-bit multiport memory with a 64K x 4-bit configuration, including memory cell array 1,
It includes a row decoder 2, a column decoder 3, a serial data register 4, and a random port input/output circuit 5. In an actual chip, it is often divided into several blocks due to layout considerations and consideration of wiring resistance, wiring capacitance, etc., but the basic structure is like this. Furthermore, although two bit lines and data lines are actually used as a pair, including a line for complementary data, it is not necessary to draw the two lines separately for the purpose of explaining the present invention. Therefore, it is represented by a single line for simplicity.

First, consider the case where a multi-port memory is accessed by multiple CPUs for drawing and data is written from a random port. Data input/output terminal I/Oo, I
/O+, I /O2. 1/Os, the random port input/output circuit 5 connects the data lines Do, D+, D2 . Drive D3. Bit line BI. B2.・・・・・・・・・Among BI024, those selected by the column decoder 3, for example, Bl, B2
．． Bi *B4 is column selection transfer gate T+, T2, T
3. Data lines Do, D+ . D2D3
are connected to each. As a result, memory cell array 1
Data is written into the memory cells of the row selected by the row decoder 2 on the bit lines B1, B2, and 83B4.

On the other hand, considering the case where data is output from the serial port for display, first, in a data transfer cycle, the data in the memory cells of the row selected by the row decoder 2 is transferred to the bit line B. B2.・・・・・・・・・BIO
Directly transfer data from I to serial data register 4. The data transferred to the serial data register 4 is sent to the serial output terminal S O o * in synchronization with the serial clock.
S O + + S O 2 Each 4 bits are serially output from SO3 and used for CRT display.

Four such 256K-bit multi-port memories can constitute one screen of a 1024.times.1024 pixel display screen as shown in FIG. For example, if the screen is divided into four vertically, lines 1 to 256 will be used as the first multi-port memory, lines 257 to 512 will be used as the second multi-port memory, lines 513 to 768 will be used as the second multi-port memory, etc. 3rd up to the eyes
The multi-port memory from the 769th line to the 1024th line may be allocated as the fourth multi-port memory. The 4 bits output simultaneously from the serial board are converted into 4 consecutive pixels in the horizontal direction on the display screen, for example, P (0.0), P (0.11), using a P/S conversion circuit.
! P (0.2>, P (0.3)). Considering the movement of the scanning line on the CRT, the data serially output from the serial port is output from the left on the horizontal line in the order in which it is output. They will be allocated to the right.The number of bits in the serial data register is 1024, which is the same as the number of all bit lines, so one data transfer will cover l rows in the horizontal direction on the display screen in Figure 5. data is transferred from RAM to SAM.

Problems to be Solved by the Invention As explained above, in conventional multi-port memory,
One row of data obtained by selecting the row address is R
Data was transferred from AM to SAM, and the data was serially output in accordance with the movement of the scanning lines on the CRT. For this reason, one row of data in RAM corresponds to one row of pixels on the display screen, or depending on the layout of the screen, it may be part of one row on the screen or a portion that spans up to two rows. It was supposed to correspond to

However, if you think about drawing vertical and horizontal lines, which is often the case when displaying figures with EWS etc.,
In the example shown in Fig. 5, the horizontal line can write data for 4 pixels to the RAM in one write cycle, and even if the line has more than 4 pixels and requires multiple write cycles, the data can be written in the horizontal direction. Since the pixels lined up correspond to the same row of the RAM, they can be written using a high-speed access mode such as page mode, and can be drawn at relatively high speed. However, the vertical line is made pixel by pixel, and the row address
Since it is necessary to write in the normal access mode in which the column address is input together, the time required for drawing increases. Therefore, the burden on the CPU side for drawing increases, causing a decrease in display speed.

In order to shorten drawing time, IM bit products have appeared that have added high-speed writing functions such as block write and flash write to conventional multi-port memories. However, these are all high-speed writing functions that follow the scanning line of the CRT, and although they are effective in speeding up freezing and crushing of surfaces, they are not suitable for drawing figures consisting of vertical, horizontal, and diagonal lines. On the other hand, it had almost no effect.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention makes one line of data in the RAM correspond to a two-dimensional rectangular area (hereinafter, this rectangular area is referred to as a page) on the display screen, Within this page, vertical and horizontal lines can be drawn in one access, and even shapes such as diagonal lines that cannot be drawn at once can be drawn using a high-speed access mode such as page mode as long as they are within this page. It is something that makes it possible.

To achieve this objective, the multi-port memory of the present invention provides a first port for transferring data in the RAM to the SAM according to the vertical position within the page on the display screen (hereinafter referred to as page row). It includes a column selection circuit and a second column selection circuit for writing data at once across all page rows at a certain position in the horizontal direction within a page (hereinafter referred to as a page column).

Effect: With this configuration, vertical lines and figures that span two or more scanning lines within a page can be written to RAM faster than conventional multi-port memories, and drawing This reduces the time required to access memory and improves drawing speed.

Embodiment An embodiment of the multiport memory of the present invention is shown in FIG. Bit line B+ in FIG. 1! B2 r・・・・・・B
1024 indicates bit lines Bl, B2," in FIG. 5 showing the display screen when row R+ is selected, for example.
"", B32 is pixel P (0.0), PC0, +1, "
""P(0.31>), bit lines B33, B34T
--, B64 is pixel P (+, O) + P (++l
l+ """' P (1.31),...Bit line Bss3, B994, ゜-=. BI02
4 is pixel P (31.0) + P (31, +1 +
""" + P (corresponds to 31, 311.

FIG. 3 is an enlarged view of such a page consisting of 32×32 pixels. Each time a row address is input and one row is selected by the row decoder 2, pixels for one page are selected on the display screen. Further detailed locations within this page are specified by column addresses.

For CRT display, for example, pixels P (0.0), P
C0. +1, “””. When transferring data of P(0.31>) to the serial port, the column address that specifies the first row of the page row is input to the horizontal column decoder 3, and the column address that specifies the first row of the page row is Bit line BIB2 belonging to the eye...
..., B32 data is sent to column selection transfer gate 'r. ,T
? , """. Data lines Do, D+, . . . pass through T32.
..., is transferred to D31 and input to the serial data register 4. In the example of FIG. 1, such a data transfer cycle is executed every time 32 pixels are displayed on the CRT.

Next, let us consider the case where data is written from the CPUs to the multiport memory for drawing. First, a page to be drawn is selected using a row address. When writing vertical line A in Figure 3 on this page, vertical line A
A column address specifying the second column of the page column is input to the vertical column decoders 6, 7, . . . , 37, and the bit line B2+B belonging to the second column of the page column in each page row is
34,...B994, column selection transfer gate 7
1026, T 1058, ”'...,720
1B through the data line D. ,D. ,...D31
data is transmitted, and the data is written on these bit lines to the memory cell selected by the row address representing the page. Data lines IjO, DI +...
..., on D31, random port input/output circuit 5
Accordingly, the data input/output terminals 1/Oo, I/O+,
...=, data input from I/031 is being transmitted.

When writing horizontal 1 & 1 IC in FIG. 3 within a page, a horizontal column decoder is used as in the transfer cycle. That is, the column address specifying the second page row is input to the horizontal column decoder 3, and the bit lines B33, B34, . . . , B belonging to the second page row are input to the horizontal column decoder 3.
64, column selection transfer gates T33, T34,...
, data line D. through T64. ．． D.・・・・・・
The data of D3+ is transmitted, and the data is written into the memory cells belonging to the selected row on these bit lines. As described above, both horizontal and vertical lines for 32 pixels within a page can be drawn in one write cycle.

In a case like the diagonal line B in Figure 5, it cannot be written in one time, but if you use a vertical column decoder to write two pixels at a time, it will be drawn in 16 times, which is half the time compared to the conventional multi-board mesori. is completed.

Moreover, since these writes can use a page mode cycle, which takes about half the time of a normal write cycle, drawing can be completed in about a quarter of the time compared to a conventional multiport memory.

In the embodiment shown in FIG. 1, a transfer cycle must be executed to transfer new data to the SAM every time 32 pixels are displayed on the CRT. Since access from random ports is not possible during the transfer cycle, in some cases, this large number of transfer cycles may cause a decrease in drawing efficiency. In order to improve this point, it is preferable to combine the parts other than the random port input/output shown in FIG. 1 into one block and connect this block as shown in FIG. 2.

In FIG. 2, 39, 40, 41, and 42 are such blocks, and in order to select which block is to be accessed from the random port, the block decoder 38 and the block selection transfer gate T 2049 are used.
NaT 2050! ``''''' lT 2+76 is provided.The serial port output of each block is multiplexed by multiplexer 43, and block 39
When the serial output from block 40 is completed, the next block is block 40, and when the serial output from block 40 is completed, the next block is block 4l, and so on, the four blocks 39 to 42 are sequentially switched to obtain serial output. Therefore, once a data transfer cycle is executed, 128
Data for pixels can be output serially. That is, it is sufficient to execute one data transfer cycle while displaying 128 pixels on the CRT.

Using the multi-port memory shown in Figure 2, by selecting one row address, four
An area corresponding to a page is selected. The four pages correspond to block 39, block 40, block 41, and block 42 in order from the left.

Since each block of the multi-port memory shown in FIG. 2 has 256K memory cells as shown in FIG. 1, four blocks constitute 1M, which can be made into one chip using current manufacturing technology. Using this, 1 as shown in Figure 5.
In the case of a 024x1024 display screen, data for one brane can be stored in one chip.

Effects of the Invention As explained above, according to the present invention, it is possible to realize a multi-port memory that can draw at high speed even lines perpendicular to the scanning line direction or figures spanning two or more scanning lines.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a multi-port memory J according to an embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing a multi-port memory J according to the present invention. Figure 4 is a block diagram showing the configuration of a conventional multi-port memory, and Figure 5 is a schematic diagram showing one page on the display screen when displayed using a multi-port memory. FIG. 3 is a schematic diagram showing a display screen. Bl, B2 +..., BI024...
...Bit line, D O +DI+...,
D31...Data line, TI, T2,...
..., T2048... Column selection transfer gate.

Claims (2)

[Claims] (1) A memory cell array arranged in a matrix, a row access means, the entire column is divided into a plurality of column groups each consisting of a plurality of columns, and a plurality of columns belonging to any one of the column groups are simultaneously operated. a first column access means for selecting and accessing a column; a second column access means for simultaneously selecting and accessing one column from each column group in the plurality of column groups; writing means for writing data input from a random port into a column selected by the column access means; a serial data register serially accessible from the serial port;
A multi-port memory comprising data transfer means for transferring data of a column selected by the column access means to the serial data register. (2) The memory cell array according to claim 1, comprising a plurality of blocks each comprising a row access means, first and second column access means, a serial data register, and a data transfer means, one block among the plurality of blocks. Select a block access means to access from a random port,
A multi-port memory comprising serial access means that allows all contents of the serial data registers of the plurality of blocks to be serially accessed from a serial port.