JP3061824B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a multiport memory for displaying raster scan graphics.

2. Description of the Related Art In recent years, multiport memories have been widely used for image processing in graphic terminals and the like.

Hereinafter, a conventional multiport memory will be described. FIG. 3 shows a block diagram of a conventional multiport memory. W _{L1 to} W _Ln are word lines of random access memory (RAM), B _{L1 to} B _L16 are bit lines of RAM, T ₁
Through T ₁₆ column address transfer gates, D _L1 to D _L4 are data lines.

The operation of the multiport memory will be described. Data input / output to / from the RAM is performed using data lines D _{L1 to} D _L4 . For example, consider a case in which data on the data lines D _{L1 to} D _L4 is written to a memory cell on the word line W _L1 . Word line W _L1 is selected, the data in the memory cells connected to the bit line and the word line W _L1 selected by the column address decoder is written. In the case of reading, data of a memory cell connected to the selected word line and the bit line selected by the column address decoder is read through each of the data lines D _{L1 to} D _L4 .

Next, when serial data is read from a serial access memory (SAM), data of a memory cell connected to a selected word line in the RAM is transmitted through a bit line to the SA.
Transferred to M and output as serial data. When performing screen display, data to be displayed on the screen was written to RAM, and the data was transferred to SAM, serially output, and displayed on the screen.

Problems to be Solved by the Invention In the conventional configuration, when data transferred to the SAM is continuously output in accordance with the movement of the scanning line according to the normal usage, the data of the SAM is transferred to the word line selected at the time of transfer. Since the data is equal to the data, basically the data on one word line is displayed on one scanning line or a part thereof. Therefore, when writing a graphic having a vertical spread and relating to a plurality of scanning lines to the RAM, a plurality of word lines having different row addresses must be accessed. Generally, when accessing memory cells having the same row address but different column addresses in a dynamic RAM, a high-speed access mode such as a page mode can be used. Only the access mode of can be used. That is, when writing a graphic having a spread in the vertical direction into the memory, the conventional multiport memory has a drawback that only a normal access mode with a low speed can be used, and the writing speed of the display graphic is low.

Also, even when using a conventional multi-port memory,
If data on one word line is made to correspond to a two-dimensional rectangular area having a vertical spread on the display screen,
It is possible to write figures with a vertical spread in page mode. However, in this case, of the data for one word line transferred to the SAM, the data that is actually continuously output along the scanning line and used for display on the screen is the scanning within the rectangular area. Only data located on the line will be available.

Even in the rectangular area, data located on another scanning line cannot be displayed unless it is transferred again in another transfer cycle. In other words, only a very small part of the data to be transferred is actually used for display, and most of the other data is wasted transfer. Because of the useless transfer, the power consumption and the layout area of the SAM on the chip are wasted.

In order to solve the above problem, the present invention selects and transfers only data of a necessary column address so that only data on one scanning line in the rectangular area can be transferred to the SAM,
An object of the present invention is to provide a multi-port memory capable of writing in a high-speed access mode such as a page mode even in a figure having a vertical spread without performing unnecessary data transfer.

Means for Solving the Problems In order to achieve this object, a multiport memory of the present invention is a raster scan graphics display multiport memory having a random access port and a serial access port, comprising a row address and a column. A RAM accessed by specifying an address, and a plurality of bit lines of the RAM connected to a plurality of bit lines of the RAM via a column address selection gate selectively conductive according to the column address, respectively, and a specified row address and column of the RAM A plurality of data lines used for input / output of data with respect to an address, a SAM coupled to the plurality of data lines, and serially outputting screen display data, and the word of the RAM selected by the row address; The data of a plurality of memory cells connected to a line is stored in a rectangular block Data of a plurality of scanning lines in the one rectangular block are respectively associated with different column addresses, and data for screen display is transferred from the RAM to the SAM.
When transferring the data corresponding to one scanning line by designating the column address from among the data of a plurality of memory cells connected to the word line of the RAM selected by the row address. Through the column address selection gate and the plurality of data lines.
Transfer to SAM.

Operation With this configuration, it is possible to shorten the time for writing data to be displayed on the screen to the RAM and to speed up the screen display, and at the same time, to useless data transfer when reading the data from the RAM to the screen. Disappears.

Embodiment An embodiment of the present invention will be described below with reference to a screen. In the following description, the number of data lines is four for simplicity.
Therefore, the case where the number of column addresses is 4 is taken up, but the present invention can of course be implemented even when the number of data lines and the number of column addresses are larger. Although two bit lines and data lines are used as a pair, these are also shown by one line for simplicity. FIG. 1 is a block diagram showing a multi-port memory according to the present invention. W _{L1 to} W _Ln
Is the word line of RAM, B _{L1 to} B _L16 are the bit lines of RAM, T ₁ to ₁₆
Is a column address transfer gate, and D _{L1 to} D _L4 are data lines.
Input / output of data to / from the RAM is performed using data lines D _{L1 to} D _L4 . For example, consider a case where data on each of the data lines D _{L1 to} D _L4 is written to the memory cell of the word line W _L1 . A bit line selected by the column address decoding coater word line W _L1 is selected, the data in the memory cells connected to the word line W _L1 is written. In the case of reading, data of a memory cell connected to the selected word line and the bit line selected by the column address decoder is read through each of the data lines D _{L1 to} D _L4 . Then SAM
When reading serial data from the RAM, the data of the memory cell connected to the selected word line in the RAM is read onto the bit line, and the data of the column address selected by the column address decoder is read from the column address transfer gate T. _{1 to} T ₁₆
The data is transferred to the SAM through the column address transfer gate that has been turned on and any one of the data lines D _{L1 to} D _L4 and serially output. For example, when the word line W _L1 becomes to column address transfer gate T ₉ through T ₁₂ is "on" selected, the data of each memory cell connected to the word line W _L1 and the bit line B _L9 .about.B _L12 is, Transferred to SAM and output as serial data.

As described above, the multiport memory of the present invention can transfer only data for one column address to the SAM, and the size of the SAM can be designed according to the data size for one column address. Since it is possible, the layout area can be reduced.

Next, an operation when the multiport memory of the present invention is used for image processing of a graphic terminal will be described. FIG. 2 shows a screen of a graphic terminal.
(1) to (n) are blocks obtained by dividing the screen into rectangles, A
ＤD are scanning lines existing in each block. In FIG. 2, four scanning lines A to D are used in a block. However, the number of scanning lines in one block depends on the storage capacity of the multiport memory used for the graphics terminal and other factors. The present invention can be similarly implemented even when the number of scanning lines in a block is other than four, because it is determined by factors. As shown in FIG. 2, (1)-
(N) Divided into rectangular blocks, and the data amount of each block is equivalent to the data amount that can be written to the memory cell connected to one word line of the RAM of the multiport memory of the present invention. I do.

When data to be displayed on the screen is written to the RAM of the multiport memory of the present invention, writing can be performed in a page mode within a range of each block of a scene. next,
To output the data written in RAM to the screen,
2 is selected, and four data of the memory cells connected to the bit line selected by the column address decoder among the memory cells connected to the word line are transferred to the SAM and serially output. (1) is displayed on the scanning line of the block A. And the next data displayed is RA
Select another word line of M, and similarly, among the memory cells connected to the selected word line, data 4 of the memory cell connected to the bit line selected by the column address decoder.
Are transferred to the SAM, serially output, and displayed on the scanning line A of the block (2) in FIG. In other words, the data to be displayed is displayed along the scanning lines and while repeating the data transfer from the RAM to the SAM each time the block changes.

According to the multiport memory of the present invention, when writing data to be displayed on the screen to the RAM, the data of each block of the screen can be written to the RAM in the page mode, so that the writing time is greatly reduced. Can be shortened to

[Brief description of the drawings]

FIG. 1 is a block diagram of a multiport memory according to an embodiment of the present invention, FIG. 2 is a conceptual diagram showing a screen of a graphic terminal, and FIG. 3 is a block diagram of a conventional multiport memory. W _{L1 to} W _Ln … RAM word line, B _{L1 to} B _L16 … RAM bit line, T _{1 to} T ₁₆ … column address transfer gates, D _{L1 to} D _L4 …
... data lines.

Continuation of the front page (56) References JP-A-62-287497 (JP, A) JP-A-63-142593 (JP, A)

Claims (1)

(57) [Claims] 1. A multi-port memory for raster scan graphics display having a random access port and a serial access port, wherein the random access memory (RAM) is accessed by designating a row address and a column address. A plurality of data which are respectively connected to a plurality of bit lines of the RAM via a column address selection gate which selectively conducts according to a column address, and are used for inputting / outputting data for a specified row address and column address of the RAM. And a serial access memory (SAM) coupled to the plurality of data lines and serially outputting screen display data, and connected to a word line of the RAM selected by the row address. The memory cell data is associated with one rectangular block that boasts multiple scanning lines on the display screen. The data of the plurality of scanning lines in the one rectangular block are respectively associated with different column addresses, and when transferring screen display data from the RAM to the SAM, the data of the RAM selected by the row address is used. By specifying the column address from data of a plurality of memory cells connected to a word line, data corresponding to one scanning line is selected, and the data is selected via the column address selection gate and the plurality of data lines. A multi-port memory for transferring to the SAM.