JPS6148189A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To accomplish a high transfer rate by composing corresponding respective column outputs of a random access memory corresponding to respective steps of a shift register, and composing an input output device of plural bits to access in parallel plural columns corresponding to plural steps adjacent to the shift register. CONSTITUTION:A RAM composed of a 16K word X 4 bits is assembled with a serial shift register of 256 bits as a reading means. Data of a CPU data bus access simultaneously through an I/O1-I/O4 and the contents of RAM are transferred between shift registers and the shift register serially outputs data from a terminal SOUT with high speed by a shift clock SCLK. By such a composition, non-synchronously with a high speed reading by the shift register, a RAM side can access at randomly as an independent memory. Consequently, like a picture memory between CPU and a video display, the memory is used when a high speed serial data output and independent picture data processing from the output are necessary.

Description

[Detailed Description of the Invention] [Field of Industrial Application] Does the present invention apply to semiconductor memory devices? ! ! i! In particular, the present invention relates to a semiconductor memory device that combines a random access memory (RAM) with a multi-pin input/output configuration and a shift register for high-speed reading.

[Conventional technology]

Conventionally, a semiconductor memory device jl (memory) that combines a dynamic RAM with a 1-bit input/output configuration (for example, 464), a RAM with a word×1 bit configuration, and a serial shift register has already been announced. In addition, a multi-bit input/output configuration, for example, a 4-bit RAM and an externally connected shift register, which have a similar function, have also been announced. This kind of memory is capable of high-speed reading on the shift register side asynchronously with the random access on the general KRAM side, and the cycle time between the RAM side and the shift register side is usually 1:5 to 1:10. It is. That is, CI'
With respect to the data input/output between the U data bus and the AM, the data rate transferred from the AM to the shift register and read out from the shift register is extremely fast, and therefore the speed of data between the CPU and the video display device is extremely high. It is used for high-speed processing of image data.

[Problem that the invention seeks to solve]

In general, when the bit configuration on the RAM side is 1 pit configuration, data transfer between the CPU data bus and RAM, especially writing, is significantly slower than reading from the shift register, as mentioned above, so interleaving is performed to increase the efficiency of this transfer. Some methods have been used to solve this problem, but there is a problem in that K uses a large number of devices.

Therefore, it is conceivable to incorporate a shift register for high-speed serial reading in a RAM having a multi-bit input/output configuration to increase the data transfer speed by random access and to match the serial reading speed. In general, an AM with a multi-bit input/output configuration has an internal configuration divided into multiple blocks.For example, an AM with a 16 word x 4 pit configuration has a memory cell array block of 256 rows x 64 columns. It is common to adopt a configuration in which four are arranged side by side. In that case, the 4-pit data for each word is stored separately in each block, so a shift register is attached to each block that connects each column output to each stage.
If these shift registers are connected in series and the serial output is taken out, data written or read simultaneously in parallel by random access will not appear consecutively all at once in the serial output, which will be extremely inconvenient in data processing. There's a problem. In order to avoid this, it is possible to provide a separate data bus for each shift register attached to each block and convert the output from each shift register to serial output via a multiplexer. This creates a problem in that the configuration becomes complicated, requiring the addition of a multiplexer.

[Failure to solve the problem]

It is an object of the present invention to provide a semiconductor memory device that solves the above problems, and the means thereof is to make each column output of a random access memory correspond to each stage of a shift register, and to perform a transfer operation of the shift register. The configuration is such that the valley column output data can be output as serial data in accordance with the output data, and the input/output device for multiple bit input/output is a 44V configuration that accesses multiple columns corresponding to adjacent multiple stages of the shift register in parallel. The present invention is characterized in that a plurality of bits of data that are written or read simultaneously by parallel access by an input/output device are continuously output in serial data output.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of a semiconductor memory device as an embodiment of the present invention. In this example, the word
A 4-pit RAM is combined with a 256-pit serial shift register as a reading means. The data on the CPU data bus is sent to the RA at the same time via steps 101 to 104.
M is accessed and the contents of the RAM are transferred to and from the shift register, and the shift register receives the shift clock 5OII.
Serial output of data at high speed by terminal Sot+
Start from 7. In this type of I1 configuration, the RAM side can be randomly accessed as an independent memory asynchronously with the high-speed first-out using the shift register, and therefore the image between the CPU and the video f
'3! It is used when high-speed serial data output and independent image data processing are required, such as in memory.

FIG. 2 is a block diagram showing the semiconductor memory device shown in FIG. 1 in detail. In FIG. 2, 1 is a column decoder, 2 is a row decoder, I/(h-104 is an input/output device %SA1-8 A256 is a sense amplifier, SR1-
5R251S is a shift register as a reading means, M is a plurality of memory cells, T2 is a transfer gate provided between each sense amplifier and a data bus, and between each bit line and each stage of the shift register, and TCLK.
is a transfer lock for turning on and off transfer gate T2.

The shift register operates on clocks 8or,x, and produces a serial output from the serial output terminal f3oty7. In such a side configuration, each sense amplifier is connected to an independent data bus 1111ilDB1 to 1111ilDB1 by a transfer gate T1 controlled by a column decoder output.
They are connected to DB4 in the order of data bus lines as shown. That is, for 256 columns, one Ilo
64 sense amplifiers are connected to the data bus line connected to the middle 6
One sense amplifier is connected to each other via a transfer gate T1. Such a connection method is also applied to other data buses.

On the other hand, column decoder 1 carries any four sense amplifiers and selects four transfer gates T1 at a time. This is done by deciding whether to select one of the four sense amplifiers or one of the 64 sense amplifiers. Therefore, column decoder 1 has address CA.

The row decoder 2 selects one of 64 groups of four sense amplifiers each using six lines from addresses RAo to RA7. Choose one. As described above, in the present invention, the four sense amplifiers are connected in accordance with the order of the four data bus lines.
Data input by bit random access simultaneously is serially output from the shift register SR as adjacent data.

In this case, each stage SR+ to 5R2s6 of the shift register is provided so that the output of each column is inputted via the transfer gate T2 as shown in the figure, so it functions as four data buses like a sense amplifier. DB+~DB4
Therefore, the four columns that are simultaneously accessed in parallel by steps 101 to 104 are connected to four adjacent stages of the shift register. Therefore, the parallel 4-bit write or read data by random access is also continuous at the output of the shift register.

In the embodiment described above, the data bus and the sense amplifier are connected through the transfer gate, but it goes without saying that the data bus may be arranged and connected to the other end of the bit line.

〔Effect of the invention〕

As explained above, according to the present invention, writing and reading of data is made faster due to the multi-bit configuration, but furthermore, since the output of the shift register is used for high-speed image processing, simultaneous input data of many pits can be processed quickly. It is necessary that there is a correlation between the
It is possible to create a correlation between the processing and the shift register output, and it is possible to process temporally close data together. Therefore, by making such data related to each other possible, for example, in image processing, it is possible to process a certain specific area with high efficiency. As a result, it is possible to achieve an equivalently high transfer rate by combining the multi-bit configuration and shift register according to the present invention. .

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a semiconductor memory device as an embodiment of the present invention, and FIG. 2 is a detailed block diagram of the device of FIG. 1. (Explanation of symbols) 1... Column decoder 2... Row decoder Ilo... Input/output device SA... Sense amplifier SR... Shift register

Claims (1)

[Claims] 1. In a semiconductor memory device that combines a random access memory with a multi-bit input/output configuration and a shift register for reading, each column output of the random access memory is made to correspond to each stage of the shift register. Each column output data is configured to be output as serial data in accordance with the transfer operation of the shift register, and the input/output device for multiple bit input/output connects multiple columns corresponding to adjacent multiple stages of the shift register in parallel. What is claimed is: 1. A semiconductor memory device characterized in that the data of multiple bits written or read simultaneously in parallel access by the input/output device is continuously accessed even in serial data output.