JPH0317137B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt control device, and more particularly to an interrupt control device with programmable priorities.

Interrupt control refers to the central processing unit (CPU)
) is a control for temporarily interrupting program execution due to some factor during program execution, and executing a processing program according to the factor. Therefore, there are various interrupt sources depending on the data processing system. Interrupt control applied to a microcomputer as a system will be explained below.

Generally, interrupt factors in a microcomputer can be divided into external factors and internal factors. External factors include those for recognizing that the outside of the microcomputer has entered a special state, and processing requests from external peripheral devices to the microcomputer. Internal factors include elapse of a set time by an internal timer and a processing request to the microcomputer from a built-in peripheral function at the end of serial data transfer. If there are multiple interrupts, it may be necessary to disable some interrupts for program processing. This prohibition is called "masking interrupts."

When there are various interrupt factors, a plurality of factors may occur simultaneously, or another interrupt factor may occur during a certain interrupt process. (Multiple Interrupts) For example, an internal timer interrupt request and a data transfer end interrupt request may occur simultaneously, or an external interrupt request may occur during internal timer interrupt processing. In such a case, the question becomes which of the two types of interrupt processing should be prioritized.

For example, if there is an internal timer interrupt and an external interrupt, the internal timer is used to send a signal to the outside at every set time, and when controlling an external device in real time, the internal timer interrupt is prioritized and the internal timer interrupt is If a signal is not outputted to the outside as soon as this occurs, the external device cannot be controlled at the set time. Furthermore, when inputting data from the outside at high speed using external interrupts, if the external interrupts are not prioritized, response to processing requests from external peripheral devices will be delayed. In this way, the priorities of various interrupts differ depending on the application, so
Priority must be able to be set arbitrarily. Also,
Even during interrupt processing, if a high-priority interrupt occurs, it is necessary to configure the system so that the interrupt processing program can be executed.

However, in the past, it was expensive to set the priority order arbitrarily, so in low-cost systems, the interrupt priority order was fixed for each interrupt factor. This has caused problems in some applications. In the above example, if the internal timer interrupt is fixed at a higher priority than the external interrupt, when inputting external data at high speed using an external interrupt, mask the internal timer interrupt and change the priority. You must do so. Then, there was a drawback that internal timer interrupts could not be used.

In addition, conventionally, when another interrupt request is received during interrupt processing, in order to accept only the one with a high priority, it is necessary to mask that interrupt and interrupts with lower priority during interrupt processing. I was dealing with it. However, this method requires complicated procedures such as setting a mask every time interrupt processing is started, saving the mask state and changing the mask when entering multiple interrupt processing, and restoring the saved mask when returning from multiple interrupt processing. There was something I had to do.

The present invention has been made in view of the above points, and
It is an object of the present invention to provide, at a low price, an interrupt control device which is suitable for all application fields and is capable of setting and changing interrupt reception priorities to predetermined orders and does not require complicated procedures even in multiple interrupt processing.

According to the present invention, there is provided a priority designation section that designates the priority of an interrupt whose contents can be changed by program operation, a scanning signal that scans the contents of the priority designation section from the top of the priority order at a predetermined cycle, and a detection unit that detects a match with the contents of the priority designation unit; an interrupt request storage unit that stores that the interrupt source has generated an interrupt request; and an interrupt request control unit that enables or disables the interrupt request. an interrupt acceptance unit that generates an interrupt acceptance signal when the interrupt request storage unit stores the interrupt request, the detection unit detects a match, and the interrupt request control unit detects that the interrupt request is enabled; Controls the generation of the scanning signal and stores the priority order of interrupts accepted based on the interrupt acceptance signal.
An interrupt control device is obtained that includes a control section that sends an interrupt signal to a CPU.

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. Here, four types of interrupt generation sources, A, B, C, and D, will be explained. Subscripts A, B, C, and D in the numbers indicate parts involved in processing interrupt requests from interrupt sources A, B, C, and D, respectively. The parts surrounded by broken lines in FIG. 1 that are involved in processing interrupt requests from the respective interrupt sources have exactly the same configuration. The portion that processes the interrupt request from interrupt source A will be described below.

The acceptance priority of each interrupt is written in the priority designation unit 105-A using a signal controlled by a program. The control unit 101 generates a scanning signal 1 obtained by scanning the priority order from the highest priority order.
Outputs 02. The detection unit 104-A compares this scanning signal 102 with the priority contents written in each priority designation unit 105-A, and if a match is detected, outputs a match signal 109-A. The interrupt reception unit 108-A outputs the match signal 109-A, the interrupt request control unit 106-A enables the interrupt request, and the interrupt request storage unit 107-A stores the interrupt request 100-A. When detecting that there is an interruption, it outputs an interrupt acceptance signal 110-A.
The parts corresponding to interrupt sources B, C, and D also function in exactly the same way.

Next, the operation of the control section 101 will be explained. Control part 1
01 changes the scanning signal 102 from the highest priority one to the lowest priority one by one, and if the interrupt acceptance signals 110-A, B, C, and D are not output, the scanning signal 102 is When the signal 102 reaches the lowest priority, scanning continues again starting from the highest priority. If any of the interrupt acceptance signals 110-A, B, C, and D is output, the control unit 101 stores the priority order of the accepted interrupt, and the scanning signal 102 corresponds to the priority order stored in the control unit 101. That is, when the priority level becomes equal to that of the accepted interrupt, the scanning signal 102 is set to the highest priority level, and while the CPU is processing an interrupt, the scanning signal 102 is set from the highest priority level to the priority level of the interrupt being processed. Vary between. and,
When an interrupt processing end signal 113 is sent from the CPU, the control unit 101 changes the stored priority order of the interrupt being processed. When returning from multiple interrupts, the priority is set to that of the interrupt to which the return destination is returned, and if it is not a multiple interrupt, the stored priority is erased and the initial state is returned.

FIGS. 2a to 2j are timing charts showing the operation of the present invention. Signals 102, 109-A, B,
C, D, and 103 correspond to the same numbered signals in FIG. 1, respectively. Signal 111 is an interrupt request signal from interrupt source C, signal 112 is interrupt source B
This is an interrupt request signal from Storage data 114 stored in the control unit 101 indicates the priority of the interrupt currently being processed. However, the priority is 0, 1,
Numbers 2 and 3 are higher in order.

The operation of the present invention will be explained with reference to FIGS. 1 and 2. First, a priority is written in each priority designation section using signals controlled by the program.
Now, 0 is in the priority order specification section 105-A, 105
-B has 1, 105-C has 2, 105-D
Assume that 3 is written in . When there is no interrupt request or when interrupts are disabled, when the scanning signal 102 changes from 0, 1, 2, 3, the coincidence signal 1 is generated.
09-A, B, C, and D each change like the period P in FIG.

Here, it is assumed that an interrupt request is received from the interrupt source C at timing _T1 , and the interrupt is permitted. When the scanning signal 102 becomes 2 at timing _T2 and a coincidence signal 109-C is generated, an interrupt is accepted and an interrupt signal 103 is sent to the CPU.
At this time, the control unit 101 stores the priority level 2 of the accepted interrupt (stored data 114). When an interrupt is accepted and the CPU is executing interrupt processing with priority level 2, the scanning signal 102 is transmitted to the stored data 114.
If it becomes equal to , it returns to 0 again (timing
T ₃ ), only interrupts with priorities 0, 1, and 2 can be accepted.

Next, assume that a high-order interrupt request occurs from interrupt source B at timing _T4 . If interrupts from B were enabled, the scanning signal 102 would be 1.
Then, a coincidence signal 109-B is generated. At timing T5, the interrupt is accepted and an interrupt signal 103 is sent to the CPU. And the stored data 114 is 2
Changes from to 1. When the scanning signal 102 becomes 1, it returns to 0 again (timing T6), and the priorities are 0 and 1.
Only interrupts can be accepted.

When multiple interrupt processing is completed, signal 11 is sent from the CPU.
When 3 is sent (timing T7), memory data 1
14 changes from 1 to 2, and the scanning signal 102 changes from 0 to 2.
The priority will change to 1, 2, and the priority will be 0, 1,
2 interrupts can now be accepted.

The interrupt processing for interrupt source C has also finished, and the CPU
When signal 113 is sent from (timing T8),
The stored data 114 disappears and returns to the initial state in which all interrupts can be accepted.

Next, a specific circuit example of the embodiment shown in FIG. 1 of the present invention is shown in FIG. Figure 3 is 104- in Figure 1.
A, 105-A, 106-A, 107-A, 10
FIG. 8 is a circuit diagram of an example of a portion 8-A. R.S. flip-flops 301-A and 302-A are flip-flops that store the upper bit and lower bit when the priority is expressed in 2 bits, respectively.
They form a set and constitute a priority order designation section 105-A.

The priority value is set to CPU30 depending on the program.
Writing is programmable from 0 using signals 310-A and 311-A. signal 102-1,
102-2 is the upper bit and lower bit when the scanning signal 102 is 2 bits.

Exclusive OR gates 305-A and 306-A independently compare the upper bits of the priority order with the upper bits 102-1 of the scanning signal, and the lower bits of the priority order and the lower bits 102-2 of the scanning signal, respectively.
If they match, a logical value of "0" is output. Therefore, when the priority and the scanning signal 102 are equal, the NOR gate 3
07-A outputs a logic value "1" as a match signal 109-A. The two exclusive OR gates and one NOR gate constitute the detection section 104-A.

The R/S flip-flop 303-A is an interrupt mask register, and the interrupt request controller 106-A
corresponds to signal 312- when masking interrupts.
A is used to set flip-flop 303-A, and when not masked, reset it. Flip-flop 304-A is an interrupt request flag, which is set when an interrupt request signal 313-A is sent from the interrupt source, and when no interrupt request is generated.
Or, it is reset when the output of AND gate 308-A is "1". This interrupt request flag 304-
A corresponds to the interrupt request storage section 107-A.

108-A is an AND gate, and a match signal 109
When -A has a logical value of "1", the R.S. flip-flop 303-A, which is a mask register, is reset and the interrupt request flag is set, an interrupt acceptance signal 110-A is output. This AND gate constitutes the interrupt reception section 108-A.

When the vector generation unit 309-A receives the interrupt confirmation signal 314 from the CPU 300, it outputs the vector address 313-A of the accepted interrupt to the CPU 300. The interrupt request flag 304-A is set to the AND gate 308-A when the interrupt acceptance signal 110-A is "1" and the interrupt confirmation signal 314 is "1".
It is reset by the output of A.

FIG. 4 shows 1 of the control section 101 in the embodiment of FIG.
An example circuit diagram is shown. Signal 102-1, 102-2
are T-flip-flops 401 and 402, respectively.
This is the output of Signal 102-2 is clock signal 4
The signal 102-1 is inverted at the falling edge of signal 102-2. That is, T-flip-flops 401 and 402 are quaternary counters that count clock signal 403. Signals 102-1 and 102-2 represent the upper and lower bits of the scanning signal 102, respectively.
The quaternary counter constituted by T-flip-flops 401 and 402 is reset when the output of NOR gate 404 becomes logic "1".

When any of the interrupt acceptance signals 110-A, B, C, and D is output, the interrupt signal 103, which is the output of the OR gate 405, becomes "1". At this time, when the signals 102-1 and 102-2 are both "0", the output of the AND gate 406 becomes "1", so
R.S-flip-flop 407 is set. Similarly, the signal 102-1 is "0", and the signal 102-1 is "0".
-2 is “1”, the output of the AND gate 408 is “1”, so the R/S flip-flop 4
09 is set, and when the signal 102-1 is "1" and the signal 102-2 is "0", the AND gate 410
Since the output of
When both 2-2 are "1", the output of the AND gate 412 becomes "1", so the R.S. flip-flop 113 is set.

When an interrupt is accepted and the interrupt signal 103 becomes "1", the R/S flip-flops 407, 409, 4 corresponding to the priority of the interrupt are activated.
One of 11,413 is set. R・
S-flip-flop 407, 409, 411,
413 indicates that interrupts with priorities 0, 1, 2, and 3 have been accepted, respectively. The interrupt signal 103 causes the T-flip-flop 401 to
The clock 425 is supplied to the AND gate 424.
prohibited.

And gate 414, 415, 416, 41
7. When the priority of the interrupt being accepted and the scanning signal 102 become equal, the OR gate 418 outputs T-
A signal for resetting flip-flops 401 and 402 is output. However, while the interrupt signal 103 is "1", the AND gate 423 prohibits resetting. R・S-Flip Flop 40
7 is reset and R.S. flip-flop 4 is reset.
When 09 is set, that is, priority 1
During interrupt processing, if the signal 102-1 becomes "0" and the signal 102-2 becomes "1", when the interrupt signal 103 becomes "0", the T-flip-flops 401 and 402 are reset and the signal 102 becomes "0". -1,
102-2 both become "0".

Next, R・ indicates the priority of the interrupt currently being accepted.
S-flip-flop 407, 409, 411,
The reset operation of 413 will be explained. When the interrupt end signal 113 becomes "1", the R.S. flip-flop 407 is set.
- Flip-flop 407 is reset.
When the R.S. flip-flop 407 is reset, the output of the AND gate 419 is "1".
Therefore, the R.S. flip-flop 409 is reset. R・S-Flip Flop 40
When both 7 and 409 are reset, the output of AND gate 420 becomes "1", so R.S.
- Flip-flop 411 is reset.
R・S-Flip Flop 407, 409, 41
When all 1's have been reset, the output of AND gate 421 becomes "1", so R.S. flip-flop 413 is reset. When the interrupt end signal 113 becomes "1" in this way, the R.S. flip-flops indicating the highest priority among the R.S. flip-flops indicating the priority of the accepted interrupts are reset in order.

According to the present invention, it is possible to obtain an interrupt control device that is suitable for all kinds of application fields, which can set and change the interrupt reception priority order to a predetermined order, and which does not require complicated procedures even in multiple interrupt processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIGS. 2 a to j are timing charts of its operation, and FIG. 3 shows a priority designation section, an interrupt acceptance control section, FIG. 4 is a circuit diagram of an example of an interrupt request storage section, a detection section, and an interrupt acceptance section. FIG. 4 is a circuit diagram of an example of a control section in the embodiment of FIG. 101...Control unit, 104A-D...Detection unit,
105A-D...Priority designation section, 106A-D
...Interrupt request control unit, 107A-D...Interrupt request storage unit, 108A-D...Interrupt reception unit.

Claims (1)

[Claims] 1. A priority designation section that specifies the priority of an interrupt, and a detection device that detects a match between the content of the priority designation section and a scanning signal that scans the contents of the priority designation section from the highest priority level at a predetermined cycle. an interrupt request storage unit that stores information that an interrupt source has generated an interrupt request; and an interrupt request storage unit that stores an interrupt request and outputs an interrupt acceptance signal when the detection unit detects a match. An interrupt reception unit that generates an interrupt, and a control unit that controls the generation of the scanning signal, stores the priority order of the accepted interrupt based on the interrupt reception signal, and sends the interrupt signal to a central control unit. Control device.