JP3093374B2 - Interrupt controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt controller built in a microcomputer.

[0002]

2. Description of the Related Art Generally, a microcomputer has a configuration as shown in FIG. In the microcomputer 1, the CPU 2 performs processing according to the instructions stored in the memory 3. The peripheral function 5 is controlled by writing or reading data (hereinafter referred to as access) via the CPU 2 and the internal bus 6, and operates independently of the CPU 2. The peripheral function 5 includes a timer, an external interrupt signal, and the like. For example, when the timer reaches a certain value or when there is an external input pulse (hereinafter referred to as an external interrupt), the peripheral function 5 If detected, C
The peripheral function 5 generates an interrupt request signal 7 for the PU2 to detect. The interrupt request signal 7 is input to the interrupt controller 4. The interrupt controller 4 performs a state in which an interrupt processing request may be sent to the CPU 2 (interrupt enabled state), determines the presence / absence of another interrupt request, and determines the priority of the interrupt request. Interrupt processing request signal 8
To send to. When the CPU 2 detects and receives the interrupt processing request signal 8, it outputs various control signals 9 such as a signal indicating that the interrupt processing request signal 8 has been received to the interrupt controller 4. Upon receiving the interrupt processing request, the CPU 2 interrupts the processing being executed up to that point and executes the interrupt processing corresponding to the corresponding interrupt request signal 7.

FIG. 6 is a block diagram of a conventional interrupt controller, and its operation will be described with reference to a timing diagram of FIG. In FIG. 6, INT0, INT1, INT2, and INT3 are interrupt request signals 7 output from the peripheral function 5, and the respective interrupt request signal control devices 11,
12, 13, and 14. Since the interrupt request signal control device 11, the interrupt request signal control device 12, the interrupt request signal control device 13, and the interrupt request signal control device 14 have the same configuration, the interrupt request signal control device 11 will be described. When the interrupt request signal 7 is generated and INT0 becomes "1", the RC flip-flop 137 which is an interrupt request flag (hereinafter, referred to as IF0 flag) is set to "1". CPU2
Points to the address of the interrupt request signal control device 11 on the internal address bus, outputs data to the internal data bus 149 to generate a write signal, and the output 115 of the write signal control circuit 128 changes to "1". From 149, the data output by the CPU 2 is written to the latch 142 which is a mask bit. When the content of the mask bit is "1", the output of the AND circuit 638 is fixed to "0" by the inverter 143, but when the content of the mask bit is "0", the output of the AND circuit 638 is set to the EI signal. It is determined by the interrupt request flag. The EI signal is a signal for permitting the interrupt processing. When the EI signal is "1", the interrupt processing is permitted. Therefore, INT0 is “1”, the mask bit is “0”, and the EI signal is “1”.
At this time, the output of the AND circuit 638 becomes “1”, and the output of the OR circuit 125 also becomes “1”. When the output 131 from the interrupt request signal control device 11 becomes "1", the output of the inverter 119 becomes "0", and the AND circuits 122, 1
23 and 124 are fixed to "0". Similarly, when the output 132 from the interrupt request signal control device 12 becomes "1", the AND circuits 123 and 124 are fixed at "0". Similarly, output 1 from interrupt request signal control device 13
When 33 becomes "1", the AND circuit 124 is fixed at "0". The output of the AND circuit 638 and the AND circuit 122;
Each output of 123 and 124 is input to the OR circuit 125. That is, when a plurality of interrupts occur simultaneously, INT0, INT1, INT2, INT3
, And is input to the OR circuit 125. CL
K is the timing clock, and the latch 126
Latches the output "1" of the OR circuit 125 at the timing when "0" is output, and INTRQ8 is output. When the CPU 2 detects that the INTRQ 8 is “1”, the CPU 2 starts interrupt processing after a series of processing such as saving the processing address of the program currently being executed and saving the program status. First, the OEVC signal is output from the CPU 2 and input to the output buffer 130. When any of the outputs of the output and the AND circuit 122, 123 and 124 of the AND circuit 638 becomes "1", INT0, INT
The vector interrupt processing address corresponding to each of the interrupt processing of 1, INT2 and INT3 is output from the vector table address 129 to the internal data bus 149 via the output buffer 130. In the CPU 2, the interrupt processing request signal 7 is set to I based on the vector interrupt processing address.
It is determined which interrupt NT0, INT1, INT2 or INT3 has issued. Next, CPU2
Of the CLRIF signals among the control signals 9 is set to "1". When the CLRIF signal becomes “1”, the AND circuit 63
The outputs of the AND circuits 135 of the interrupt request signal control device 11, the interrupt request signal control device 12, the interrupt request signal control device 13, and the interrupt request signal control device 14, in which the outputs of 8, 122, 123 and 124 are "1". Becomes "1", and the interrupt request flag is reset to "0". The reset signal is output from the interrupt controller 4
When the reset signal becomes "1", the interrupt request flag becomes "0" and the mask bit becomes "1".
Is initialized to

Now, for INT0, INT1, INT2, and INT3, the mask bits are "0",
The case where the "0", "0", "0", and EI signals are set to "1" will be described with reference to the timing chart of FIG. FIG.
If INT0 becomes "1" at the timing T2, the IF0 flag is set to "1". Since the inverter 143 is “1” and the EI signal is “1”, the AND circuit 638 outputs “1”. Then, the output of the OR circuit 125 becomes “1” and the CL at the timing T2
At the timing when K is “0”, “1” is output from the latch 126, and INTRQ8 is output. INT at CPU2
OEVC at T6 timing after RQ8 is accepted
A signal is input. The output buffer 130 is rendered conductive by the OEVC signal, and the vector interrupt processing address is output to the internal data bus 149. CLRIF signal is T10
If it becomes "1" at the timing, the output of the AND circuit 135 of the interrupt request signal control device 11 becomes "1", and the IF0 flag is reset to "0" via the OR circuit 136. The output "0" of the RS flip-flop 137, which is the IF0 flag, is supplied to the AND circuit 638 and the OR circuit 1
25, and is output as INTRQ8 via the latch 126. On the other hand, if INT1 becomes “1” at timing T5, the IF of the interrupt request signal control device 12
The gate corresponding to the 0 flag is set to "1". The gate corresponding to the inverter is “1” and the EI signal is “1”
Therefore, “1” is output from the gate corresponding to the AND circuit 638 and input to the AND circuit 122. Since the output of the gate corresponding to the inverter 143, which is the other input of the gate corresponding to the AND circuit 122, is “0”, the output of the gate corresponding to the AND circuit 122 is fixed to “0”. CLRI at T10 timing
When the F signal is input and the output of the inverter 119 becomes “1”, the output of the AND circuit 122 becomes “1”. Then, the output of the OR circuit 125 becomes “1”, and C
At the timing when LK is “0”, “1” is output from the latch 126, and INTRQ8 is output. Hereinafter, INT0
The same processing as that of the interrupt acceptance is performed. In this way, the output of INTRQ8 by INT1 is kept waiting until the IF flag of INT0 having a higher priority is reset to "0". Similarly, I by INT2 and INT3
The NTRQ output is also kept waiting until the IF flags of the interrupt requests with high priority are all reset to "0".

[0005]

However, the conventional interrupt controller uses INT
Since RQ is always output, if you want to perform interrupt processing only once when multiple interrupt requests are collected,
It has been necessary to provide software processing for detecting the completion of a plurality of interrupt requests or to provide a circuit outside the microcomputer.

[0006] In a recent micro-computer, becomes a colorful interrupt application for the application of real-time control, such as high-speed processing, also only interrupt processing it at a time when a plurality of interrupt requests are met in order to perform fine-grained control Is required. As an example of such an application, for example, there is an application such as time measurement using a timer.
Generally, in time measurement using a timer, a pulse is generated from an external function to be measured and input to an external interrupt terminal of a microcomputer. The microcomputer latches the timer value when an external interrupt is input. (Hereinafter, this operation is referred to as a capture operation, and the latch is referred to as a capture register.) This capture operation is repeated twice, and is generated by an external function from the difference between the first latched value and the second latched value, and the count cycle time of the timer. Calculate the time measurement between the applied pulses. In the microcomputer, when an external interrupt is input, an interrupt processing request is always output from the interrupt controller. Therefore, the interrupt process is started twice, and in the first interrupt process, the value of the capture register is saved after detecting that it is the first interrupt. In the second interruption processing, the time measurement processing is performed after detecting that the interruption is the second interruption. But,
If two capture registers are prepared, the first interrupt processing is completely useless, causing a reduction in the processing speed of the entire microcomputer.

As described above, in the conventional example, control is performed by software processing for detecting that a plurality of interrupt requests are completed or by providing a circuit outside the microcomputer. However, when the control is performed by software processing, the processing speed of the entire microcomputer is reduced, and when an external circuit is provided, there is a disadvantage that the applied system becomes large and the cost increases.

An object of the present invention is to provide an interrupt controller having means for detecting that a plurality of interrupt request signals generated by peripheral functions have been set.

[0009]

The present invention is incorporated in a microcomputer having a plurality of peripheral functions for issuing an interrupt request signal, and controls the interrupt request signal to output an interrupt processing request signal to a central processing unit. An interrupt controller that stores an interrupt request signal issued by the plurality of peripheral functions, and makes a determination based on a determination condition with respect to the interrupt request signal stored in the storage circuit. A condition determination circuit that outputs a determination signal indicating that the determination has been made, and a determination signal from the condition determination circuit or the interrupt request signal are simultaneously transmitted.
An interrupt processing request signal output device that outputs an interrupt processing request signal to the central processing unit only once when a plurality of signals are detected.

[0010]

The interrupt request signals issued by the plurality of peripheral functions are stored. The stored interrupt request signal is determined based on a determination condition for determining that a predetermined number of interrupt request signals are stored within a predetermined period, and a determination signal indicating that the determination condition is satisfied is output. I do.
When the determination signal or the interrupt request signal is detected, an interrupt processing request signal is output to the central processing unit.

[0011]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of the interrupt controller of the present invention. In FIG. 1, an AND circuit 135, an OR circuit 136, I
RS flip-flops 137 and I which are F0 flags
The RS flip-flop 139 as the F01 flag corresponds to a storage circuit of an interrupt request signal, the latch 140, the latch 142 as a mask bit, the inverter 143, the OR circuit 141, and the AND circuit 138 correspond to a condition determining circuit. The reference numeral 125 and the latch 126 correspond to an interrupt processing request signal output device.

In this embodiment, as shown in FIG. 5, an AND circuit 135, an OR circuit 136, and an R circuit 136 are storage circuits for storing interrupt request signals 7 issued by a plurality of peripheral functions 5.
Condition determination for making a determination based on a determination condition with respect to the S flip-flop 137 and the RS flip-flop 139 and the interrupt request signal 7 stored in the storage circuit, and outputting a determination signal indicating that the determination condition is satisfied Latch 140, Latch 142, OR circuit 141
And an AND circuit 138; an OR circuit 125 which is an interrupt request signal output device for outputting an interrupt processing request signal 8 to the central processing unit 2 when the determination signal or the interrupt request signal 7 from the condition determination circuit is detected; 126.

Next, the operation of this embodiment will be described. FIG.
3 is a timing chart showing the operation of FIG. In FIG. 1, FIG.
Since the functions indicated by the same numbers perform the same operations, the description will be omitted, and different parts will be described. In FIG. 1, an RS flip-flop 139 outputs an interrupt request IN to a set input.
T01 is connected, and the reset input is connected to an OR circuit 136.
Are connected, and the same operation as that of the RS flip-flop 137 is performed. The output of the RS flip-flop 139 is input to the OR circuit 141. The output of the latch 140 is connected to the other input of the OR circuit 141. Latch 140
1 bit of the internal data bus 149 is input as data, a select signal 145 is input as a clock input from the write control circuit 128, and data can be written from the CPU 2 similarly to the latch 142 which is a mask bit described in the conventional example. It has a configuration. When “1” is written to the latch 140, “1” is input to the OR circuit 141, and the output of the OR circuit 141 is fixed at “1”.
When “0” is written in 40, the OR circuit 141
Is input to the RS flip-flop 1
When the output of 39 is “1”, the output of the OR circuit 141 becomes “1”. The output of the OR circuit 141 is the AND circuit 13
8 has been entered. The other input of the AND circuit 138 is IF
The output of the RS flip-flop 137, the output of the inverter 143, and the interrupt enable signal EI, which are 0 flags, perform the same operations as in the conventional example, and thus description thereof is omitted. Therefore, when the interrupt enable signal EI and the mask bit are “1” and “0”, respectively, the latch 1
When 40 is "1", the output of the AND circuit 138 is RS
The output value of flip-flop 137 is output, and latch 1
When 40 is "0", the output of the AND circuit 138 is RS
Flip-flop 137, RS flip-flop 139
"1" is output only when the outputs are "1" and "1", respectively. The output of the AND circuit 138 is the OR circuit 125
And is output as INTRQ8 via the latch 126.

Next, the operation of FIG. 1 will be described with reference to the timing chart of FIG. FIG. 2 is a timing chart showing the operation of the interrupt controller 4 when the latch 140 is set to "0" when the interrupt enable signal EI and the mask bit are "1" and "0", respectively. In FIG. 2, it is assumed that INT0 becomes "1" at timing T2. When INT0 becomes “1”, the RS flip-flop 137 is set to “1” at timing T2. The output of the RS flip-flop 137 is input to the AND circuit 138, but the output of the OR circuit 141, which is the other input of the AND circuit 138, is "0", so that the output of the AND circuit 138 remains unchanged at "0". . Next, assuming that INT01 becomes “1” at timing T5, the RS flip-flop 139
Is set to “1” at timing T5. The output “1” of the RS flip-flop 139 is input to the AND circuit 138 via the OR circuit 141. Therefore, the output of the AND circuit 138 becomes “1” at timing T5, and is input to the latch 126 via the OR circuit 125. The latch 126 latches “1” at the falling edge of the CLK at the timing of T5 by the inverter 127 which is the latch clock input, and outputs it at the same time as INTRQ8. Next, the CPU 2 outputs an OEVC signal at timing T8, and the interrupt controller 4 outputs a vector address to the internal data bus 149. Next, T
It is assumed that the CLRIF signal is output from the CPU 2 at twelve timings. The CLRIF signal is input to an AND circuit 135 and an AND circuit corresponding to the AND circuit 135 of each of the interrupt request signal control device 12, the interrupt request signal control device 13, and the interrupt request signal control device 14. AND circuit 135 and interrupt request signal control device 12,
The signals are input to AND circuits corresponding to the AND circuits 135 of the interrupt request signal control device 13 and the interrupt request signal control device 14, respectively. AND circuit 135, interrupt request signal control device 12, interrupt request signal control device 13,
AND circuit 1 of each interrupt request signal control device 14
The other inputs of the AND circuit corresponding to 35 are the outputs of the AND circuit 138, the AND circuit 122, the AND circuit 123, and the AND circuit 124, respectively. Since only the AND circuit 138 is "1", the AND of the interrupt request signal control device 11 Only the circuit 135 becomes “1”. The output “1” of the AND circuit 135 is input to the reset side of the RC flip-flop 137 and the RS flip-flop 139 via the OR circuit 136, and the RS flip-flop 137 and the R
The S flip-flop 139 is reset to “0”.
Outputs “0” of the RS flip-flops 137 and 139 are input to an AND circuit 138,
The output of the AND circuit 138 becomes "0". AND circuit 1
The output "0" of 38 is an OR circuit 125 and a latch 126.
Is output as INTRQ8 at the falling edge of CLK at timing T12. As described above, in the present embodiment, when there is a "1" input from the two signals INT0 and INT01, INTRQ8 is generated only once. Also, INT1 and INT11 or INT2
Similarly, when INT1 or INT3 and INT31 receive "1" input from two signals, INT
RQ8 can be generated only once.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 3 shows the interrupt controller 4
FIG.

In FIG. 3, an AND circuit 135 and an OR circuit 13
6, RS flip-flop 137 as IF0 flag,
An RS flip-flop 139 serving as an IF01 flag and an RS flip-flop 339 serving as an IF02 flag correspond to a storage circuit for an interrupt request signal.
The latch 340, the latch 142, the inverter 143, the OR circuit 141, the OR circuit 341 and the AND circuit 338 correspond to a condition determining circuit, and the OR circuit 125 and the latch 126 correspond to an interrupt processing request signal output device.

FIG. 4 is a timing chart of FIG. The second embodiment is completely the same control as the first embodiment except that the interrupt request signal input to each interrupt request signal control register is one signal and three signals are added. The description of the operation of the circuit with the same number is omitted. In FIG. 3, the RS flip-flop 339 has a set input connected to the interrupt request INT02, a reset input connected to the output of the OR circuit 136, and performs the same operation as the RS flip-flop 137 and the RS flip-flop 139. The latch 340 has a configuration in which writing from the CPU 2 can be performed similarly to the latch 140 described in the first embodiment, and its output is input to the OR circuit 341. Therefore, the latch 340 is provided in the same manner as in the first embodiment.
The output of the OR circuit 341 is fixed to “1” when “1” is written to the latch 340, and the OR is output when the output of the RS flip-flop 339 is “1” when “0” is written to the latch 340. The output of the circuit 341 becomes “1”. The output of the OR circuit 341 is input to the AND circuit 338. The other inputs of the AND circuit 338 are the output of the RS flip-flop 137, the output of the RS flip-flop 139, the output of the inverter 143, and the interrupt enable signal E
I, which operate in the same manner as in the conventional example and the first embodiment, and a description thereof will be omitted. Therefore, the interrupt enable signal EI and the mask bit are "1" and "0", respectively.
Latch 140 and latch 340 are "0"
In the case of “0”, the outputs of the AND circuit 338 are RS flip-flops 137, 139, R
The output of the S flip-flop 339 is “1”,
"1" is output only when "1" or "1". The output of the AND circuit 338 is output from the OR circuit 125 and the latch 126.
Is output as INTRQ8 via

Next, the operation of FIG. 3 will be described with reference to the timing chart of FIG. FIG. 4 shows the operation of the interrupt controller 4 when the latch 140 and the latch 340 are set to "0" and "0", respectively, when the interrupt enable signal EI and the mask bit are "1" and "0", respectively. FIG. In FIG. 4, the same operation as that of the first embodiment is performed until the timing T4, and thus the description is omitted. It is assumed that the interrupt request signal INT01 becomes “1” at timing T5. When INT01 becomes “1”, the RS flip-flop 139 which is the IF01 flag is set to “1” at timing T5. The output of the RS flip-flop 139 is input to the AND circuit 338.
Since the output of the OR circuit 341 as the other input of the AND circuit 338 is “0”, the output of the AND circuit 338 remains “0” and does not change. Next, assuming that INT02 becomes "1" at the timing T8, the RS flip-flop 339 is set to "1" at the timing T8. The output “1” of the RS flip-flop 339 is input to the AND circuit 338 via the OR circuit 341. Therefore, at the timing T8, the output of the AND circuit 338 becomes “1”, and the OR circuit 12
5 to the latch 126. The latch 126 latches “1” at the falling edge of the CLK at the timing of T8 by the inverter 127, which is the latch clock input, and outputs it at the same time as INTRQ8. Next, an OEVC signal is output from the CPU 2 at timing T11, and a vector address is output from the interrupt controller 4 to the internal bus 149. Next, it is assumed that a CLRIF signal is output from the CPU 2 at timing T15.
The CLRIF signal is supplied to the AND circuit 135 and the AND circuit 13 of each of the interrupt request signal control device 12, the interrupt request signal control device 13, and the interrupt request signal control device 14.
5 and is input to the AND circuit corresponding to 5. AND circuit 13
5 and the other inputs of the AND circuits corresponding to the AND circuits 135 of the interrupt request signal control device 12, the interrupt request signal control device 13, and the interrupt request signal control device 14, respectively, are AND circuit 338, AND circuit 122, AND circuit 123, AND circuit Since this is the output of the circuit 124 and only the AND circuit 338 is “1”, only the AND circuit 135 of the interrupt request signal control device 11 becomes “1”. The output “1” of the AND circuit 135 is output via the OR circuit 136 to the RS flip-flop 137 and the RS flip-flop 1
39 and the RS flip-flop 339 are input to the reset side, and the RS flip-flop 137, the RS flip-flop 139, and the RS flip-flop 339 are reset to “0”. RS flip-flop 13
7, the output “0” of the RS flip-flop 139 and the RS flip-flop 339 is input to the AND circuit 338, and the output of the AND circuit 338 becomes “0”. The output value “0” of the AND circuit 338 is output as INTRQ8 via the OR circuit 125 and the latch 126 at the falling edge of the CLK at the timing T12. Thus, in this embodiment, INT0, INT01, INT0
INTRQ8 occurs only once when there is a "1" input from all three signals. Also, INT1, I
NT11, INT12 or INT2, INT21, I
Similarly, in NT22 or INT3, INT31, INT32, when "1" is input from all three signals, I
NTRQ8 can be generated only once.

In this embodiment, an interrupt processing request is generated only when the interrupt requests are prepared. However, even if the condition for determining the state of the peripheral function is arbitrarily changed and special conditions are set, the effect is not changed. Absent.

[0020]

As described above, the present invention does not reduce the processing speed of the entire microcomputer and does not provide an external condition detection circuit. Has an effect that can be generated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the second embodiment of the present invention.

FIG. 5 is a configuration diagram of a general microcomputer.

FIG. 6 is a block diagram showing the configuration of a conventional example.

FIG. 7 is a timing chart showing the operation of the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Microcomputer 2 CPU 3 Memory 4 Interrupt controller (INTC) 5 Peripheral function 6 Internal bus 11 Interrupt processing request signal controller (IC0) 12 Interrupt processing request signal controller (IC1) 13 Interrupt processing request signal controller (IC2) 14 Interrupt request signal controller (IC3) 119 Inverter 122 AND circuit 123 AND circuit 124 AND circuit 125 OR circuit 126 Latch 127 Inverter 128 Write control circuit 129 Vector address table 130 Output buffer 135 AND circuit 136 OR circuit 137 RS flip-flop 138 AND Circuit 139 RS flip-flop 140 Latch 141 OR circuit 142 Latch 143 Inverter 145 Select signal 149 Internal data bus 3 8 and circuit 340 latch 341 OR circuit 638 and circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 9/46 G06F 13/24 G06F 15/78

Claims (1)

(57) [Claims] An interrupt controller which is incorporated in a microcomputer having a plurality of peripheral functions for issuing an interrupt request signal and outputs an interrupt processing request signal to a central processing unit in response to the interrupt request signal. A plurality of storage circuits for storing an interrupt request signal issued by the peripheral function, and an output of any one of the plurality of storage circuits and an output from a latch connected to an internal data bus are input to an OR circuit. A condition determination circuit including an output and an output of the storage circuit that does not pass through the OR circuit, an output of a mask bit latch connected to an internal data bus, and an AND circuit that receives a permission signal as input, and a plurality of conditions from the plurality of condition determination circuits. The interrupt processing request signal output device which outputs an interrupt processing request signal when any one of the judgment signals is input Interrupt controller, characterized in that that.