JP2661222B2 - Pulse output device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a pulse output device for controlling peripheral devices and the like.

[Conventional technology]

Today, microcomputers are becoming more highly integrated and multifunctional due to advances in LSI technology, and various peripheral hardware have been mounted on a single chip. Above all, a pulse output device is indispensable for controlling an external mechanism such as a motor, and it is necessary to generate various pulses according to the type and properties of an external device to be controlled. Products having such a pulse output function include the μPD7811 manufactured by NEC.

Here, a conventional pulse output device will be described using a programmable rectangular wave (hereinafter, referred to as PPG) output device as an example.

FIG. 4 is a block diagram of a conventional panel output device, and FIG.
FIG. 6 is a timing chart of the operation.

The pulse output device includes a central processing unit (hereinafter, referred to as a CPU) 10 for reading and executing a program, and storage means (hereinafter, referred to as a memory) for storing programs and data.
20, a pulse output unit 30 for generating an arbitrary pulse, an interrupt control unit 40 for receiving an interrupt request from the pulse output unit 30 and requesting the CPU 10 to start an interrupt process, and an internal bus connecting these components to each other Consists of 50 and 50.

The memory 20 is a program memory for storing a program.
21 and a data memory 22 for storing processing data. The pulse output unit 30 includes a counter 31 that counts the count clock φ, first and second registers 32 and 33 that store a value to be compared with the counter 31, a counter 31 and a first
And the comparison operation of the second registers 32 and 33 is performed, and the first and second coincidence signals 41 and 42 which become active when the contents of the counter 31 and the contents of the first and second registers 32 and 33 match are output. The first and second comparators 34 and 35 perform the above-mentioned operations, and the output control circuit 36 controls a pulse output to the outside. When detecting that the first match signal 41 generated from the first comparator 34 has become active, the interrupt control unit 40 notifies the CPU 10 of the occurrence of the interrupt request by the interrupt request signal 43.

 Next, the operation of each unit will be described with reference to FIG.

The counter 31 of the pulse output unit 30 starts the counting operation after the system reset is released, and counts up every time the count clock φ is input. The first comparator 34 constantly compares the contents of the counter 31 and the contents of the first register 32, and when the contents of the two become equal, activates the first coincidence signal ("1"). When the first coincidence signal 41 becomes active, the first coincidence signal 41 sets the RS flip-flop of the output control circuit 36 ("1"), and at the same time, sets the interrupt control unit.
Output to 40 to notify the occurrence of an interrupt request. On the other hand, the second comparator 35 always compares the contents of the counter 31 and the contents of the second register 33.
Make 42 active ("1"). When the second coincidence signal 42 becomes active, the second coincidence signal 42 is output to the output control circuit 36.
Is reset ("0"), and at the same time, the contents of the counter 31 are cleared to "0". When detecting that the first coincidence signal 41 has become active ("1"), the interrupt control unit 40 activates the interrupt activation signal 43 ("1") and requests the CPU 10 to activate the interrupt processing. The CPU 10 reads and executes instructions from a program memory 21 in the normal memory 20 according to a program counter (not shown). Each time the processing of one instruction ends, the CPU1
A value of 0 determines whether or not the interrupt activation signal 43 is active (“1”). If the value is “0”, the instruction processing is repeated.
If the interrupt activation signal 43 is active (“1”),
The CPU 10 starts executing the interrupt processing program.

Next, the relationship between the operation of the pulse output unit 30 and the interrupt processing will be described with reference to the timing chart of FIG.

Now, the first register 32, the value w ₁ that determines the pulse width of the output pulse from the terminal, the value determines the pulse period P (P> w ₁₎ is set in the second comparison register 33 . Counter 31 sequentially counts the count clock phi, when the count value becomes w _1, the first comparator 34 activates the first coincidence signal 41, R- flip flop reset ( "0 of the output control circuit 36 ") And invert the pulse output. Further, the interrupt control unit 40 detects that the first coincidence signal 41 has become active, and outputs an interrupt activation signal 43 to the CPU 10. When detecting that the interrupt activation signal 43 has become active, the CPU 10 starts executing the interrupt processing program. The interrupt processing program reads the pulse width w ₂ of the pulse will be output from the data memory 22, the process of writing to the first register 32 performs. The counter 31
also performs a count-up operation after becoming w _1, now when the count value becomes P is a second comparator 35 the second coincidence signal 42
Is activated, the RS flip-flop of the output control circuit 36 is set ("1"), and the pulse output is inverted. At the same time, the counter 31 is cleared to "0" and the count-up operation is performed again.

By repeating the above processing, the pulse cycle T _P = P × tφ tφ = the cycle of the count clock φ Pulse width T _W = w _n × t φ w _n = the value of the first register 32 at the _n -th pulse (n = 1 , 2, ...) can be output.

[Problems to be solved by the invention]

The conventional pulse output device described above has a time from when a coincidence signal is generated from the comparator to when the interrupt processing ends,
Correct control may not be performed depending on the relationship with the next pulse width value set in the interrupt processing.

This phenomenon will be described with reference to the timing chart of FIG.

Now, when the count value of the counter 31 becomes w _1, a first coincidence signal 41 becomes active, R-S of the output control circuit 36
The flip-flop is set (“1”), and the pulse output level is inverted. At the same time, the interrupt controller 40 receives the first coincidence signal 41 and generates an interrupt activation signal 43. CPU10
Upon detecting that the interrupt activation signal 43 has become active, the above-described interrupt processing is started.

Next pulse set value set in this interrupt processing
w ₂ is greater than the count value of the counter 31 at the time of the set, the count value of the counter 31 becomes the w _2, a first coincidence signal 41 is generated again in one pulse period. An interrupt process corresponding to the first match signal 41, the next pulse width w ₃ will be written into the first register 32, as shown in FIG. 6, a pulse corresponding to w ₂ is not output , pulses corresponding to w ₃ is then output.

[Means for solving the problem]

In the pulse output device according to the present invention, when the pulse output unit outputs the first coincidence signal again after the output of the first coincidence signal and before the output of the second coincidence signal, A prohibition circuit is provided for prohibiting the first match signal from being output as an interrupt request signal to the interrupt control unit.

[Action]

Therefore, when the set value of the next pulse width is larger than the count value of the counter at the set time, the next pulse width will not be written to the first register.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the pulse output device of the present invention, and FIG. 2 is an operation timing diagram thereof.

This pulse output device reads and executes a program
A CPU 10, a memory 20 for storing programs and data, a pulse output unit 30 for outputting pulses, an interrupt control unit 40 for receiving an interrupt request signal 44 from the pulse output unit 30 and notifying the CPU 10, and Internal bus to connect
Consists of 50. CPU 10, memory 20, interrupt control unit 40
Is similar to that of the conventional pulse output device shown in FIG.

The pulse output unit 30 includes a counter 31 that counts the count clock φ, first and second registers 32 and 33 that store a value to be compared with the counter 31, first and second registers 32 and 33, and a counter 31. And the first and second comparison signals output by the first and second coincidence signals 41 and 42 which become active when the value of the counter 31 and the contents of the first and second registers 32 and 33 match. Devices 34 and 35, an RS flip-flop 36 for controlling the output pulse, and an RS flip-flop
From the output of 36, the first match signal 41 to the interrupt request signal 44
And an interrupt request prohibition circuit 37 for generating

Next, the operation of this embodiment will be described with reference to the timing chart of FIG.

Now, the value of the counter 31 becomes to w _1, the first comparator 34 activates the first coincidence signal 41. At this time, since the level of the pulse output from the terminal, that is, the output of the RS flip-flop 36 is low, the interrupt request signal
44 becomes active and outputs to the interrupt control unit 40, and at the same time, the RS flip-flop 36 is set ("1"). When detecting that the interrupt request signal 44 has become active, the interrupt control unit 40 outputs an interrupt start signal 43 to the CPU 10 to prompt the start of interrupt processing. CPU10 is interrupt activation signal 4
When it detects that 3 has become active, it starts interrupt processing, and stores the value w ₂ that determines the next pulse width in the first register.
Write to 32. If this w ₂ is greater than the value of the counter 31 at the time of performing the write, first coincidence signal 41 is generated again before the second coincidence signal 42 is generated. However, R-
The output of the S flip-flop 36 is at high level ( "1"), the interrupt request signal 44 is not active, therefore, does not take place even interrupt process, the first register 32 of the w ₂ value Hold. When the counter value reaches P, the second coincidence signal 42 becomes active, and R
Reset the -S flip-flop 36 ("0") and clear the counter 31 to 0. Thereafter the counter 31 continues to count-up operation, the first coincidence signal 41 becomes active again count value reaches w _2. At this time, since the output of the RS flip-flop 36 is low level ("0"), the interrupt request signal 44 becomes active, and the RS flip-flop 36 is set ("1"). That is, a pulse having a low level width (T _W2 ) corresponding to w ₂ has been output. When four interrupt request signals 44 become active, the CPU 10
Write the next pulse width w ₃ in the first comparison register 32 in the interrupt process corresponding to.

In the present embodiment, the activation of the interrupt processing by the first coincidence signal 41 is urged only during the period when the output pulse is at the low level ("0"). The same control can be easily performed simply by inputting a signal obtained by inverting the output of the RS flip-flop 36 to the prohibition circuit 37.

FIG. 3 is a block diagram of a pulse output unit of a second embodiment of the pulse output device of the present invention.

In this embodiment, the flip-flop 381 and the inverter 382
And an output control circuit 38 comprising an AND gate 383 and an OR gate 384; and an interrupt request circuit 39 comprising an inverter 391 and an AND gate 392.

Also in this case, the operation timing is exactly the same as that of the first embodiment, and the operation is performed at the timing shown in FIG. 2. However, since the circuit configuration is easier than that of the first embodiment, the design is easy. In addition, the circuit scale can be reduced.

〔The invention's effect〕

As described above, the present invention adds a simple control circuit in order to prevent an erroneous pulse output operation due to a high-speed interrupt response, and prohibits hardware from performing the same interrupt processing a plurality of times within one pulse cycle. By doing
There is an effect that accurate pulse output can be performed without being affected by the response time of the interrupt or the data of the counter.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the pulse output device of the present invention, FIG. 2 is an operation timing chart of the embodiment of FIG. 1, and FIG. 3 is a pulse in the second embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of the output unit, FIG. 4 is a block diagram of a conventional pulse output device, and FIGS. 5 and 6 are operation timing diagrams of the conventional pulse output device of FIG. 10 ... CPU, 20 ... memory, 21 ... program memory, 22 ... data memory, 30 ... pulse output unit, 31 ... counter, 32 ... first register, 33 ... second register, 34 first comparator, 35 second comparator, 36,38 pulse output control circuit, 37,39 interrupt request generation prohibition circuit, 40 interrupt request control unit, 41 First match signal, 42... Second match signal, 43... Interrupt start signal, 44... Interrupt request signal, 50.

Claims (1)

(57) [Claims] A central processing unit, storage means for storing data, a pulse output unit for outputting a pulse having a desired period and a pulse width, and an interrupt request generating unit for generating an interrupt request to the central processing unit. A pulse output unit that counts clocks and is reset by a second coincidence signal; first and second registers in which values for determining a pulse width and a period are respectively set; The first and second registers compare the values of the first and second registers, respectively, and when they match, output first and second comparators, respectively, and output a pulse to the outside by the first and second match signals. And an output control circuit for outputting the first coincidence signal when the first coincidence signal is generated.
A pulse output device that outputs an interrupt start signal to the central processing unit, and the central processing unit receives the signal and reads a value that determines the pulse width of the next pulse to be output from the storage unit and writes the read value into the first register. In the pulse output unit, after the first coincidence signal is output,
And a prohibition circuit for prohibiting the first match signal from being output to the interrupt control unit as an interrupt request signal when the first match signal is output again until the match signal is output. A pulse output device.