JPH0443302B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an interrupt control device used in microcomputers and the like, and more particularly to an interrupt control device having a programmable priority determining function.

(Explanation of the prior art) Interrupt control is a process performed by a central processing unit (hereinafter referred to as CPU).
This control is used to temporarily interrupt the program processing that is currently being executed when some factor occurs during program execution, and to execute a processing program that corresponds to the factor. Therefore, there are various interrupt sources depending on the data processing system. Interrupt factors can be divided into two types: external factors and internal factors.

External factors include those that cause the microcomputer to recognize that an external device connected to the microcomputer has entered a special state, and those that request processing from an external peripheral device to the microcomputer. On the other hand, internal factors include processing from peripheral functions built into the microcomputer, such as notifications that a timer installed inside the microcomputer has passed the set time, notifications that the serial data transfer has ended, etc. I have a request. Even if an interrupt occurs, the interrupt may be prohibited. This is called "masking interrupts."

When there are many interrupt factors, multiple factors may occur simultaneously, or another interrupt may occur while one interrupt is being processed (multiple interrupts). For example, an internal timer interrupt request and a data transfer end interrupt request may occur at the same time, or an external interrupt request may occur during internal timer interrupt processing. In such a case, the problem is which interrupt should be processed with priority.

For example, when an internal timer interrupt request and an external interrupt request occur simultaneously, the internal timer interrupt sends a signal to the outside at a certain set time interval, and when this signal is used to control an external device in real time, the internal timer Unless priority is given to interrupts and a signal is output to the outside immediately when an internal timer interrupt occurs, the external device cannot be controlled at the set time. Furthermore, when inputting data from the outside at high speed based on external interrupts, unless priority is given to the external interrupts, the response to processing requests from external peripheral processing devices will be delayed. As described above, the priority order of interrupts differs depending on the system including the microcomputer, so a function is required to change the priority order depending on the system. At this time, if an interrupt with a higher priority occurs during the processing period of a certain interrupt, the interrupt processing program with the higher priority must be configured to be executed. Furthermore, multiple interrupts may be set to the same priority, and assuming that multiple interrupts with the same priority occur simultaneously or in an overlapping manner, the interrupt processing is executed according to the predetermined priority. It is necessary to make sure that In particular, in this case, it is necessary to configure the hardware in such a way that the burden on the software can be reduced.

However, in the past, the hardware mechanism for making the priorities variable was expensive, so in microcomputers used in low-cost systems, the interrupt priorities were uniquely fixed for each interrupt factor. Therefore, there was a drawback that system applications were limited. Furthermore, in the above example, if the internal timer interrupt is fixed at a higher priority than the external interrupt, the internal timer interrupt can be masked in a system that requires high-speed input of external data using external interrupts. I had changed my priorities. However, since no internal timer interrupt processing is possible at that time, system applications are still limited. Therefore, there is a need for a function that allows internal timer interrupt processing to be performed in the middle of external interrupt processing so that both can be executed in parallel.

Furthermore, conventionally, when an interrupt with a higher priority than the accepted interrupt occurs during interrupt processing, it is accepted and the interrupt currently being executed and the interrupt with a lower priority than the accepted interrupt are forcibly masked. However, with this method, a mask must be set each time interrupt processing is started. Furthermore, in multiple interrupt processing, it is necessary to save the mask state at the time of interruption and then change the mask, and in addition, when returning from multiple interrupts, the saved mask state must be restored. .
This required complicated procedures.

(Object of the Invention) An object of the present invention is to provide an interrupt control device having a function of easily changing the priority order of interrupt requests.

Still another object of the present invention is to provide an interrupt control device that simplifies the procedure for multiple interrupts.

Still another object is to provide an interrupt control device at a low cost that can process interrupts according to a predetermined priority when a plurality of interrupts are set to have the same priority.

(Structure of the Invention) The present invention provides an interrupt control device that receives interrupt requests from a plurality of interrupt sources, and an interrupt request storage unit that stores interrupt requests for each interrupt source, and a system that can specify the interrupt requests in an arbitrary order. a priority designation section in which data indicating a designated priority is set; a scanning section that generates scanning signals in order from the highest priority; and priority data of the scanning signal and the priority designation section. a detection unit that compares the two and outputs a match signal when the two match; an interrupt request acceptance unit that accepts the interrupt request in the order in which the match signal was output; force selection of one,
The method is characterized in that it includes means for determining an interrupt request to be processed.

(Effects of the Invention) According to the present invention, since the priority determining means has a two-stage configuration, it is possible to designate a plurality of interrupt requests of the same level in the preceding stage determining means (designating section), and furthermore, this allows With respect to the plurality of interrupt requests designated by the interrupt request, a subsequent determining means (setting section) can further select one request among them according to a predetermined order. That is, by commonly supplying the outputs of a plurality of interrupt acceptance blocks (including a priority specification section), each of which is composed of the same circuit block, to a priority setting section, it is possible to Even if multiple interrupt requests are output at the same time, one request can be selected from among them. Therefore, using the present invention, multiple interrupt sources can be given the same priority. Furthermore, the number of circuit blocks can be added by simply changing the determining means at the subsequent stage, so the range of applications of the microcomputer is significantly improved.

(Description of an Embodiment) An embodiment of the present invention will be described with reference to FIG. Here, four interrupt sources 100-A, 1
00-B, 100-C and 100-D are assumed. Subscripts A, B, C, and D of the numbers in the figure indicate interrupt sources 100-A, 100-B, and 10, respectively.
The parts involved in processing interrupt requests from 0-C and 100-D are shown. The parts surrounded by broken lines in the figure that are involved in processing interrupt requests from respective interrupt sources have the same circuit configuration. The portion that processes the interrupt request from the interrupt source 100-A will be described below.

The priority order is written into the priority order designation section 105-A using a signal controlled by a program. The control unit 101 outputs the scanning signals 102 in order of priority. The detection unit 104-A uses this scanning signal 102 and its own priority order designation unit 105-
Compare with the priority written in A. As a result, if the two match, a match signal 109-A is generated. The interrupt reception unit 108-A receives the coincidence signal 1
Occurrence of 09-A and interrupt request control unit 106-A
When it is detected that the interrupt request is permitted in the interrupt request storage section 107-A and that the interrupt request is stored in the interrupt request storage section 107-A, the interrupt acceptance signal 110-A is generated. If an interrupt acceptance signal is generated in another broken line block, the interrupt acceptance signal 110-A is inputted to the priority order setting section 111 together with the other interrupt acceptance signals. Only the interrupt acceptance signal evaluated to have the highest priority among the plurality of interrupts generated simultaneously is output from the priority setting section 111 and input to the control section. If the setting unit 111 is now outputting an interrupt acceptance signal 110-A, the priority setting unit 111 outputs outputs 112-B, 112-, which indicate that an interrupt request with a high priority exists.
C, 112-D to the interrupt reception unit 10 of another block.
8-B, 108-C, and 108-D, respectively, and control is performed to set a predetermined priority order in the interrupt receiving section.

Next, the operation of the control unit 101 will be explained. Control part 1
01 changes the scanning signal 102 from the highest priority to the lower priority one by one and sends it to each block. Interrupt acceptance signal 110- after one round of scanning
If A, B, C, and D are not output, scanning is repeated in order from the highest priority. Control unit 101
When it receives any of the interrupt acceptance signals 110-A, B, C, and D, it internally stores the priority of the accepted interrupt and sets the scanning signal 102 to the highest priority. In this way, the priority order is scanned in order from the highest priority order, and when the priority order becomes equal to the priority order stored in the control unit 101, that is, the priority order of the accepted interrupt, this series of scanning is repeated. That is, while the CPU is processing an interrupt, the scanning signal 102 is changed between the highest priority order and the priority order of the interrupt being processed, and the CPU scans for occurrences of higher priority interrupts. When an interrupt processing end signal 113 is sent from the CPU, the control unit 101 changes the stored priority order of the interrupt being processed. When returning from multiple interrupts, the priority order of the interrupt to which the return destination is set is set, and if it is not a multiple interrupt, the stored priority order is erased and the initial state is returned.

FIG. 2 is a timing chart showing the operation of this embodiment. Signals 102, 109-A, B, C,
D and 103 correspond to the signals with the same numbers in FIG. 1, respectively. Data 114 stored in the control unit 101 indicates the priority of interrupts currently being processed by the CPU. However, the priority order is 0, 1, 2, and 3, with 0 being the highest and 3 being the lowest.

The operation will be explained with reference to FIG. 1 and FIG. 2. First, a desired priority order is written in each priority order designation section using a program or the like. Now, the priority specification section 105-A has 0, the priority specification section 105-B has 1, and 10
Assume that 2 is written to 5-C and 3 is written to 105-D. When there is no interrupt request or when interrupts are prohibited, when the contents of the scanning signal 102 change in the order of 0, 1, 2, 3, a coincidence signal 1 is generated.
09-A, B, C, and D change as shown in period P in FIG. 2, respectively. Now, assume that an interrupt request is generated from the interrupt source 100-C at timing T1, and that the interrupt is enabled (not masked). When the scanning signal 102 is "2", a coincidence signal 109-C is generated. This interrupt is accepted and the interrupt signal 1 is sent to the CPU at timing T2.
03 is sent. At this time, the priority level "2" of the accepted interrupt is stored as data 114 in the control unit 101. While the CPU is executing interrupt processing with priority "2", the scanning signal 102 changes in the range of "0" → "1" → "2" and cannot be equal to the data 114 (i.e. "2"). Then, “0” again
Return to (T3). As a result, high priority “0”,
Only “1” interrupts can be accepted. Note that the scanning signal 102 also outputs “2”, but the control unit 101
is configured so that it cannot accept a duplicate interrupt that is currently being accepted.

Next, assume that a high-order interrupt request is generated from interrupt source B (T4). If interrupt B is enabled, a match signal 109-B is generated when the scanning signal 102 becomes "1". This interrupt is accepted with priority over the currently executing interrupt C, and the interrupt C is temporarily saved. Data 114 changes from "2" to "1" (T5). In this state, the scanning signal 102 changes in the range from "0" to "1", and when it becomes "1", it returns to "0" again (T6). That is, at this time, only interrupts with priority "0" can be accepted.

Multiple interrupt processing based on interrupt B is completed,
When the end signal 113 is sent from the CPU (T7),
Data 114 changes from "1" to "2". Along with this, the scanning signal 102 changes to "0", "1", and "2" as before, and interrupts with priorities "0" and "1" can be accepted.

When the interrupt processing of the interrupt source 100-C is completed and the signal 113 is sent from the CPU (T8),
The data 114 disappears and returns to the initial state in which all interrupts can be accepted.

Next, a specific circuit example of this embodiment will be explained based on the drawings.

Figure 3 shows 104-A, 105-A, 1 in Figure 1.
It is a circuit diagram of one block consisting of 06-A, 107-A, and 108-A. R・S-F/F301
-A and 302-A are set/reset type flip-flops that respectively store the upper and lower bits when the priority is expressed in 2 bits, and these flip-flops form a set of two in the priority order specifying section 105-.
Configure A. The priority value is determined by the CPU 300 through signals 310-A and 311-A.
is written using Therefore, the content is programmable. Signals 102-1 and 102-2 are the upper bit and lower bit when the scanning signal 102 is 2 bits.

The EX-OR gates 305-A and 306-A respectively output the upper priority bit 301-A and the upper bit 102-1 of the scanning signal, and the lower priority bit 302-A and the lower bit 102-2 of the scanning signal.
are compared independently, and if they match, the logical value is “0”
Output.

Therefore, when the priority and the scanning signal 102 are equal, the match signal 109 is output from the NOR gate 307-A.
-A (logical value 1) is output. With these two EX-OR gates and one NOR gate, the detection unit 104-A
It consists of 303-A is an interrupt mask register, which corresponds to the interrupt request control unit 106-A;
When an interrupt is to be masked, the R.S-F/F is set using the signal 312-A, and when not to be masked, it is reset. 304-A is an interrupt request flag and is the interrupt request signal 3 transferred from the interrupt source.
13-A, and is set when sent, and when no interrupt request is generated or
It is reset when the output of AND gate 308-A is "1". This interrupt request flag 304-A
corresponds to the interrupt request storage section 107-A. 10
8-A is an AND gate, and the match signal 109-A has a logical value of 1 and the mask register (R・S-F/F
303-A) is in a reset state and the interrupt request flag is set, it outputs an interrupt acceptance signal 110-A. This AND gate is the interrupt reception section 108-A. Vector generation section 30
9-A is the interrupt confirmation signal 314 from the CPU 300
When the interrupt is sent, the vector address 313-A of the accepted interrupt is output to the CPU 300. The interrupt request flag 304-A is the interrupt acceptance signal 110-
It is reset when A is a logic 1 and the interrupt acknowledge signal 314 is a logic 1.

FIG. 4 is a specific circuit diagram of the control section 101. Signals 102-1 and 102-2 are each T-
These are the outputs of F/F 401 and TF/F 402. Signal 102-2 is inverted on the falling edge of clock signal 403, and signal 102-1 is inverted on the falling edge of clock signal 403.
-2 falling edge inverts. That is, T-
F/Fs 401 and 402 are clock signals 403
It constitutes a quaternary counter that counts . Signals 102-1 and 102-2 are each scanning signal 1
Represents the upper bits and lower bits of 02. T-
The quaternary counter constituted by F/Fs 401 and 402 is reset when the output of NOR gate 404 becomes a logical value 1. Interrupt acceptance signal 110-
When any one of A, B, C, and D is output, the output of the priority setting section 111 becomes a logical value 1.

Now, R-S F/F407,409,411,
413 are reset, the output of the OR gate 418 is always a logic 0, so the interrupt signal 103, which is the output of the AND gate 402, is a logic 1. At this time, when the signals 102-1 and 102-2 are both logic 0 and the interrupt signal 103 is logic 1, the AND gate 406
Since the output of is logic 1, R・S-F/F407
is set. Similarly, the signal 102-1 is logic 0, the signal 102-2 is logic 1, and the interrupt signal 103
When is logic 1, the output of AND gate 408 becomes logic 1, so R.S-F/F 409 is set. Signal 102-1 is logic 1, signal 102-
When 2 is logic 0 and interrupt signal 103 is logic 1,
Since the output of AND gate 410 becomes logic 1, R.S-F/F 411 is set. signal 10
Both 2-1 and 102-2 are logic 1 and interrupt signal 10
When 3 is logic 1, the output of AND gate 412 becomes logic 1, so R.S-F/F 413 is set.

When an interrupt is accepted and the interrupt signal 103 becomes logic 1, the R・S-F/F 407, 409, 411, 413 corresponding to the priority of the interrupt
One of them is set. R・S-F/F4
07, 409, 411, and 413 indicate that interrupts with priority levels "0", "1", "2", and "3" were accepted, respectively. In response to the interrupt signal 103, the AND gate 424 prohibits the supply of the clock 425 to the TF/F 401. AND gates 414, 415, 416, 417 and OR gate 418 operate T-F/F4 when the priority of the interrupt being accepted becomes equal to the scanning signal 102.
Outputs a signal to reset 01 and 402.
However, during the period when the interrupt signal 103 is logic 1, the AND
Gate 423 prohibits reset. R・
S-F/F407 is reset and R・S-F/
When F409 is set, that is, when an interrupt of priority "1" is being processed, the signal 102-
When 1 becomes logic 0 and 102-2 becomes logic 1, when the interrupt signal 103 becomes logic 0, T-F/F4
01 and 402 are reset and the signals 102-2,
102-2 both become logic 0. At this time, even if another interrupt with priority "1" occurs again, R・S−
If F/F409 is set, AND gate 4
Since the output of 02 is logical 0, the accepted interrupt cannot be accepted twice.

Next, R・ indicates the priority of the interrupt currently being accepted.
The reset operation of SF/Fs 407, 409, 411, and 413 will be explained. Interrupt end signal 1
When R.13 goes to logic 1, R.S-F/F 407 is reset if R.S-F/F 407 is set. When the R.S-F/F 407 is reset, the output of the AND gate 419 becomes logic 1, so that the R.S.F/F 409 is reset. When both R・S-F/F 407 and 409 are reset, AND gate 42
Since the output of 0 becomes logic 1, R・S-F/F4
11 is reset. R・S-F/F407,
When 409 and 411 are all reset, the output of AND gate 421 becomes logic 1, so R.S-F/F 413 is reset. In this way, when the interrupt end signal 113 becomes logic 1,
R indicating the priority of accepted interrupts.
R, which indicates the highest rank among S-F/F.
It is reset in order from S-F/F. In this way, interrupts can be multi-processed according to their priorities.

The above is an example of assigning different priorities to each block. However, depending on the applied system, multiple blocks may be given the same rank. At this time, the priority setting section 1 shown below
11 is valid.

FIG. 5 is a circuit diagram of the priority setting section 111, and FIG. 6 is a timing diagram thereof. Now, interrupt sources 100-A, 100-C, 100-D
Priority order designation units 105-A, 105-C, 10
A case will be described in which the contents of 5-D are both set to "3" and interrupt sources 100-A, 100-C, and 100-D occur simultaneously. It is assumed that the content of the priority order designation unit 105 of the interrupt source 100-B is "1".

When the scanning signal 102 becomes “3”, the coincidence signal 10
9-A, 109-C, 109-D are all logic 1
(T1 timing in FIG. 6). At this time,
Interrupt request storage units 107-A, 107-C, 10
7-D stores the interrupt request and sets its output to logic 1.
, interrupts are enabled, and the interrupt control unit 106-
When the outputs of A, 106-C, and 106-D are logic 1, the interrupt receiving unit 10 of the interrupt source 100-A
Since the output of 8-A becomes logic 1, one input of OR gate 501 of priority setting section 111 becomes logic 1. At this time, the output of the interrupt accepting unit 108-B of the interrupt source 100-B is logic 0, assuming that there is no interrupt request. Therefore, the output of OR gate 501 is a logic one. Further, the outputs of the OR gates 502 and 503 both become logic 1 and generate an interrupt acceptance signal to the control section.
However, at this time, the output lines 112-C, 112-D
is logic 1, so the interrupt reception unit 108
Interrupt acceptance signal 110-C which is the output of -C and D
and 110-D are both logic 0. Therefore, in this case, only the interrupt acceptance signal 110-A of the interrupt source 100-A is accepted by the CPU, and the other interrupt request signals 110-C and 110-D are received when interrupts are enabled and no interrupt requests are made. I can't accept it even if it is. That is, the interrupt source 100-
Only the interrupt acceptance signal 110-A of A is input to the control unit, and the interrupt vector address 313-A is sent to the CPU in response to the interrupt confirmation signal 314, so that A's interrupt processing is executed. During this time, the contents of the interrupt request storage units 107-C and 107-D are suspended, and the interrupt acceptance signal 110-C becomes logic 1 every time the scanning signal 102 reaches priority level "3". Signal 110-D is OR gate 50
2), the fourth
As explained in the figure, interrupts with the same priority as the currently accepted priority "3" will not be accepted.
Interrupt signal 103 does not become a logic one. In the case of FIG. 5, interrupt source 100-A has the highest priority, followed by interrupt sources 100-B, 100-C, and 100-D.
The priority order is in the order of interrupt acceptance signals 110-A, B, C, D and OR gate 501,
By changing the connection relationship with 502 and 503, it is possible to set it to an arbitrary top priority.

As described above, when a plurality of interrupt requests with the same priority occur simultaneously, the priority setting unit 111 selects only a predetermined interrupt acceptance signal from among them, and selects the interrupt acceptance signal with the highest priority. It can be input to the control unit.

Furthermore, the circuitry for setting and changing the priority order in a predetermined order can be very small. Furthermore, the connection between the control unit and each interrupt source is a line passing through the scanning signal 102 and a line passing through the priority setting unit 111 (the outputs of OR gates 501, 502, 503 are connected in series). Therefore, there is only one line that connects the interrupt generation source) and a line that passes the interrupt confirmation signal 314 input from the CPU, and it can be configured with a small number of control lines. Therefore, the chip area of the microcomputer can be extremely small, making it possible to provide a low-cost interrupt control device.

As described above, according to the present invention, it is possible to set or change the acceptance priority order of interrupt requests to a desired order, and there is no need for complicated procedures even in multiple interrupt processing. Furthermore, even when a plurality of interrupt processes are set with the same priority, an interrupt control device capable of selecting one interrupt with a predetermined priority from among them can be realized at a low cost.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention, FIG. 2 is a timing chart of its operation, and FIG. 3 is a priority designation section, an interrupt acceptance control section, an interrupt request storage section, a detection section, and an interrupt acceptance section. FIG. 4 is a circuit diagram of the control section, FIG. 5 is a circuit diagram of the priority setting section, and FIG. 6 is an operation timing chart of FIG. 101...control unit, 104-A to D...detection unit, 105A to D...priority designation unit, 106
A to D...Interrupt request control unit, 107A to D
...Interrupt request storage unit, 108A to D...Interrupt acceptance unit, 111...Priority setting unit, 300
……CPU.

Claims (1)

[Claims] 1. In an interrupt control device that receives interrupt requests from multiple interrupt sources, there is an interrupt request storage section that stores interrupt requests for each interrupt source, and an interrupt request storage section that can be specified in any order, and the specified priority A priority designation section in which data indicating the priority is set, a scanning section that generates scanning signals in order from the highest priority, and a comparison between the scanning signal and the priority data of the priority designation section, and a check is made to determine whether the two match. a detection unit that outputs a match signal when a match signal is output, an interrupt request acceptance unit that accepts the interrupt request in the order in which the match signal is output, and when there are multiple accepted interrupt requests at the same time, one of the interrupt requests is forcibly executed. 1. An interrupt control device comprising: means for selecting an interrupt request and setting it as an interrupt request to be processed.