JPH0315236B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a traffic signal control device for ensuring the safety and smoothness of road traffic.

(Constitution of conventional example and its problems) FIG. 1 shows a method of offset synchronization control between a central unit and terminal signals in a conventional traffic signal control device. The configuration of this conventional example will be explained below based on FIG. 1. In Fig. 1, 1 indicates the operation timing of the cycle counter of the central device, which is the reference for the signal control cycle.
It is a decimal counter that counts 1% of the cycle as 1 count. 2, 3, and 4 indicate the operation timings of the terminal signal 1, 2 is a reference cycle counter, 3 is a follow-up cycle counter, and 4 is each timing for displaying the signal light color. Reference numerals 5, 6, and 7 indicate the operation timings of the terminal signal 2; 5 is a reference cycle counter, 6 is a follow-up cycle counter, and 7 is each timing for displaying the signal light color.

Next, the operation of the above conventional example will be explained. 1st
In the figure, by sending the second value of cycle counter 1 and the timing of count 0 from the central device to each terminal signal, reference cycle counters 2 and 5 of each terminal have the same cycle as cycle counter 1 in the center, I'm counting by timing. Furthermore, from the central device to each terminal signal,
Offset values 01, 02 and split values
By sending SA1, SB1, SA2, and SB2, in the terminal signal 1, the timing of count 0 of follow-up cycle counter 3 becomes the timing of count 10 of reference cycle counter 2 (01 = 10%
), the period length of the follow-up cycle counter 3 is expanded or contracted to perform the offset follow-up operation, and when the follow-up operation is completed, the cycle counter 1 of the central unit is offset from the reference point (count 0 point) as shown in Figure 1. The main line blue of the terminal signal 1 starts with a shift of 01, and the signal control is performed by allocating the time for the main line and crossing using preset values SA1 and SB1. Similarly, the main blue of the terminal signal 2 starts off offset 02 from the reference point, and the split value SA2
SB2 will be used to allocate time between trunk lines and intersections, and control signals.

However, in the above conventional example, it is necessary to synchronize the cycle counter of the central unit and the reference cycle counter of the terminal signal every time the signal control cycle changes. Therefore, the time required for data transmission and reception increases and the procedure becomes complicated. In particular, as is clear from Figure 1, in order to keep the cycle counter deviation between the center and each terminal within 1%, data is sent and received between the center and all terminals instantly at the time of every cycle change. This was a major problem in system configuration. In addition, if communication between the central terminal and a specific terminal is interrupted due to a failure, etc., if the cycle value changes even once, the offset synchronization between the central terminals will be lost, and the offset synchronization between the central terminals will be lost, and the offset synchronization between the central terminals will be lost. The drawback was that the control effect of the fail-safe constants (cycle, split, and offset values) was halved.

(Object of the Invention) The present invention eliminates the drawbacks of the above-mentioned conventional examples, reduces the time required for transmitting and receiving data for offset synchronization between a central device and a plurality of terminal signals, and simultaneously The purpose is to simplify the procedure and further improve the effectiveness of fail-safe control in the event that communication between the center and the terminals is interrupted.

(Structure of the Invention) In order to achieve the above object, the present invention includes an N-ary counter in the central unit that counts at millisecond intervals regardless of the signal control cycle, and individual control constants (cycle, split, etc.) for each terminal signal.
The control constant and the count value of the N-ary counter are sent to each terminal signal, and each terminal signal is preset with the received count value. An N-ary counter with the same interval and the same cycle length as the central device, a reference cycle counter whose count value becomes 0 at a specific count of the N-ary counter, with the received cycle value as the period length, and an offset received from the central device. By arranging a follow-up cycle counter whose count value is the time when the reference counter counts the value and whose period length is the received cycle value,
In offset synchronization of traffic signal control equipment, the time required to send and receive data between the center and the terminals can be reduced, the communication procedure can be simplified, and the effect of fail-safe control can be improved when communication between the center and the terminals is cut off. It will improve.

(Description of Embodiment) The configuration of an embodiment of the present invention will be described based on FIGS. 2 and 3.

In FIG. 3, 21 to 27 indicate each part in the configuration of the central device, and 31 to 41 indicate each part in the configuration of the terminal signal 1. Reference numeral 21 denotes an N-ary counter, which operates based on the m-second clock from the processing section 23 and can perform setting and reading from the processing section 23. 22 is a control constant storage unit that stores the contents of the constant setting unit 24 through the processing unit 23;
You can read from 3. 25, 26, 27 are transmitting/receiving units, which include terminal signals 1, 2...n and processing unit 2.
3, and transmits and receives signals according to commands from the processing section 23.

31 is a reference cycle counter, 32 is a follow-up cycle counter, and 33 is a terminal N-ary counter, which are each connected to the processing section 35 and can be set and read by the processing section 35, respectively. The terminal N-ary counter 33 further operates based on the m-second clock from the processing section 35. 36 is a fail-safe control constant storage section, 37 is a control constant storage section, 3
Reference numeral 4 denotes a transmitting/receiving unit, which is connected to the processing unit 35 and stores the control constants sent from the central device and the contents of the constant setting unit 38 through the processing unit 35, and also allows the processing unit 35 to read the stored contents. . Reference numeral 39 denotes a control unit which is connected to the processing unit 35, the main light device 40, and the cross light device 41, and is connected to the main light device 40 and the cross light device 41 based on the command from the processing portion 35.
0, the crossing light device 41 is controlled.

In FIG. 2, reference numeral 11 indicates the operation timing of the N-ary counter of the central unit, and the period of counting at one second intervals is, for example, one hour, regardless of the signal control cycle, and N=3.600. 12, 13, 14, and 15 indicate the operation timing of the terminal signal 1, and 12 is a terminal N-ary counter (12) that counts at the same interval (1 second) and same period length (1 hour) as the N-ary counter of the central device. N
= 3600), 13 is the decimal standard cycle counter,
Reference numeral 14 indicates a follow-up cycle counter in decimal notation, and 15 indicates each timing of display of the signal light color.

16, 17, 18, 19 indicate the operation timing of the terminal signal 2;
2, 13, 14, and 15, respectively.

Next, the operation of the above embodiment will be explained. Second
In the figure, N is sent from the central device to terminals 1 and 2.
The count value of the decimal counter 11, for example 12,1
6 is sent at each timing.

By presetting the terminal N-ary counters 12 and 16 with the received count value, they are synchronized with the central N-ary counter 11 and count the same number of seconds. Further, control constants such as a cycle value C, offset values 01 and 02, and split values SA1, SA2, SB1, and SB2 are sent to terminals 1 and 2 from the central device at regular time intervals. Each terminal uses the received cycle value (second value) to divide the current count value of the N-ary counters 12, 16, and the remainder (second value) is changed to a percentage value, and the reference cycle counter 13, 1
Preset 7. For example, if terminal 1 receives a cycle value of 120 (seconds), N-ary counter 12
If the current count value is 1212, perform the following calculation: (1) 1212 (seconds) ÷ 120 (seconds) = 10 remainder 12 (seconds) (2) 12 (seconds) ÷ 120 (seconds) x 100 = 10 % Therefore, the calculated percentage value 10 is preset in the reference cycle counter 13.

Further, in order to make the reference cycle counter 13 a decimal counter whose cycle length is the received cycle value 120 (seconds), it is counted at 1.2 second intervals, which is 1% of the cycle value.

By the above operation, the reference cycle counter 13
is set to the current count value assuming that the count value is 0 at the time when the current count value of the N-ary counter 12 is 0, and this periodic state continues.

By performing the above operation in terminal 2, the reference cycle counters 13 and 17 of each terminal count at the same timing (same count value),
Let the cycle value received from the central device be the cycle length.
It becomes a decimal counter.

That is, in the conventional example, data is sent to each terminal instantly from the central device at the time of a cycle change, so that each terminal's reference cycle counter (Fig. 1, 2,
5) at the same timing as the central cycle counter (Fig. 1), in this embodiment data transmission and reception between the center and the terminals is performed sequentially to each terminal approximately once an hour. Timing alignment is performed at each terminal signal, and each terminal's reference cycle counter (Figure 2
3 and 17) are counted at the same timing.

After the operation timing of the reference cycle counter of each terminal is obtained as described above, the operation is exactly the same as in the conventional example. That is,
Count of follow-up cycle counters 14 and 18 is 0
so that the timing of the reference cycle counter is 20 and 10 (01=20%, 02=
10%), the cycle length of each follow-up cycle counter is expanded or contracted to perform offset follow-up operation, and when the follow-up operation is completed, the reference cycle counter and follow-up cycle counter have the same cycle length as shown in Figure 2, and the reference cycle counter is The cycle counters are counted by offset values 01 and 02, respectively.

Each terminal signal has a following cycle counter 14,
18's count value 0 is the start of the main line blue, the cycle length is used as the signal control cycle, and the split value distributes the time between the main line and the crossing, as shown in the light color display timing of the reference cycle counters 15 and 19. control.

(Effects of the Invention) The present invention has the above-described configuration, and provides the following effects.

In this embodiment, in order to perform offset cycle control between the central device and each terminal signal, an N-ary counter that counts at intervals of seconds is used in the central device and each terminal device, and the mutual counts can be adjusted at any time. If a crystal oscillator is used as the oscillation source of the counter, the error is very small, so it is sufficient to perform communication at intervals of about once every few hours. The time required for this is therefore significantly reduced. Moreover, by sending the count values from the central device to each terminal individually, the count values can be easily matched between each other, and the procedure is simple, especially when the number of terminals is Even when the number of devices increases significantly to several hundred or more, there is an advantage that errors due to communication delays do not occur.

In addition, even if communication is temporarily cut off between the center and a specific terminal, by memorizing in advance the change point in the cycle value sent from the central device to each terminal signal, it is possible to use internal fail-safe constants. ,
This has the advantage that offset synchronization control equivalent to control from a central device can be maintained for a long period of time.

Furthermore, the fail-safe constant for each terminal signal,
If the cycle value change point and the terminal N-ary counter are set to a power outage compensation circuit method (backup due to battery), even if a communication cutoff and power outage occur at the same time at a specific terminal, the offset can be immediately tracked from the time the power is restored. This has the advantage of improving fail-safe control, such as by performing offset synchronization between adjacent terminal signals and allowing system control to continue.

[Brief explanation of the drawing]

FIG. 1 is a timing diagram showing the offset synchronization control method between the central unit and terminal devices of a conventional traffic signal control device, and FIG. 2 shows the offset synchronization control method of the traffic signal control device in an embodiment of the present invention. The timing diagram shown in FIG. 3 is a block diagram of the system of the present invention. 1... Operation timing of the cycle counter of the central device, 2... Reference cycle counter of the terminal signal 1, 3... Follow-up cycle counter of the terminal signal 1, 4... Each operation timing of the signal light color display of the terminal signal 1, 5 ...Reference cycle counter of the terminal signal 2, 6...Following cycle counter of the terminal signal 2, 7...Each operation timing of the signal light color display of the terminal signal 2, 11...Operating timing of the N-ary counter of the central device, 12 ...Terminal N-ary counter of terminal signal 1, 13...Reference cycle counter of terminal signal 1, 14...Following cycle counter of terminal signal 1, 15...Each operation timing of signal lamp color display of terminal signal 1, 16... ...Terminal N-ary counter of terminal signal 2, 17...Reference cycle counter of terminal signal 2, 18...Following cycle counter of terminal signal 2, 19...Each operation timing of signal light color display of terminal signal 2, 21... Central N-ary counter, 22... Control constant storage section, 23...
...Processing section, 24...Constant setting section, 25, 26, 2
7...Transmission/reception section, 31...Reference cycle counter, 32...Following cycle counter, 33...Terminal N-ary counter, 34...Transmission/reception section, 35...Processing section, 36...Fail-safe control constant storage section , 37...Control constant storage unit, 38...Constant setting unit, 39...Control unit, 40...Main lamp device, 41...
...crosslights.

Claims (1)

[Claims] 1. Consists of a central device and terminal signals 1, 2,...n, the central device includes an N-ary counter 21, a control constant storage section 22, a processing section 23, a constant setting section 24, and a transmitting/receiving section. It consists of sections 25, 26, and 27, and the processing section 23
are connected to all other parts, and the terminal signals 1, 2,...n are connected to a reference cycle counter 31, a follow-up cycle counter 32, a terminal N-ary counter 33, a transmitting/receiving section 34, and a processing section 3.
5, a fail-safe control constant storage section 36,
Consists of a control constant storage section 37, a constant setting section 38, a control section 39, a main light device 40, and a cross light device 41, and all other sections except the main light device 40 and the cross light device 41 are processed. The main light unit 40 and the cross light unit 41 are connected to the control unit 39, and the transmitting/receiving units 25, 26, 27 of the central device and the transmitting/receiving units of each terminal signal device 1, 2,...n The N-ary counter 21 of the central unit operates based on the m-second clock from the processing unit 23 to perform settings and reading from the processing unit 23, and the control constant storage unit 22 of the central unit. is constant setting section 2
The contents of 4 are set and stored through the processing unit 23 and read from the processing unit 23. Transmits and receives signals according to commands from the terminal signal, the reference cycle counter 31, the follow-up cycle counter 32, and the terminal N-ary counter 33.
are set and read by the transmitting/receiving section 34 and the processing section 35 of the terminal signal, respectively, based on the control constants sent from the central device. The fail-safe control constant storage section 36, the control constant storage section 37, and the transmitting/receiving section 34 operate at the same cycle interval as the N-ary counter of the device, and process the control constants sent from the central device and the contents of the constant setting section 38. The settings are stored through the section 35, and the stored contents are read by the processing section 35.
1 based on a command from a processing unit 35, and each terminal signal 1, 2, .