CN116157786A

CN116157786A - Synchronous data processing method and equipment

Info

Publication number: CN116157786A
Application number: CN202280006021.7A
Authority: CN
Inventors: 陈熙; 黄昌联; 房欢; 张宏韬; 张凯
Original assignee: Ecoflow Technology Ltd
Current assignee: Ecoflow Technology Ltd
Priority date: 2022-12-28
Filing date: 2022-12-28
Publication date: 2023-05-23

Abstract

A method of synchronous data processing, comprising: transmitting a preset synchronization frame to the plurality of slave devices, wherein the preset synchronization frame is used for indicating each slave device to enter an edge triggering mode; transmitting synchronization data to the plurality of slave devices, wherein the synchronization data is used for indicating each slave device to start data sampling when receiving the first edge of the synchronization data; receiving the transmission time sent by each slave device, wherein the transmission time is the total time recorded by the slave device in the edge trigger mode and used for receiving the synchronous data; calculating the relative time deviation among the plurality of slave devices according to the transmission time sent by each slave device; receiving sampling data returned by each slave device; and processing the sampling data according to the relative time deviation to obtain synchronous sampling data of the plurality of slave devices.

Description

Synchronous data processing method and equipment

Technical Field

The application belongs to the technical field of communication, and particularly relates to a synchronous data processing method and equipment.

Background

The statements herein merely provide background information related to the present application and may not necessarily constitute exemplary techniques.

The current communication bus has wide application scene, and the communication bus can be used for communication among various devices. In practical applications, in a communication bus including a master device control and a data sampling unit with a plurality of slave devices, the requirement of clock synchronism for sampling data of each slave device is high.

However, the master device and each slave device have respective clock systems, and there is a certain deviation between the respective clock systems, so that it is difficult for the master device to obtain data with high synchronism from the slave devices.

Disclosure of Invention

According to various embodiments of the present application, a synchronous data processing method, apparatus, and storage medium are provided.

In a first aspect, an embodiment of the present application provides a method for processing synchronous data, which is applied to a master device, where the master device is communicatively connected to a plurality of slave devices, and the method includes:

transmitting a preset synchronization frame to the plurality of slave devices, wherein the preset synchronization frame is used for indicating each slave device to enter an edge triggering mode;

transmitting synchronization data to the plurality of slave devices, wherein the synchronization data is used for indicating each slave device to start data sampling when receiving the first edge of the synchronization data;

Receiving the transmission time sent by each slave device, wherein the transmission time is the total time recorded by the slave device in the edge trigger mode and used for receiving the synchronous data;

calculating the relative time deviation among the plurality of slave devices according to the transmission time sent by each slave device;

receiving sampling data returned by each slave device;

and processing the sampling data according to the relative time deviation to obtain synchronous sampling data of the plurality of slave devices.

In a second aspect, an embodiment of the present application provides a method for processing synchronous data, which is applied to a slave device, where the slave device is communicatively connected to a master device, and the method includes:

changing a receiving mode to an edge triggering mode in response to a preset synchronous frame sent by the main equipment;

starting data sampling when the first edge of the synchronous data sent by the main equipment is received, and obtaining sampling data;

taking the total time of receiving the synchronous data in the edge trigger mode as transmission time, and sending the transmission time to the master device;

and sending the sampling data to the master equipment so that the master equipment calculates the relative time deviation among a plurality of slave equipment based on the transmission time sent by each slave equipment, and processing the sampling data according to the relative time deviation to obtain synchronous sampling data of the plurality of slave equipment.

In a third aspect, an embodiment of the present application provides a synchronous data processing method, which is applied in a communication system, where the communication system includes a master device and a plurality of slave devices, and the master device is communicatively connected to the plurality of slave devices, and the method includes:

the master device sends a preset synchronization frame to the plurality of slave devices;

the slave device responds to a preset synchronous frame sent by the master device, and changes a receiving mode into an edge triggering mode;

the master device sends synchronous data to the plurality of slave devices;

the slave device starts data sampling when receiving the first edge of the synchronous data to obtain sampling data;

the slave device takes the total time of receiving the synchronous data in the edge trigger mode as a transmission time;

the slave device sends the transmission time and the sampling data to the master device;

the master device receives the transmission time and the sampling data sent by the plurality of slave devices;

the master device calculates the relative time deviation among the plurality of slave devices according to the transmission time sent by each slave device;

and the master device processes the sampling data according to the relative time deviation to obtain synchronous sampling data of the plurality of slave devices.

In a fourth aspect, an embodiment of the present application provides a computer device, where the computer device includes a processor and a memory, where the processor is configured to implement the above-mentioned synchronous data processing method when executing a computer program stored in the memory.

In a fifth aspect, embodiments of the present application provide a computer readable storage medium having a computer program stored thereon, which when executed by a processor, implements the above-described synchronous data processing method.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the application will be apparent from the description and drawings, and from the claims.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.

Fig. 1 is an application environment diagram of a synchronous data processing method according to an embodiment of the present application.

Fig. 2 is a flowchart of a method for processing synchronous data according to an embodiment of the present application.

Fig. 3 is a schematic diagram of signal waveforms when synchronous data is transmitted on a bus according to an embodiment of the present application.

Fig. 4 is a flowchart of calculating a relative time offset according to an embodiment of the present application.

Fig. 5 is a flowchart of determining synchronous sampling data according to an embodiment of the present application.

Fig. 6 is a flowchart of a synchronous data processing method according to another embodiment of the present application.

Fig. 7 is a flowchart of a trigger condition of an edge trigger mode according to an embodiment of the present application.

Fig. 8 is a flowchart of calculating a transmission time according to an embodiment of the present application.

Fig. 9 is a flowchart for determining an end edge of synchronous data according to an embodiment of the present application.

Fig. 10 is a flowchart of determining a transmission time according to an embodiment of the present application.

Fig. 11 is a flowchart of a method for processing synchronous data according to still another embodiment of the present application.

Fig. 12 is a schematic structural diagram of a synchronous data processing device according to an embodiment of the present application.

Fig. 13 is a structure of a computer device according to an embodiment of the present application.

Detailed Description

In order that the above-recited objects, features and advantages of the present application will be more clearly understood, a more particular description of the application will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments may be combined with each other.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, and the described embodiments are merely some, rather than all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

The application scene of the communication bus is wide, and the communication bus can be used for communication among various devices. In practical applications, in a communication bus network topology employing a master device and a plurality of slave devices, the requirement for clock synchronization for sampling data from each slave device is high. However, the master device and each slave device have respective clock systems, and there is a certain deviation between the respective clock systems, so that it is difficult for the master device to obtain data with high synchronism from the slave devices.

The communication bus can be divided into a data bus, an address bus and a control bus according to the types of information transmitted among various devices, and the data bus, the address bus and the control bus are respectively used for transmitting data, data addresses and control signals.

Taking the communication bus as an RS485 bus as an example, an application environment diagram of the synchronous data processing method provided in the embodiment of the present application is described with reference to fig. 1. The master device and the plurality of slave devices are in communication connection through the RS485 bus, and the number of the slave devices is not particularly limited. The master device and each slave device use a single chip microcomputer as a control unit, and each single chip microcomputer is provided with a respective clock system, such as a crystal oscillator. When data is transmitted among various devices through the RS485 bus, the master device is difficult to obtain the data with high synchronism from the slave device due to certain deviation among various clock systems.

Based on the above-mentioned problems, the embodiments of the present application provide a synchronous data processing method, so that a master device can obtain data with high synchronism from each slave device.

The synchronous data processing method provided by the embodiment of the application can be executed by the computer equipment, and accordingly, the synchronous data processing device runs in the computer equipment. Fig. 2 is a flowchart of a synchronous data processing method according to an embodiment of the present application, where the synchronous data processing method is applied to a master device. As shown in FIG. 2, the synchronous data processing method may include the following steps S11-S16, the order of the steps in the flowchart may be changed according to different needs, and some may be omitted.

S11, sending a preset synchronous frame to a plurality of slave devices, wherein the preset synchronous frame is used for indicating each slave device to enter an edge triggering mode.

In at least one embodiment of the present application, the preset synchronization frame is a data frame with a custom configuration format. For example, the preset sync frame may include one or more bytes, each of which may include a start bit, a data bit, and a stop bit, and the specific number of bits of the start bit, the data bit, and the stop bit may be customized. In some embodiments, a check bit may also be included in the bytes of the preset sync frame. Taking the RS485 bus communication as an example, 1 byte may include 10 bits. The master device sends a preset synchronous frame to a plurality of slave devices at the same time point, and the slave devices change the receiving mode into an edge triggering mode after receiving the preset synchronous frame.

It will be appreciated that the slave device defaults to a serial receive mode before entering an edge triggered mode. Taking the RS485 bus as an example, in this embodiment, the serial port receiving mode refers to that after the RS485 bus receiving port of the slave device receives complete 1 byte data, the application program is notified to execute a corresponding operation. The edge triggering mode refers to triggering an interrupt when the level of data received from an RS485 bus receiving port of the device changes, executing an interrupt processing function, and performing corresponding operations, such as data sampling. The level change may be a change from a high level to a low level of the data or a change from a low level to a high level of the data.

It will be appreciated that in some embodiments, a plurality of slave devices are used for data sampling and a master device is used to obtain sampled data from between the individual slave devices. Taking an RS485 bus as an example, after the slave device performs data sampling, the sampled data is reported to the master device through the RS485 bus.

And S12, transmitting synchronous data to the plurality of slave devices, wherein the synchronous data are used for indicating each slave device to start data sampling when receiving the first edge of the synchronous data.

In at least one embodiment of the present application, the master device simultaneously transmits synchronization data to the plurality of slave devices within a preset time period, where the preset time period is a preset duration for transmitting synchronization data. The synchronization data refers to a preset number of bytes, the preset number being preset. For example, the preset time period is 2 milliseconds, and the preset number may be 1000, which indicates that the master device will transmit 1000 bytes of synchronization data in the future 2 milliseconds, and the slave device will prepare to receive 1000 bytes of synchronization data at any time in the future 2 milliseconds until the reception is completed. The preset time and the preset number can be set or adjusted according to the requirements in practical application.

As described above, each byte may include several bits, including, for example, a start bit, a data bit, and a stop bit, where the start bit and the stop bit may be 1 bit, and the data bit may be 8 bits. In some embodiments, a check bit may also be included, at which point the start bit and stop bit may be 1 bit, e.g., only the start bit or only the stop bit.

It will be appreciated that for synchronous data, the value of the bits per byte is different, so that each time the current bit is entered from the last bit, either a rising or falling edge occurs, the slave device can determine the number of bits received. A schematic diagram of edge variation of a slave device when receiving synchronization data according to an embodiment of the present application is described with reference to fig. 3. Illustratively, the slave device has its bus interface port at a default level, e.g., high, before it does not receive synchronization data. When the slave device receives the start bit of the 1 st byte of the synchronous data, the start bit is 0, the data changes in level, and the slave device changing from the high level to the low level can record a falling edge at P1, wherein the falling edge is also the first edge of the synchronous data. Then, the slave device receives the first data bit 1 of the 1 st byte of the synchronous data, the data changes the level again, the low level changes to the high level, the slave device can record the rising edge at the P2, and the like, which will not be described here. The slave device triggers an interrupt when receiving the first edge of the synchronous data, and executes an interrupt processing function. And then, starting data sampling from the equipment, and collecting data of each channel.

In the embodiment of the application, the master device sends the synchronous data to each slave device, and controls each slave device to start data sampling when receiving the first edge of the synchronous data. Because the edge triggering time is extremely short, each slave device can start sampling at the same time, and the synchronization of starting the sampling by each slave device is ensured to be high.

S13, receiving the transmission time sent by each slave device, wherein the transmission time is the total time recorded by the slave device in the edge trigger mode for receiving the synchronous data.

In at least one embodiment of the present application, each slave device has its own clock system. When each slave device receives the 1 st byte start bit of the synchronous data, the slave device starts to count according to the respective clock system, calculates the total time from the 1 st byte start bit to the last byte stop bit, and takes the total time as the transmission time of each slave device. In this embodiment, the last stop bit is not counted. Assuming that the number of bytes of the synchronization data is 1000, each byte includes 10 bits, the total time for receiving the synchronization data from the device record is the total time for receiving (10 x 1000-1) bits.

For example, taking 1000 bytes of synchronous data, 2 slaves (slave a and slave B, respectively), the slave a starts timing when receiving the 1 st byte of synchronous data, ends timing when receiving (10 x 1000-1) bits, and records the timing time as T _A The total time recorded by the slave device A for receiving the synchronous data is T _A . Similarly, slave device B starts timing when receiving the 1 st byte start bit of the synchronization data, ends timing when receiving (10 x 1000-1) bits, and records the timing time as T _B The total time recorded by the slave device B for receiving the synchronous data is T _B 。

S14, calculating the relative time deviation among the plurality of slave devices according to the transmission time sent by each slave device.

In at least one embodiment of the present application, since each slave device is provided with a clock system, there is a certain deviation between the clock systems, so each slave deviceThe standby clocks may also be biased by their respective clock systems. On the basis, each slave device samples data according to a stipulated sampling interval, and the sampling interval of each slave device is deviated, so that a certain deviation exists in the time of sampling the data. However, since the skew caused by the clock system is fixed, the skew also exists when the synchronous data is received. Still taking 1000 bytes of synchronization data, the number of slave devices is 2 (slave device a and slave device B, respectively), for example, the transmission time T recorded by slave device a _A With transmission time T recorded from device B _B Not the same, there is a time offset that is caused by the clock system of the individual slaves.

In an embodiment, the relative time deviation is calculated by taking one slave device of the plurality of slave devices as a reference device according to a preset relative time deviation calculation formula. The preset relative time deviation calculation formula may be preset. Illustratively, taking the example that the communication bus includes slave a and slave B, the relative time offset may refer to the time offset of slave a relative to slave B, or the time offset of slave B relative to slave a, which is not limited herein. Assume that the time offset of slave device B relative to slave device a is Δt _BA Then:

ΔT _BA ＝(T _B -T _A )/T _A 。

s15, receiving the sampling data returned by each slave device.

In at least one embodiment of the present application, the slave device may utilize a DMA (Direct Memory Access ) channel to control an ADC (Analog-to-Digital Converter) to sample data as it samples the data, resulting in sampled data. The mode of controlling the ADC to sample by using the DMA channel is not limited in this embodiment, and may be any existing technology, which is not described herein.

In an embodiment, each slave device performs data sampling at the same sampling interval as the start time of the data sampling at the time of triggering the interrupt and executing the interrupt processing function. It will be appreciated that since the time for edge triggering is extremely short, each slave device initiates sampling at approximately the same time. The sampling interval may be preset, for example, 1ms, which is not limited herein.

In one embodiment, after the master device sends the last byte in the synchronization data to the slave device, the synchronization process ends at this point. Each subsequent slave device transmits the sampled data to the master device.

It will be appreciated that after the synchronization data is sent, the slave device may continue to sample the data, for example, by sampling periodically for a predetermined period of time, or by continuing to sample at a predetermined sampling interval until the master device sends a stop sampling notification.

S16, processing the sampling data according to the relative time deviation to obtain synchronous sampling data of a plurality of slave devices.

In at least one embodiment of the present application, there is a certain time offset due to the clock system between the slaves. Therefore, there is also a deviation in the sampling interval between the slaves, and thus, when the slaves sample data at the same sampling interval at the same start time, the final sampled data is not synchronized. And correcting the sampling interval of the other slave devices by taking one slave device of the plurality of slave devices as a reference device, and correcting the sampling moment of each sampling data point in the sampling data relative to the starting moment according to the sampling interval to obtain the sampling data corrected by the other slave devices, wherein the sampling data of the slave devices are synchronous.

According to the synchronous data processing method provided by the embodiment of the application, the master device controls each slave device to enter an edge triggering state through a preset synchronous frame. And then, the master device sends the synchronous data to each slave device and controls each slave device to start data sampling when receiving the first edge of the synchronous data, and each slave device can start sampling at the nearly same time due to extremely short edge triggering time, so that the synchronism of the sampling start of each slave device is high. Subsequently, the master device receives the transmission time sent by each slave device, determines the relative time deviation among the slave devices according to the transmission time, and processes the sampled data of each slave device according to the relative time deviation, thereby obtaining the data with high synchronism.

The following describes, with reference to fig. 4, a flow of calculating a relative time offset provided in an embodiment of the present application, and in some embodiments, calculating a relative time offset between a plurality of slave devices according to a transmission time sent by each slave device, including:

s140, selecting a first slave device from the slave devices, and determining the transmission time of the first slave device.

In an embodiment, the first slave device is a reference device. The selection manner of the first slave device may be specified or random. For example, there is a slave a and a slave B, and the slave a may be designated as a first slave; or randomly selecting a slave device from the slave device A and the slave device B as a first slave device.

S141, determining other slave devices except the first slave device in the slave devices as second slave devices, and calculating the relative time deviation between the transmission time sent by each second slave device and the transmission time sent by the first slave device.

In an embodiment, the number of the second slave devices may be 1 or more, which is not limited herein. The relative time deviation can be calculated by a preset relative time deviation calculation formula. Still exemplified by the number of slaves being 2 (slave a and slave B, respectively), the transmission time of slave a is T _A For example, T _A 10085, slave B has a transmission time T _B For example, T _B 99754. Relative time offset Δt of transmission time sent from slave device B and slave device a _BA Is (T) _B -T _A )/T _A I.e., -1.1%. It will be appreciated that-1.1% means that slave B is 1.1% slower than slave a.

The following describes, with reference to fig. 5, a process for determining synchronous sampling data provided in an embodiment of the present application, where in some embodiments, processing the sampling data according to a relative time deviation to obtain synchronous sampling data of a plurality of slave devices includes:

s160, determining the starting time of data sampling and the first sampling interval.

In one embodiment, the start time and the sampling interval of the data sampling are preset, for example, the sampling interval is 1ms. The starting time of the data sampling of each slave device is the same, namely the corresponding time when the first edge of the synchronous data is received. It will be appreciated that the agreed sampling interval should be the same for each slave device, but the actual sampling interval for each slave device is biased due to the individual slave device clock bias. Here, the first sampling interval refers to a sampling interval of the first slave device, and when the first slave device is used as a reference device, the sampling interval is set to be accurate by default, and sampling interval deviations of other slave devices are corrected with the sampling interval of the first device as a reference.

S161, determining a second sampling interval of the second slave device according to the first sampling interval and the relative time deviation.

In an embodiment, as shown before, since there is a relative time deviation between the slaves, there is also a deviation in the actual sampling interval between the slaves, and a second sampling interval of the second slave is determined according to the first sampling interval and the relative time deviation, where the second sampling interval is a sampling interval corrected by the second slave based on the clock of the first slave. Illustratively, assuming that slave B is 1.1% slower than slave a's clock, the first sampling interval of slave a is 100 clock cycles, the second sampling interval of slave B is 99 clock cycles.

And S162, correcting the sampling time of each sampling data point in the sampling data of the second slave device relative to the starting time according to the second sampling interval to obtain corrected sampling data of the second slave device.

In one embodiment, each sampled data point has a corresponding sampling time, assuming that each slave device samples 1 time per 100 slave station clocks to obtain a data sample point. And correcting the sampling time of each sampling data point in the sampling data of the second slave device relative to the starting time according to the second sampling interval to obtain the sampling data corrected by the second slave device.

Illustratively, taking the number of slaves as 2 (slave a and slave B, respectively) as an example, a sampling interval of 100 clock cycles is set, each slave samples 1 time every 100 slave clock cycles. It will be appreciated that in the absence of a time offset from slave a to slave B, assuming that the 100 th sampled data point sampled by slave a corresponds to time a (relative to the starting time), then the 100 th sampled data point sampled by slave B should also correspond to time a, i.e., slave a and the 100 th sampled point of slave B correspond to the same time. However, if there is a time offset between the slave device a and the slave device B, there will be a deviation in the correspondence relationship. Assuming that slave a is the reference device, the time offset of slave B relative to slave a is 1%, i.e. slave B is 1% slower than the clock of slave a. At this time, the 100 th sampled data point of the slave device a, at this time a, actually corresponds to the 99 th sampled data point sampled by the slave device B. Therefore, the 99 th sampling data point of the slave device B corresponds to the 100 th sampling data point of the slave device a, and the sampling time of the 99 th sampling point of the slave device B is corrected to the time a, so that synchronous sampling data of the slave device a and the slave device B can be obtained.

S163, determining the sampling data of the first slave device as synchronous sampling data of the first slave device, and determining the corrected sampling data of the second slave device as synchronous sampling data of the second slave device.

It is understood that the first slave device is used as a reference device, and the sampling data of the first slave device can be used as synchronous sampling data without correction. And for the sampling data of other slave devices such as the second slave device, the sampling data obtained after correction according to the process can be obtained.

Fig. 6 is a flowchart of a synchronous data processing method according to an embodiment of the present application, where the synchronous data processing method is applied to a slave device. As shown in fig. 6, the synchronous data processing method may include steps S21 to S24, and the order of the steps in the flowchart may be changed according to different needs, and some may be omitted.

S21, responding to a preset synchronous frame sent by the main equipment, and changing the receiving mode into an edge triggering mode.

In at least one embodiment of the present application, the master device sends a preset synchronization frame to the plurality of slave devices at the same time point, and the slave devices change the receiving mode to the edge trigger mode after receiving the preset synchronization frame. The edge triggering mode refers to triggering an interrupt when the level of data received from an RS485 bus receiving port of the device changes, executing an interrupt processing function, and performing corresponding operations, such as data sampling. The level change may be a change from a high level to a low level of the data or a change from a low level to a high level of the data.

S22, starting data sampling when the first edge of the synchronous data sent by the main equipment is received, and obtaining sampling data.

In at least one embodiment of the present application, the slave device receives the first edge of the synchronization data (i.e., the start bit of the 1 st byte), the data changes in level, and when the slave device receives the data changes in level, the slave device triggers an interrupt and executes an interrupt processing function. And then, starting data sampling from the equipment, and collecting data of each channel.

In one embodiment, the slave device may use a DMA (Direct Memory Access ) channel to control the ADC (Analog-to-Digital Converter) to sample the data as it is being sampled, resulting in sampled data. The manner in which the ADC is controlled to sample by the DMA channel is in the prior art, and will not be described in detail herein.

In an embodiment, each slave device performs data sampling at the same sampling interval as the start time of the data sampling at the time of triggering the interrupt and executing the interrupt processing function. It will be appreciated that since the time for edge triggering is extremely short, each slave device initiates sampling at approximately the same time. The sampling interval is preset, for example, 1ms, and is not limited herein.

S23, taking the total time of receiving the synchronous data in the edge triggering mode as the transmission time, and sending the transmission time to the master device.

Illustratively, slave device A, upon receiving the 1 st byte of start bits of synchronization data, ends the timer upon receiving (10 x 1000-1) bits, records the timer time as T _A The total time recorded by the slave device A for receiving the synchronous data is T _A 。

And S24, sending the sampling data to the master equipment so that the master equipment calculates the relative time deviation among the plurality of slave equipment based on the transmission time sent by each slave equipment, and processing the sampling data according to the relative time deviation to obtain synchronous sampling data of the plurality of slave equipment.

In at least one embodiment of the present application, since each slave device is provided with a clock system, there is a certain deviation between the clock systems, so each slave device also has a deviation in timing according to the respective clock system. On the basis, each slave device samples data according to a stipulated sampling interval, and the sampling interval of each slave device is deviated, so that a certain deviation exists in the time of sampling the data. However, since the offset caused by the clock system is fixed, the clock system is not always in the same stateThis deviation also exists when synchronous data is received. Still taking 1000 bytes of synchronization data, the number of slave devices is 2 (slave device a and slave device B, respectively), for example, the transmission time T recorded by slave device a _A With transmission time T recorded from device B _B Not the same, there is a time offset that is caused by the clock system of the individual slaves.

In an embodiment, the master device uses one slave device of the plurality of slave devices as a reference device, and calculates the time deviation of the rest slave devices relative to the reference device according to a preset relative time deviation calculation formula. The preset relative time deviation calculation formula is preset. Since there is a relative time deviation between the slaves, there is also a deviation in the sampling interval between the slaves, which results in that the final sampled data is not synchronized when the slaves sample data at the same starting time and at the same sampling interval. And correcting the sampling interval of the other slave devices by taking one slave device of the plurality of slave devices as a reference device, and correcting the sampling moment of each sampling data point in the sampling data relative to the starting moment according to the sampling interval to obtain the sampling data corrected by the other slave devices, wherein the sampling data of the slave devices are synchronous.

Describing the triggering condition of the edge trigger mode provided in the embodiment of the present application with reference to fig. 7, after responding to the preset synchronization frame sent by the master device, the method further includes:

S210, determining check bits corresponding to the preset synchronous frames.

In one embodiment, the preset sync frame may include one or more bytes, each of which may include a start bit, a data bit, and a stop bit, and the specific number of bits of the start bit, the data bit, and the stop bit may be set in a customized manner. In some embodiments, the bytes in the preset sync frame may also include check bits.

S211, when the check bit meets the preset check requirement, determining that the check is correct and updating the receiving mode to be an edge triggering mode.

In an embodiment, before receiving the preset synchronization frame, each slave device is in a serial port receiving mode, that is, after receiving the complete data frame, the slave device responds to the data frame to perform a corresponding operation. The check bit is used for confirming that the current preset synchronous frame is received completely and correctly, and when the preset check bit meets the preset check requirement, the preset synchronous frame can be confirmed to be received completely. At this time, the slave device updates the reception mode to the edge trigger mode. When the check bit does not meet the preset check requirement, the receiving mode does not need to be updated to be an edge triggering mode.

The calculation flow of the transmission time provided in the embodiment of the present application is described with reference to fig. 8, and calculating the total time of receiving the synchronization data as the transmission time includes:

S230, determining the bit quantity corresponding to the synchronous data.

In an embodiment, the synchronization data refers to a preset number of bytes, and the preset number is preset, for example, the preset number may be 1000. Each byte may contain several bits, including, for example, a start bit, a data bit, and a stop bit, where the start bit and the stop bit may be 1 bit and the data bit may be 8 bits. The number of bits refers to the number of bits in the synchronous data, and when the synchronous data contains 1000 bytes and 1 byte contains 10 bits, the stop bit of the last 1 byte in the synchronous data is considered to be not counted, and the number of bits is 10×1000-1.

S231, determining the end edge of the synchronous data according to the first edge of the synchronous data and the bit quantity.

In an embodiment, the master device transmits the start bit of the 1 st byte in the synchronization data to each slave device as the first edge, and considers that the stop bit of the last 1 st byte in the synchronization data is not counted, and takes the 10 x 1000-1 th bit in the synchronization data as the end edge.

S232, determining the time interval between receiving the first edge and the end edge as the transmission time.

In one embodiment, taking 1000 bytes of synchronous data as an example, slave device A starts timing when receiving the start bit of 1 st byte of synchronous data, ends timing when receiving (10 x 1000-1) bits, and records the timing time as T _A From the slaveThe total time (i.e., transmission time) of the received synchronization data recorded by device a is T _A 。

The determining process of the end edge of the synchronous data according to the embodiment of the present application is described with reference to fig. 9, where determining the end edge of the synchronous data according to the first edge of the synchronous data and the number of bits includes:

s2310, when the first edge of the synchronization data is received, the start counter accumulates the number of received edges.

In one embodiment, the edges herein refer to either rising or falling edges. As previously described, the value of each bit in each byte of the synchronization data is different, i.e., the beginning of each bit in each byte of the synchronization data is either a rising edge or a falling edge. After receiving the pre-synchronization frame, the slave device enters an edge triggered mode. When the master device starts to send the synchronous data, the slave device can confirm that the rising edge or the falling edge is the first edge of the synchronous data when identifying the first rising edge or the falling edge, and starts the counter to start counting. It will be appreciated that the type of the first edge depends on the setting of the start bit and the stop bit, e.g. if the value of the start bit is set to 0 and the stop bit is set to 1, the first edge is a falling edge and vice versa a rising edge. The counter is used to record the number of edges in the synchronization data received from the device. When receiving the first edge (taking the first edge as a falling edge as an example) of the synchronous data, the slave device enters the edge for triggering for the 1 st time, and starts a counter to count from 0; when the slave receives the second edge (taking the second edge as a rising edge for example), the slave enters the edge trigger for the 2 nd time, the count is incremented by 1, and so on, the counter may count the number of edges received, i.e. the number of bits of the synchronization data received.

In one embodiment, the synchronization data is 1000 bytes, and 1 byte includes 10 bits, for example, 10×1000 bits. When 10 x 1000 edges are received from the device, the number of counters is 10 x 1000-1.

S2311, when the count of the counter is equal to the number of bits, it is determined that the current edge is the end edge of the synchronous data.

In one embodiment, when the synchronization data contains 1000 bytes and 1 byte contains 10 bits, the stop bit of the last 1 byte in the synchronization data is considered to be not counted, and the number of bits is 10×1000-1. When the count of the timer is also 10 x 1000-1, the current edge is determined to be the end edge of the synchronous data.

The determining process of the transmission time provided in the embodiment of the present application is described with reference to fig. 10, where determining that the time interval between receiving the first edge and the ending edge is the transmission time includes:

s2320, when the first edge of the synchronous data is received, a timer is started for timing.

In an embodiment, a timer is used to record the time at which an edge in the synchronization data is received from the device. When the first edge of the synchronous data is received (taking the first edge as a falling edge as an example), the slave device enters the edge trigger for the 1 st time, resets the timer to 0, and starts timing.

S2321, when the end edge of the synchronization data is received, the timer is stopped.

In one embodiment, when the synchronous data comprises 1000 bytes and 1 byte comprises 10 bits, considering that the stop bit of the last 1 byte in the synchronous data is not counted, when the end edge of 10 x 1000-1 is received, the control timer stops counting, and the time is recorded as T ₁ 。

S2322, a timing time of the timer is determined as a transmission time.

In one embodiment, the transmission time is T ₁ 。

Fig. 11 is a flowchart of a synchronous data processing method according to an embodiment of the present application, where the synchronous data processing method is applied to a communication system, and the communication system includes a master device and a plurality of slave devices, and the master device is communicatively connected to the plurality of slave devices. As shown in fig. 11, the synchronous data processing method may include steps S31 to S39, and the order of the steps in the flowchart may be changed according to different needs, and some may be omitted.

S31, the master device sends a preset synchronous frame to the plurality of slave devices.

S32, the slave device responds to the preset synchronous frame sent by the master device, and changes the receiving mode into an edge triggering mode.

S33, the master device sends synchronous data to the plurality of slave devices.

S34, the slave device starts to sample data when receiving the first edge of the synchronous data, and sampling data is obtained.

S35, the slave device takes the total time of receiving the synchronization data in the edge trigger mode as the transmission time.

S36, the slave device transmits the transmission time and the sampling data to the master device.

S37, the master device receives the transmission time and the sampling data sent by the plurality of slave devices.

S38, the master device calculates the relative time deviation among the plurality of slave devices according to the transmission time sent by each slave device.

And S39, the master device processes the sampling data according to the relative time deviation to obtain synchronous sampling data of a plurality of slave devices.

The steps S31-S39 correspond to the steps S11-S16 and the steps S21-S24, respectively, and the detailed implementation process is described in the foregoing embodiments, which are not repeated here.

It should be appreciated that in the above embodiments, one of the plurality of slave devices is referenced, and in other embodiments, the master device may be referenced. When the master device is used as a reference device, the relative time deviation between the duration of the preset time period and the transmission time sent by each slave device can be calculated according to the preset time period of the synchronous data sent by the master device, and the sampling data of each slave device are processed according to the relative time deviation between the master device and each slave device, so that synchronous sampling data of a plurality of slave devices are obtained.

Referring to fig. 12, fig. 12 is a schematic structural diagram of a synchronous data processing apparatus according to an embodiment of the present application. In some embodiments, the synchronous data processing device 20 may comprise a plurality of functional modules consisting of computer program segments. The computer program of the individual program segments in the synchronization data processing arrangement 20 can be stored in a memory of the computer device 30 and executed by at least one processor to perform the functions of the synchronization data processing (described in detail with reference to fig. 1).

In the present embodiment, the synchronous data processing apparatus 20 may be divided into a plurality of functional modules according to the functions it performs. When the synchronous data processing apparatus 20 is applied to a master device, the functional modules may include: a synchronous frame transmitting module 201, a synchronous data transmitting module 202, a transmission time receiving module 203, a time deviation calculating module 204, a sampling data receiving module 205, and a sampling data processing module 206. A module as referred to in this application refers to a series of computer program segments, stored in a memory, capable of being executed by at least one processor and of performing a fixed function. In the present embodiment, the functions of the respective modules will be described in detail in the following embodiments.

The sync frame transmitting module 201 is configured to transmit a preset sync frame to the plurality of slave devices, where the preset sync frame is used to instruct each slave device to enter an edge trigger mode.

The synchronization data sending module 202 is configured to send synchronization data to the plurality of slave devices, where the synchronization data is used to instruct each slave device to start sampling data when receiving a first edge of the synchronization data.

The transmission time receiving module 203 is configured to receive a transmission time sent by each slave device, where the transmission time is a total time recorded by the slave device in the edge trigger mode for receiving the synchronization data.

The time offset calculation module 204 is configured to calculate a relative time offset between the plurality of slave devices according to the transmission time sent by each slave device.

The sample data receiving module 205 is configured to receive sample data returned by each slave device.

The sample data processing module 206 is configured to process the sample data according to the relative time deviation to obtain synchronous sample data of the plurality of slave devices.

Referring to fig. 13, fig. 13 is a schematic structural diagram of a computer device 30 according to an embodiment of the present application. In the preferred embodiment of the present application, computer device 30 includes a memory 31, at least one processor 32, and at least one communication bus 33.

It will be appreciated by those skilled in the art that the configuration of the computer device shown in fig. 13 is not limiting of the embodiments of the present application, and that either a bus-type configuration or a star-type configuration may be used, and that the computer device 30 may include more or less other hardware or software than that shown, or a different arrangement of components.

In some embodiments, the computer device 30 is a device capable of automatically performing numerical calculations and/or information processing according to predetermined or stored instructions, the hardware of which includes, but is not limited to, microprocessors, application specific integrated circuits, programmable gate arrays, digital processors, embedded devices, and the like. The computer device 30 may also include a client device including, but not limited to, any electronic product capable of human-computer interaction with a client via a keyboard, mouse, remote control, touch pad, or voice-controlled device, such as a personal computer, tablet, smart phone, digital camera, etc.

It should be noted that the computer device 30 is only used as an example, and other electronic products that may be present in the present application or may be present in the future are also included in the scope of the present application and are incorporated herein by reference.

In some embodiments, the memory 31 has stored therein a computer program which, when executed by the at least one processor 32, performs all or part of the steps of a synchronous data processing method, for example. The Memory 31 includes Read-Only Memory (ROM), programmable Read-Only Memory (Programmable Read-Only Memory, PROM), erasable programmable Read-Only Memory (Erasable Programmable Read-Only Memory, EPROM), one-time programmable Read-Only Memory (OTPROM), electrically erasable rewritable Read-Only Memory (EEPROM), compact disc Read-Only Memory (Compact Disc Read-Only Memory, CD-ROM) or other optical disc Memory, magnetic tape Memory, or any other medium that can be used for a computer readable medium that carries or stores data.

Further, the computer-readable storage medium may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function, and the like; the storage data area may store data created according to the use of the computer device 30, or the like.

In some embodiments, at least one processor 32 is a Control Unit (Control Unit) of computer device 30, connects the various components of the entire computer device 30 using various interfaces and lines, and performs various functions of computer device 30 and processes data by running or executing programs or modules stored in memory 31, and invoking data stored in memory 31. For example, at least one processor 32, when executing computer programs stored in memory, implements all or part of the steps of the synchronous data processing methods in embodiments of the present application; or to implement all or part of the functionality of the synchronous data processing apparatus. The at least one processor 32 may be comprised of integrated circuits, such as a single packaged integrated circuit, or may be comprised of multiple integrated circuits packaged with the same or different functionality, including one or more central processing units (Central Processing unit, CPU), microprocessors, digital processing chips, graphics processors, a combination of various control chips, and the like.

In some embodiments, at least one communication bus 33 is provided to enable connected communication between the memory 31 and the at least one processor 32 or the like.

Although not shown, the computer device 30 may also include a power source (e.g., a battery) for powering the various components, preferably the power source is logically connected to the at least one processor 32 via a power management device that performs the functions of managing charge, discharge, and power consumption. The power supply may also include one or more of any of a direct current or alternating current power supply, recharging device, power failure detection circuit, power converter or inverter, power status indicator, etc. The computer device 30 may also include various sensors, bluetooth modules, wi-Fi modules, etc., which are not described in detail herein.

The integrated units implemented in the form of software functional modules described above may be stored in a computer readable storage medium. The software functional modules described above are stored in a storage medium and include instructions for causing a computer device (which may be a personal computer, a computer device, or a network device, etc.) or processor (processor) to perform portions of the methods of various embodiments of the present application.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of modules is merely a logical function division, and other manners of division may be implemented in practice.

The modules illustrated as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units can be realized in a form of hardware or a form of hardware and a form of software functional modules.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it will be obvious that the term "comprising" does not exclude other elements or that the singular does not exclude a plurality. Several of the elements or devices recited in the specification may be embodied by one and the same item of software or hardware. The terms first, second, etc. are used to denote a name, but not any particular order.

Finally, it should be noted that the above embodiments are merely for illustrating the technical solution of the present application and not for limiting, and although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present application may be modified or substituted without departing from the spirit and scope of the technical solution of the present application.

Claims

1. A method of synchronous data processing applied to a master device communicatively coupled to a plurality of slave devices, the method comprising:

transmitting a preset synchronization frame to the plurality of slave devices, the preset synchronization frame configured to instruct each of the slave devices to enter an edge-triggered mode;

transmitting synchronization data to the plurality of slave devices, the synchronization data configured to instruct each of the slave devices to begin data sampling upon receipt of a first edge of the synchronization data;

receiving sampling data returned by each slave device;

2. The method of claim 1, wherein said calculating the relative time offset between the plurality of slave devices based on the transmission time sent by each of the slave devices comprises:

selecting a first slave device from the slave devices, and determining the transmission time of the first slave device;

and determining other slave devices except the first slave device in the slave devices as second slave devices, and calculating the relative time deviation of the transmission time sent by each second slave device and the transmission time sent by the first slave device.

3. The method of claim 2, wherein said processing said sampled data based on said relative time offset to obtain synchronized sampled data for said plurality of slave devices comprises:

determining the starting time of data sampling and a first sampling interval;

determining a second sampling interval of the second slave device according to the first sampling interval and the relative time deviation;

correcting the sampling time of each sampling data point in the sampling data of the second slave device relative to the starting time according to the second sampling interval to obtain corrected sampling data of the second slave device;

The method includes determining sample data of the first slave device as synchronous sample data of the first slave device, and determining corrected sample data of the second slave device as synchronous sample data of the second slave device.

4. A method of synchronous data processing applied to a slave device, the slave device being communicatively coupled to a master device, the method comprising:

5. The method of claim 4, wherein after the responding to the preset synchronization frame sent by the master device, the method further comprises:

Determining a check bit corresponding to the preset synchronous frame;

and when the check bit meets a preset check requirement, determining that the check is correct and updating the receiving mode into the edge triggering mode.

6. The method of claim 4, wherein the calculating the total time to receive the synchronization data as the transmission time comprises:

determining the bit quantity corresponding to the synchronous data;

determining an end edge of the synchronous data according to the first edge of the synchronous data and the bit quantity;

the time interval between receipt of the first edge and the end edge is determined to be a transmission time.

7. The method of claim 6, wherein the determining the ending edge of the synchronization data based on the first edge of the synchronization data and the number of bits comprises:

starting a counter to accumulate the number of the received edges when the first edge of the synchronous data is received;

and when the count of the counter is equal to the bit number, determining that the current edge is the end edge of the synchronous data.

8. The method of claim 7, wherein the determining that the time interval between receipt of the first edge and the ending edge is a transmission time comprises:

When the first edge of the synchronous data is received, starting a timer to count time;

stopping timing when receiving the end edge of the synchronous data;

and determining the timing time of the timer as the transmission time.

9. A method of synchronous data processing applied in a communication system comprising a master device and a plurality of slave devices, the master device being communicatively coupled to a plurality of the slave devices, the method comprising:

the master device sends synchronous data to the plurality of slave devices;

10. A computer device comprising a processor and a memory, wherein the processor is configured to implement the method of synchronous data processing according to any one of claims 1 to 3 or the method of synchronous data processing according to any one of claims 4 to 8 when executing a computer program stored in the memory.