JPH03110871U - - Google Patents
Info
- Publication number
- JPH03110871U JPH03110871U JP1988990U JP1988990U JPH03110871U JP H03110871 U JPH03110871 U JP H03110871U JP 1988990 U JP1988990 U JP 1988990U JP 1988990 U JP1988990 U JP 1988990U JP H03110871 U JPH03110871 U JP H03110871U
- Authority
- JP
- Japan
- Prior art keywords
- layer conductor
- insulating substrate
- conductor patterns
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims 5
- 239000000758 substrate Substances 0.000 claims 3
- 239000000853 adhesive Substances 0.000 claims 2
- 230000001070 adhesive effect Effects 0.000 claims 2
Description
第１図はこの考案の実施例の一部を示す側面図
、第２図は従来の混成集積回路示す分解斜視図、
第３図は第２図に示す従来回路で生じる電極間短
絡を示す側面図、第４図は第３図の問題を解決し
た従来の混成集積回路を示す側面図である。
FIG. 1 is a side view showing a part of an embodiment of this invention, FIG. 2 is an exploded perspective view showing a conventional hybrid integrated circuit,
FIG. 3 is a side view showing a short circuit between electrodes that occurs in the conventional circuit shown in FIG. 2, and FIG. 4 is a side view showing a conventional hybrid integrated circuit that solves the problem shown in FIG.
Claims (1)
れた混成集積回路において、 上記絶縁基板上に第１、第２の第１層導体パタ
ーンが形成され、 これら第１、第２の第１層導体パターンの一部
上にそれぞれ第１、第２絶縁層が形成され、 これら第１、第２絶縁層上に、それぞれ上記第
１、第２の第１層導体パターンと接続された第１
、第２の第２層導体パターンが形成され、 これら第１、第２の第２層導体パターン上に、
上記導電性接着剤で上記チツプ部品の第１、第２
電極がそれぞれ接着されて、そのチツプ部品が上
記絶縁基板に実装されていることを特徴とする混
成集積回路。[Claims for Utility Model Registration] In a hybrid integrated circuit in which chip components are mounted on an insulating substrate with a conductive adhesive, first and second first-layer conductor patterns are formed on the insulating substrate, and , first and second insulating layers are formed on a portion of the second first-layer conductor pattern, respectively, and the first and second first-layer conductor patterns are formed on these first and second insulating layers, respectively. the first connected to
, a second second layer conductor pattern is formed, and on these first and second second layer conductor patterns,
The first and second parts of the chip parts are coated with the conductive adhesive.
A hybrid integrated circuit characterized in that electrodes are bonded to each other and chip components thereof are mounted on the insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988990U JPH03110871U (en) | 1990-02-28 | 1990-02-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988990U JPH03110871U (en) | 1990-02-28 | 1990-02-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03110871U true JPH03110871U (en) | 1991-11-13 |
Family
ID=31522993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988990U Pending JPH03110871U (en) | 1990-02-28 | 1990-02-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03110871U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013106054A (en) * | 2011-11-10 | 2013-05-30 | Daishinku Corp | Piezoelectric device |
-
1990
- 1990-02-28 JP JP1988990U patent/JPH03110871U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013106054A (en) * | 2011-11-10 | 2013-05-30 | Daishinku Corp | Piezoelectric device |