JPH0260193B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention enables automatic switching of the number of scanning lines between 400 lines and 200 lines in a CRT display device used for displaying electronic devices such as personal computers. related to things.

<Prior art> In recent years, the graphic functions of computers such as personal computers have been improved to enable display of kanji characters, and many of these are 320 x 200 dots, 640 x 200 dots, or 640 x 200 dots.
The output is 640 x 400 dots.

CRT display devices that are compatible with this graphic display are 320 x 200 dots and 640 x 200 dots, and the number of scanning lines is less than the 230 scanning lines of commercially available television receivers. When used as a device, there are few improvements to be made, and especially for home use, it is often used also as a television receiver.

On the other hand, in a CRT display device that displays 640×400 dots, the number of scanning lines increases, so in principle it is necessary to lower the vertical deflection frequency. In practice, the vertical deflection frequency cannot be lowered too much to prevent cathode ray tube flickering, for example 50-55 for 60Hz for 200 lines.
It can only be lowered to about Hz. Therefore, it is necessary to increase the horizontal deflection frequency, which can be increased to 22.73KHz compared to 15.75KHz for 200 lines. Therefore,
CRT display devices are often specialized because their vertical and horizontal deflection frequencies are significantly different from those of regular television receivers.

Therefore, such a 400-line receiver has little demand, especially for home use, and tends to be expensive.

<Purpose> The present invention is intended to eliminate the above-mentioned drawbacks, and the number of scanning lines can be freely switched between 200 lines and 400 lines, and it can be used in common with a television receiver.
It provides a CRT display device.

<Embodiment> An embodiment of the present invention will be described below with reference to the drawings. FIG. The output horizontal synchronization signal H and vertical synchronization signal V are input to the 400 line discrimination circuit 2, which counts the number of pulses of the horizontal synchronization signal and determines whether it is 400 lines or not depending on the timing of resetting it with the vertical synchronization signal. For example, an output signal C is sent out, and a control voltage at a predetermined level is sent out by the DC conversion circuit 3, which is made up of an integrating circuit. As a result, the deflection coil impedance switching circuit 4 is activated by switching the transformer tap, and the horizontal output line adjustment circuit 5 is activated by switching the resonance capacitance.
By operating the horizontal position correction circuit 6 by switching the phase of the AFC pulse, by operating the vertical amplitude switching circuit 7 by switching the time constant, and by operating the vertical synchronization switching circuit 8 by switching the synchronization volume constant, 400 lines from 200 line mode can be operated. The number of scanning lines is changed depending on the mode.

FIG. 2 explains in detail the 400 line discriminating circuit of the present invention. 9 is an RGB3 independent input type connector that receives video output from a personal computer; a horizontal synchronizing signal is input from this pin, and a vertical synchronizing signal is input from this pin. This vertical synchronization signal is input to pin No. 10 of the second integrated circuit 10, which has a NAND circuit configured inside, and is logically operated by the computer mode signal of pin No. 1 and NAND circuit a, and the output is sent from pin No. 2 by the inversion of the vertical synchronization signal. This signal is supplied to pin No. 1 of the first integrated circuit 11. This first integrated circuit 11 is a counter circuit that applies the horizontal synchronizing signal to a pin number and counts it as a clock pulse, and treats the vertical synchronizing signal of the pin number as a reset signal for this counter circuit. The control outputs of this counter circuit are Q ₉ and Q ₈ as
These two control outputs are output from the second terminal.
It is connected to the number pin of the integrated circuit 10,
After the arithmetic operation is performed by the NAND circuit B, the output is added to the No. pin again and inverted by the NAND circuit C with the power line No. pin, and this output is output as the control output C from the No. pin through the buffer circuit 12. It is something that

The operation of the above circuit will be explained according to the waveform diagram in Fig. 3.The counter circuit in the first integrated circuit 11 counts the number of pulses in the horizontal synchronizing signal H, and the output ^Q8 outputs 128 pulses as shown in the figure. A control signal that is inverted in increments of 256 times is output, and similarly, a control signal that is inverted in increments of 256 times is output from ^Q9 . These two count outputs are Q ⁸ × Q ⁹ which are the outputs of NAND circuits B and C of the second integrated circuit 10, because the reset pulse by the vertical synchronization signal for the 200th line resets the counter every 16.5 ms. The value is low, and the control output C becomes no signal. On the other hand, since the reset pulse due to vertical synchronization at the 400th line resets the counter every 17.7304ms, the value of Q ⁸ × Q ⁹ is high, and the 384th to 431st pulses are set to “H”.
The output signal C' is sent out as a signal.

Therefore, in the 400 line mode, the reset timing of the counter circuit is delayed and a control pulse is sent from its control output C', which is converted to a DC control voltage through the integrator circuit and used in the synchronous circuit related mode. It is automatically switched to correspond to 400 line mode.

<Effects> As described above, in the CRT display device of the present invention, the horizontal synchronizing signal is counted, and when this count is reset with the vertical synchronizing signal, the mode is switched to the mode with the number of scanning lines of 400 depending on the presence or absence of the control signal. Therefore, even if the CRT display device does not have a changeover switch, the changeover is automatically controlled by the video output of the personal computer, improving operability, and also because it can support the number of scanning lines of 200 lines and 400 lines. It also enables shared use with television receivers, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of a CRT display device of the present invention, FIG. 2 is a circuit diagram of the same CRT display device, and FIG. 3 is a waveform diagram in the same circuit diagram.

Claims (1)

[Claims] 1. In a CRT display device in which the number of scanning lines can be switched between 400 lines and 200 lines, there is a counting means for counting horizontal synchronizing signals, a means for forming control pulses based on the count output, and a means for forming control pulses using the count output, and a means for counting the horizontal synchronizing signals by using a vertical synchronizing signal. What is claimed is: 1. A CRT display device comprising: a discriminating circuit comprising means for resetting, and switching to a 400 line mode depending on the presence or absence of a control pulse at the time of resetting.