JPH0250677B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application) The present invention integrates or measures the direct current level of a video signal during a total number of burst cycles occurring in intermediate time intervals of the burst period, and in accordance with the measured direct current level. The present invention relates to a technique for adjusting the DC level of a video signal.

BACKGROUND OF THE INVENTION In color video signals, the number of burst cycles included in the back porch of the horizontal blanking interval varies from source to source of the video signal. Furthermore, color bursts typically
It has an envelope in which the amplitude gradually increases to a maximum for several cycles at the beginning of the burst interval, and the amplitude gradually decays over several cycles at the end of the burst interval. Furthermore, in many cases the burst interval does not consist of a complete number of burst cycles;
That is, it consists of a full number plus alpha burst cycles. As a result of these, in terms of burst interval characteristics, the burst interval of the video signal is
If this is not excluded from the measured value of the DC level of the back porch in the horizontal blanking interval, the measured value will be an error in such a level, which will be unpredictable and will contain a DC component. Prior art video signal DC restoration circuits have attempted to filter or otherwise eliminate the effects of burst components from the back porch DC level test value of the horizontal blanking interval.

(Means for Achieving the Disadvantages of the Prior Art, Effects of the Invention) The present invention relates to an apparatus for providing DC restoration of an analog video signal, and in order to provide such DC restoration, an error signal is generated for an amplifier through which the video signal passes. , this error signal is created by evaluating the DC level of the composite video signal in the presence of chrominance subcarrier burst components that occur during horizontal blanking intervals. The DC level of the signal is measured by using an integration technique, where the integration is performed over a precise total number of cycles of the subcarrier. This eliminates the need in the prior art to low-pass filter the video signal to remove bursts before clamping is performed.

It is an object of the invention to provide a device for restoring the DC level of a composite video signal having bursts of cycles of chrominance subcarriers.

Another object of the present invention is to measure the cycles of the chrominance subcarrier using an integration technique such that the integration occurs over the exact number of cycles of the subcarrier so that the average value of the burst being measured is accurately determined. An object of the present invention is to provide a device for restoring the DC level of a composite video signal having bursts of .

(Description of Examples) The details of the present invention will be described below based on Examples.

The illustrated embodiment of the invention can be used, for example, in conjunction with a digital videotape recorder.

The composite color video information that must be provided to such digital videotape recorders is typically
It undergoes many processing steps. This processing step includes DC restoration of the video signal to reestablish the standard direct current (DC) reference level of the video signal prior to providing the signal to the device of use. Normally, this DC restoration process is performed at the input stage of the device.

FIG. 1 shows a block diagram including the DC level restoration device of the present invention. The video signal is applied via line 200 to video amplifier 201, which amplifies the signal and restores its DC component by clamp circuit 202. Clamp circuit 202 samples the output of the amplifier on line 203 and generates a DC component on line 204 which connects to amplifier 201. The recovered DC video signal on line 203 then enters a low pass filter 205 whose output is provided on line 206 which connects to a video gain control amplifier 207. Amplifier 207 is another video amplifier 2
08, to which a second clamp circuit 209 brings the blanking level of that signal to ground level by application of a DC control signal via line 210 to the video amplifier 208. The output of this video amplifier appears on line 211, which connects to one of lines 218 extending from there to the sampling input of clamp circuit 209. Line 211 also connects to gated sync clip circuit 212 and precision H sync separator 213. The level of the sync tip present at sync tip detector 214 is detected and the corresponding signal level is provided on line 215. Line 215 extends to comparator 216 and sync separator 213. A video gain control signal on line 217 is applied to comparator 216 to control gain control amplifier 207 as needed. Output of detector 214 (which may include alternating current ripple)
is applied to one input of a precision H sync separator 213, and the video amplifier 2 is applied to the other input of this separator.
Connect to one of the lines 218 coming from the output of 08. These two inputs of separator 213 contain the AC ripple, if any, in the signal, and therefore they indicate that this separator has a synchronization circuit 221 and a horizontal synchronization phase detector 222 on line 220. A common mode condition is created to create a precisely isolated synchronization signal with no AC ripple applied to the input and output terminals. Another line 218 from the output of the video amplifier 208 extends to a coarse sync separator 219 which generates a coarse separated sync signal which is applied to a gate pulse generator 223 which line 2 whose output extends to clamp circuits 202 and 209 and synchronous chip detector 214.
Occurs on the 24th. When the horizontal sync signal is detected and isolated, pulse generator 223 provides a gate signal that causes both clamp circuits and the sync chip detector to close at the appropriate time during horizontal blanking.

Clamp circuit 209 is temporarily closed for an integer number of cycles during the burst period, rather than for an arbitrary amount of time, so that the blanking level of the video signal can be accurately obtained using integration techniques as described below.
The burst is added to line 225 and line 22
5 is a burst limiter circuit 22 connected to an amplifier 227 providing a complementary output of the limited burst input;
Added to 6. The output of limiter circuit 226 is also connected to burst detection circuit 228 which has one output on line 229 which connects to precision gate generator 230 and one output on line 260 which connects to phase detector 231. When the presence of a burst is detected, gate generator 230 generates a precision burst gate signal that enables amplifier 227 to pass through the middle three cycles of the burst and phase them out. so that it can enter the detector 231. This detector 2
31 accordingly provides a signal to voltage controlled oscillator 232 representing the phase difference between the output of oscillator 232 and the phase of the burst cycle from amplifier 227.
The effect of this phase detection circuit controlling oscillator 232 is to correct for relatively long-term rather than short-term changes in the phase of the three cycles of the burst used line by line as a subcarrier reference. The output of oscillator 232 appears on line 233 after being processed by buffer 234. The output of this oscillator is a continuously regenerated subcarrier signal phase-locked to the color burst during the burst.
SC (3.58MHz). However, if the burst detection circuit 228 does not detect a burst, the phase detector 231 detects the phase of the H/2 signal and the oscillator 2.
This H/2 signal is compared with the regenerated subcarrier output of 32, and this H/2 signal is
2 is generated by a synchronous generator 235 from an oscillator 236 controlled by a synchronous generator 235. This continuously regenerated subcarrier signal SC is used, for example, to digitize the video signal in the digital video tape recorder mentioned above.

The horizontal phase position control device 237 is used, for example, for adjusting the horizontal position of regeneration synchronization. The 8-bit binary number is output from oscillator 236.
A latch circuit 238 is entered by a manual rotary switch or the like to preset a counter 239 which is clocked by the 400H clock signal. When the counter reaches its limit count, it outputs 24 which connects to the second input of H synchronous phase detector 222.
Trigger the ramp generator 240 with a 1.
Thus, by adjusting latch circuit 238, up to ±20 microseconds can be inserted into the feedback loop on line 241, and the phase of the regenerated synchronization signal can be adjusted for horizontal positioning of the video image represented by the video information signal. It can be adjusted. Since the delay in this feedback loop means that the regenerated synchronization is advanced, controlling the horizontal position effectively changes the video information signal to compensate for propagation delays during the transmission of the signal by wiring within the television station. You can proceed to

The output of oscillator 236 is also used by sync generator 235, which is conventional for television signal processing equipment, to generate signals related to the various vertical and horizontal sync rates shown in FIG. It will be done. These synchronized velocity related signals are generated with respect to the phase of the precision regenerated H synchronization as provided by phase detector 222, and therefore always have a phase relative to the input signal.

An important aspect of the circuit of FIG. 1 is that the H sync signal of the video signal is clipped at exactly 1/2 of its value and that the blanking level is clamped exactly to ground. Since the clamp circuit 209 tests the zero average level of the video at the burst time using a clamp pulse that lasts exactly the full number of cycles of the burst, there is no need to low-pass filter this video or eliminate the burst before clamping. do not have. This is because the resulting integral of the burst is 0, and the H/2
Due to the fact that there is no ripple.

Details of the block diagram of FIG. 1 are shown in FIGS. 2A-2D.

For the operation of clamp circuit 209 (FIG. 2C), the output voltage of amplifier 208 is connected to lines 211 and 2.
18 and line 218 connects to the base of emitter follower transistor 244, which creates a voltage drop. Under balanced conditions, the blanking level of the video signal on line 218 is at ground potential.
This video signal is shifted to the negative side by approximately 0.7V due to the voltage drop across the emitter follower 244. Matching emitter follower transistor 245, whose emitter is connected by line 247 to the negative input of differential amplifier 246, shifts to the negative side, as does comparison level (ground potential) transistor 244. The emitter of transistor 244 is connected to the positive input of differential amplifier 246 when transmission gate or switch 248 is closed for a full number of cycles of the burst by the signal on line 224 generated by relimit gate pulse generator 223 of FIG. 2D. Connecting.
Thus, during a burst, switch 248 closes and charges capacitor 249 to the average level of the burst. This switch is closed during an integral number of subcarrier cycles. This eliminates the need for low-pass filtering of the video signal for burst removal before clamping, which is conventionally conventionally performed to eliminate H/2 modulation of the clamp level. The voltage on capacitor 249 is a true reflection of the average value of the burst, and differential amplifier 246
shows the error applied to video amplifier 208 through line 251, transistor 252, and line 210 which connects to the emitter of transistor 252. The blanking level of the signal on line 211 is thus the high DC voltage of differential amplifier 246.
The gain keeps it close to ground potential. The operation of clamp circuit 202 is substantially similar to that of clamp 209 and is shown in Figures 2A and 2B.

Referring to FIG. 2C, when switch 248 closes, a burst is sent to line 218 and transistor 244.
through this switch to capacitor 249
and is passed to a line 225 extending to FIG. When there is a burst, burst detection circuit 228 provides a limited burst signal on its output line 229, which clocks precision gate generator 230. A counter is used as the generator to count the limited burst signal and generate a precision burst gate during the middle three cycles of the 9-11 cycle burst interval connected to line 256 to enable amplifier 227. Therefore, except for the middle three cycles of a burst, the amplifier 227 is connected to the burst detection circuit 228.
The output becomes inoperable. In the event of a burst, diode detector 257 and subsequent latch circuit 258 of detector 228 drive line 260, which connects to switching transistor 259 (FIG. 2B) of phase detector 231, to a more negative level.
When there is a burst, switching transistor 2
59 is cut off and the other switching transistor 261 of the detector 231 becomes conductive. When transistor 261 is turned on, three cycles of the burst from amplifier 227 are applied by driver 277 to transformer 262 of detector 231 . This driver on the other hand has the phase of the burst and line 2
It is connected to a phase comparator 231a for comparing the output phase of the 3.58 MHz (SC) oscillator 232 located at 33. When a burst is not detected by detector 228, transistor 259 is turned on and driver 2 connects signal H/2 to transformer 262.
In addition to the other input of 77, and line 233
The upper oscillator output is compared to the phase of the H/2 signal.

Returning to the circuit for performing precision H synchronization separation, and referring to FIG.
64 from amplifier 208 on line 218 extending to 64.

The emitter of transistor 265 is connected to control line 2.
24 connects to a transmission gate or switch 266 that is closed for a certain period of the synchronization signal. The level of this signal is determined by charging a capacitor 267 (FIG. 2D) which is buffered by a unity gain amplifier 268 and is
Half the level is applied to one input of sync separator 213 via line 215 along with the full level of AC ripple present in this signal. The other input of this sync separator is connected to line 269 from emitter follower transistor 265. Figure 2A
In the embodiment illustrated in ~D, precision H sync separator 213 is a comparator. In this way, line 2
The output on 20 shows that the AC ripple is the comparator 2.
13 and is not present at the output of this comparator due to common mode rejection, resulting in a separate sync signal whose timing is independent of the AC ripple of the video signal.
The sync signal on line 220 is a precision sync signal used by other parts of the video signal-using device.

A coarse separated sync signal is also generated by taking the sync signal from low pass filter 264 to coarse sync separator 219 via line 270. The output of this separator appears on line 271 and synchronous detector 27
6 is applied to a gate pulse generator 223 containing a one-shot serving as 6. The upper circuit, indicated at 272, generates the gate signal used by switch 266 to close it in the presence of sync, and circuit 273 generates the back porch sample and circuit 274 requalifies the burst signal with respect to the SC phase. For emitter 223, if there is no synchronization and therefore it does not appear on line 271 from coarse synchronization detector 219, synchronization detector 27
6 is connected to the clamp circuit 209 through the circuit 274.
switch 248 in clamp circuit 202 and a similar switch 275 in clamp circuit 202 are closed so that all clamp circuits operate based on the DC feed pack loop rather than leaving them open. Thus, in the absence of a synchronization signal, the level on line 224 will be high until synchronization returns and is detected. Additionally, as a backup in the event that precision gate generator 230 does not receive the necessary number of burst cycles to clock to its limit state or count after its counting cycle has begun, detector 276 connects precision gate generator 230 through circuit 274. is connected to provide a burst gate signal to ensure the completion of its counting cycle and to ensure the provision of a precision burst gate signal. This allows the precision gate generator 230
always reliably responds correctly to all input burst signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment including a DC level restoring device according to the present invention, and FIGS. 2A-2D are detailed circuit diagrams of the block diagram of FIG. 1.

Claims (1)

Claims: 1. An apparatus for restoring the DC level of a composite video signal having a plurality of cycles of a color burst signal following a horizontal sync pulse within a horizontal blanking interval, comprising: (a) a correction signal provided; (Signal on line 210)
(b) an adjusting means 208 for adjusting the DC level of the video signal according to; (b) integrating the video signal and adjusting the DC level so as to determine an average value of the video signal;
The above correction signal is given to 8.
(c) an integrating means 249 which operates upon receiving a gate signal (the signal on line 224); A DC level restoring device comprising: gate signal applying means 219, 223 for applying the gate signal during a predetermined time period.