JPS6358667A - Slicing circuit for digital data - Google Patents

Abstract

PURPOSE:To automatically set the slicing level of the record signal itself by sampling/holding both positive and negative peak values of a data synchronizing signal to obtain the average voltage level of both held values and defining this average voltage level as a digital slicing level to perform the waveform shaping. CONSTITUTION:The video waveform signals received from an input terminal 1 are supplied to an amplifier 12 and a synchronizing separator 20 and these amplified signals are applied to peak value wave detecting circuits 13 and 14 to sample the positive and negative peaks of the data synchronizing signal. The sampled peak value is held by a sampling/holding circuit 15 and the average voltage level of the peak value is obtained by an average voltage circuit 16. Then the average voltage level is applied to a comparator 17 and the input video waveform signal undergoes the waveform shaping to deliver the digital data with the average voltage level defined as a slicing level. The circuits 13-16 are controlled by the timing of monostable multivibrators 21-23 which process the horizontal synchronizing signals sent from the circuit 20. Then the data slicing level is set at 50-60% of an input signal.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) This invention utilizes a video tape recorder (hereinafter referred to as VTR) to record information on a magnetic tape using a pulse code modulation (hereinafter referred to as PCM) method. The present invention relates to a digital data slicing circuit used in a system for reproducing digital data.

(Prior Art) In recent years, a system has been developed that uses a VTR to record and reproduce audio signals using the PCM method. In this system, the format of the recording signal is such that PCM data is inserted into the picture-corresponding portion of the baseband waveform of the video signal, as shown in FIG. When data recorded in this format is reproduced, its waveform is distorted, so in order to accurately sample this data, it is important to slice it at the center of the so-called eye pattern.

By the way, when recording a PCM digital audio signal, immediately after the horizontal synchronization signal HD, as shown in Figure 4,
The data synchronization signal DSY is recorded, and after this the actual PC
M digital audio signals DAU are recorded. The data synchronization signal DSY is used as reference phase information for sampling the digital audio signal. Therefore, it is important to accurately detect the "O"1" pattern of the synchronizing signal DSY and determine the sampling lock phase in order to eliminate data errors.

Here, in order to identify the pattern or data of "02"1", it is necessary to slice the human input signal and shape the waveform in advance.

As a circuit for this purpose, a circuit shown in FIG. 5 has conventionally been used. That is, the input video waveform signal at the input terminal 1 is pedestally clamped by the pedestal clamp circuit 2 and supplied to one input terminal of the comparator 3. Further, the pedestal voltage Vo used in the pedestal clamp circuit 2 is combined with the adjustment voltage v1 in the level shift circuit 4 and supplied to the other input terminal of the comparator 3.

Therefore, as shown in FIG. 6, the data synchronization signal DSY and digital signal of the input video waveform signal are waveform-shaped with reference to the slice level (Vo+V1) and output from the comparator 3.

(Problems to be Solved by the Invention) The above-mentioned video waveform signal has a peak value that changes depending on the frequency characteristics of the VTR, and the waveform is dull. For this reason,
When setting the slice level of comparator 3, see Figure 6 (a
) As shown in (b), it is necessary to accurately set the adjustment voltage (1). FIG. 6(a) shows the relationship between the slice level and data when the data synchronization signal DSY of normal amplitude is input. In addition, the same figure (b) shows the data synchronization signal DS when it is shifted in DC direction and the amplitude becomes small.
It shows the relationship between the slice level and data when Y is input.

However, in the above circuit, the adjustment voltage v1 is manually adjusted, and the adjustment takes time and effort. Further, the adjustment voltage V1 does not necessarily have to be set only once, but must be adjusted each time the recording tape is changed.

Therefore, the present invention has been developed to achieve the correct duty cycle without being affected by the frequency characteristics of the playback device or the level fluctuations of the recorded signal itself.
An object of the present invention is to provide a digital data slicing circuit that can automatically set a slicing level at which data of (50%-50%) can be obtained.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides means for sampling and holding the positive direction peak value of a data synchronization signal, means for sampling and holding the negative direction peak value, and both of the above-mentioned means. and a comparison means for performing waveform shaping using the obtained average voltage as a digital slice level.

(Function) With the above means, even if the human signal has waveform rounding or DC level fluctuation due to frequency characteristics, the data slice level can be set to 50% - 50% of the waveform cycle of the input signal.
50% position, and accurate data detection can be obtained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a video waveform signal on which, for example, a PCM digital audio signal is superimposed is supplied to an input terminal 11, and this signal is supplied to an amplifier 12 and a sync separation circuit 20.

The output of the amplifier 12 is supplied to one input terminal of a positive peak detector 13, a negative peak detector 14, and a comparator 17.

The forward peak detector 13 includes a transistor Ql.

Q2. It consists of a W resistor R1 and a capacitor C1, and a voltage corresponding to the peak value is charged to the capacitor C1, and the current flowing to the transistor Q2 is limited. Therefore, a voltage corresponding to the peak value of the input is applied to the emitter of the transistor Q2.

- Force negative direction peak detector 14 includes transistors Q3.
Switch 141. Precharge capacitor C2, transistor Q4. ) is accomplished by resistor R2.

The precharge capacitor C2 is precharged with a voltage via the switch 141, but the data synchronization signal DSY
In the negative polarity position, switch 141 switches and the voltage on precharge capacitor C2 is discharged via transistor Q3.

The amount of discharge at this time corresponds to the negative peak value of the manually input signal. As a result, a voltage proportional to the charging voltage remaining in the capacitor C2, that is, a voltage proportional to the negative polarity peak value is applied to the emitter of the transistor Q4.

Therefore, at the output ends of the positive direction peak detector 13 and the negative direction peak detector 14, voltages corresponding to the positive direction peak value and the negative direction peak value of the input signal are obtained. Each of these peak-to-peak voltages is sent to a sample-and-hold circuit 15.
capacitor C1l through switches 151 and 152 in
, C12.

The voltages held in the capacitors C1l and C12 are supplied to the average voltage circuit 16 via buffer amplifiers 153 and 154, respectively. The average voltage circuit 16 includes a resistor R
11 and R12, derives the midpoint potential of the peak-to-peak voltage, and uses this as the slice level for the comparator 1.
7. By this, comparator 1
7, waveform-shaped digital data with a duty of -50% to 50% can be obtained.

The aforementioned switches 141, 151, and 152 are controlled by timing means for processing the horizontal synchronization signal from the synchronization separation circuit 20, that is, the monostable multi-by-break 21.
, 22.23.

FIG. 2 shows the input video waveform signal, especially the data synchronization signal D.
SY part and monostable multi-bi break 21.22.23
Output MMI, MM2. It shows the relationship of MM3. The output MMI of the monostable multivibrator 21 is set to rise at the start edge of the horizontal synchronization signal HD and fall at the end of, for example, the first half cycle of the data synchronization signal.

Moreover, the output MM2 of the monostable multivibrator 22 is
It is set so that it rises when the output MMI falls and falls just before the half cycle period of the data synchronization signal elapses.

The output MM3 of the monostable multivibrator 23 rises and falls between the end of one cycle of the data synchronization signal and the start of the next cycle.

Therefore, when the data synchronization signal DSY starts from a positive half cycle as shown in the figure, the precharge capacitor C1 is precharged during the high level period of MM1, and M
During the high level period of M2, the voltage is pulled out until the voltage corresponds to the negative peak value. Then, a voltage corresponding to that voltage is sampled and held in the capacitor C12 at the timing of MM3. On the other hand, in the forward direction peak detection, a voltage corresponding to the peak value is charged to the capacitor C1 due to the polarity of the transistor Q1. When the peak value of the input becomes small, the charge in the capacitor C1 is discharged through the resistor R1.

As described above, the circuit of the present invention always detects the positive and negative peak-to-peak values of the data synchronization signal DSY and automatically determines the midpoint potential Vs. Therefore, even if the data of the input video waveform signal is distorted due to the frequency characteristics of the VTR, or DC level fluctuations occur due to the recording and playback characteristics, the slice level Vs
will always automatically follow the position where the positive/negative duty is 50%-50%. FIG. 3(a) shows an example when the data synchronization signal DSY is input in a normal form.
b) The DC level of the data synchronization signal DSY fluctuates;
Moreover, an example is shown in which the input is made with a small amplitude. In either case, the slice level Vs is automatically determined at the midpoint between the peak values in the positive and negative directions, and the comparator 1
7, good digital data with a duty of -50%-50% can be obtained. This slice level Vs
is held until the arrival of the data synchronization signal for the next horizontal period. Normally, data in the horizontal period is processed using the synchronization signal DSY as a reference, so if the slice level is set with reference to the data synchronization signal DSY, the subsequent PCM data will also be well shaped. .

Note that in the above embodiment, the level is determined by slicing in the first cycle of the data synchronization signal.
The present invention is not limited to this, and it may be determined in the second cycle. Alternatively, the slice levels may be detected separately in the first cycle and the second cycle, and the average thereof may be used as the slice level.

"Effects of the Invention" As explained above, the present invention provides a digital data slicing circuit that can automatically set an appropriate slice level without being affected by the frequency characteristics of the playback device or the level fluctuations of the recorded signal itself. can do.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 and 3 are signal waveform diagrams shown to explain the invention in detail, FIG. 4 is an explanatory diagram of a video waveform signal, and FIG. FIG. 5 is a diagram showing a conventional digital data slicing circuit, and FIG. 6 is a signal waveform diagram shown to explain the operation of the circuit shown in FIG. 13.14...Peak detection circuit, 15...Sample and hold circuit, 16...Average voltage circuit, 17...Comparator, 21,22.23...Monostable multi-bi break. Figure 2 Figure 3

Claims (1)

[Claims] In an apparatus for processing a video waveform signal on which a data synchronization signal and digital data are superimposed, means for sampling and holding a positive peak value of the data synchronization signal, means for sampling and holding a negative peak value of the data synchronization signal; A digital data slicing circuit comprising: means for obtaining an average voltage of the output of the means; and means for waveforming the video waveform signal using the average voltage as a slice level.