DE2759868C2 - Arrangement for generating a square-wave output signal for use in a device for changing the phase of a video signal - Google Patents

Description

The present invention relates to an arrangement for producing a rectangular Output signal for use in a device for changing the phase of a video signal according to the General term of the patent claim 1.

Such an arrangement is generally in recording and reproducing devices and especially in devices can be used for recording and reproducing television signals using digital technologies.

The ongoing technological advances have to led to various changes in devices, soft in Television broadcasting stations are used. One of the more significant changes is that photographic techniques have been abandoned in many places by commercial television broadcasters in favor of magnetic media. For example feature films that are broadcast often no longer come from a film strip, but from a magnetic tape. Even television broadcasting station news departments are largely migrating to video tape recording systems; for visible representation New news, movie cameras are being pushed back more and more. In addition, they are often moving Take advantage of transmission stations, which send information either directly from their location or to a station from which the information is either sent live or on a Videotape can be recorded, edited and broadcast at a later time. One of Many advantages of such a method is the ease of use, the flexibility and the Processing speed can be seen in comparison to a photographic film. These benefits are with coupled with the possibility of being able to use the magnetic tape again if the one recorded on it Information is no longer needed.

One of the last remaining domains of film in today's commercial television broadcasting stations is that Image projection using 35 mm film transparencies. This image projection is used for Obtaining still television images, which for example for program information, advertising and Messages are used. In general, the aforementioned option is used wherever in the Operation a still picture is necessary. The effort for such image projection becomes from the fact It can be seen that a medium-sized commercial television broadcasting station has a total inventory of the order of about 2000 to 5000 slides of 35 mm leads. Maintaining such a total stock requires a lot of work that the Introduction of new slides, the sorting out

bad slides and the constant guidance of one exact composition required jnacbt, so that slides in case of need in easier Way are accessible. If program sequences are to be compiled from such slides, see above have to rtie the individual slides by hand Projection device, carried, cleaned and manual can be used. Alone during the cleaning process For example, dust particles and scratches can be unsatisfactory even with careful handling] o Produce results. In addition, after they have been used, the slides must be sent for broadcasting purposes removed and returned to their storage location. The whole process of putting together the use for broadcast purposes and the return of the slides due to the associated manual activities require a lot of labor The projection process is common in many modern day Broadcasting stations are to a large extent outdated and generally not with fully automatic station operation compatible.

Generally speaking, the invention is based on the fact that, in contrast to projection devices or the use of opaque graphic material as a source for creating still Video images recording and playback of still images is possible, with the video information in the form of still images on magnetic Media is saved. Generally computer-controlled standard disk drive units (which, however, are modified in certain aspects) used with magnetic storage media, eliminating those associated with the projection of slides Problems are avoided. As the still images are recorded on magnetic media, occur Problems of mechanical impairment, for example from dust particles or scratches not on. Since the recorded information is still easily accessible, the same still picture can can be used practically at the same time by operators at different locations.

From US-PS 37 32 362 a signal processing system for magnetic recording and reproducing devices is known, with the trouble-free Playbacks in slow motion mode and in operation with still images are possible. Such reproductions are achieved in that odd and even fields of the video signal are reproduced several times in certain combinations. This will be the Video signal sent via two prides, which are a delay stage delaying half a horizontal line period or a non-delaying equivalent Stage with the same frequency characteristics as the delay stage. Behind these paths there is a consolidation on a switching stage, by means of which either delayed or undelayed Fields of the video signal can be switched to an output. Switching takes place via Switching pulses whose adjustable pulse-pause ratio determines the degree of deceleration in slow-motion operation up to standing images.

Such a system works on an analog basis. In In modern recording and playback devices, the analog video information is converted into digital data sequences, which are then transferred to a magnetic one Medium is recorded.

The present invention is based on the object of specifying an arrangement of the type in question, the output signal of which is suitable as a tactile pulse signal for transferring the analog video information into digital data sequences.

In an arrangement of the type mentioned at the outset, this object is achieved according to the invention by the features of the characterizing part of claim 1

As is to be explained in more detail below, will a full NTSC video information sequence of four Half-images utilizing only one field of recorded information with two fields reproduced. In the arrangement according to the invention, a comb feeding technique for separating and Processing of chrominance information used, to selectively invert the chrominance information during reproduction of the two fields of the recorded information. Since the analog color video information signal with an odd multiple of Chrominance subcarrier frequency is sampled, makes it is desirable to use the KammFJier-Tecjhnik, the video information slgaal. using a tactile clock whose phase alternates in each successive line. This is called PAL coding clock technology (PAL = phase alternating line), which is described in more detail below is described. For the sake of simplicity, this common abbreviation is used below Arrangement further includes circuitry for ensuring that the sample values are in the correct Phase positions are taken with respect to each period of the subcarrier frequency, as well as a phase-locked one Precision loop circuit which requires that the phase of the color sync component of the Chrominance subcarrier, which occurs in the horizontal blanking interval, does not change its phase in successive lines.

The arrangement according to the invention is used to generate a control signal which controls the phase change of the key clock and other parts of the arrangement so that generally only the active part of the video line is changed in phase in successive lines and that the periods of the color synchronous component occurring in the horizontal blanking interval Chrominance subcarrier are not affected.

Refinements of the inventive concept are characterized in the subclaims

The invention is illustrated below by exemplary embodiments shown in the figures of the drawing explained in more detail. It shows

F i g. 1 is a perspective view of a recording and reproducing device with a device-specific input device and two disk drive units, from which the overall appearance of the device can be seen;

Fig. 2 is an enlarged perspective view a representative remote input device used by an operator to control the functions the device is usable;

Fi g. 3 is an enlarged plan view of the keypad of the device's own input device according to FIG. 1, from which in particular the information provided by an operator various buttons and buttons that can be actuated can be seen;

F i g. 4 a simplified block diagram to explain the general functions of the entire device;

F i g. Fig. 5A shows part of a typical television signal for explaining its vertical interval;

F i g. 5B shows part of a color television signal from which

■ in particular the horizontal sync pulse and that Color sync signal can be seen;

6 is a block diagram to explain the basic operation of the signal flow path through the device during a recording operation;

F i g. 7 is a block diagram for the basic explanation of the signal flow path through the device during a playback operation;

F i g. 8A and 8B are a block diagram of the signaling system for the device including the control connections between the different blocks;

F i g. 8C is a timing diagram for explaining FIG Keying of a television signal and the phase relationships at various points in the signal system;

F i g. 9 is a block diagram of a video input circuit (similar to a reference signal input circuit) which forms part of the signal system of FIG. 9A isiiuCt;

10A is a block diagram of a reference logic circuit which forms part of the signal system according to F i g. 9A forms;

10B is a timing diagram for a PAL error flag generator in the reference logic circuit according to Fig. 10A;

11A to HD are a circuit diagram of the input circuit of the signal system according to the block diagram after 9; and

12A to 12D are a circuit diagram of the reference logic circuit of the signal system according to the block diagram according to Fig. 10.

Generally, a recording and reproducing device 70 as shown in FIGS. 1 to 3 two frames 71 and 72, which contain the associated electrical circuits and the display and control hardware. The last-mentioned components are shown in particular in the upper part of the frame 72. The device also has a pair of disk drive units 73, which are arranged next to the right-hand frame 72, each disk drive unit 73 carrying a disk stack 75 in addition to the two in FIG. 1 specifically illustrated disk drive units can be assigned to the device further disk drive units in order to increase its direct storage capacity. On the other hand, only a single disk drive unit can also be used. As can be seen from the following statements, however, many useful functions cannot be implemented with a single disk drive unit. The operational control of the device can be carried out by operators via several remote input devices, such as, for example, a remote input device 76 according to FIG. 2 or via a device-specific input device 78 provided in the frame 72. A video monitor 4 and a vector and an “A” oscilloscope 80 can also be provided in the frame 72. Phase control switches 81 are provided above the device's own input device 78. The device is controlled by an operator either via the device's own input device 78 or a remote input device 76, each of which has number and function buttons and keys as well as a display field 82 for thirty-two characters. With this display field, it is possible to read out information which is necessary to carry out the functional operations in operation and to display information such as the identity of certain addressed stationary images and others Information concerns. The in Fig. 2 shown Remote input device 76 is representative of all remote input devices, with 70 to controlling the device to seven remote input devices can be provided. The in Fig. 1 generally designated 83 The keyboard field of the device's own input device is shown in an enlarged partial view in FIG. This keypad is functionally more extensive than the keypad of the remote input devices, which have fewer function keys. As will be explained in more detail below, the keypad contains a larger matrix of keys 84 and a smaller matrix of function keys 85 on the left side of the Keypad. Furthermore, a switch 86 operated by a rotary knob can also be provided which can be switched between normal and extinguishing mode. This is a security against the Possibility of incorrect or unauthorized deletion? .Μ · ν of grooved still images possible. According to the greatly simplified block diagram of FIG. 4 the device is recording a video input signal, which is processed by a recording signal processing circuit 88 and then fed to a recording signal branching circuit 89 which feeds the signal to all disk drive units 73. One in each one specific Disk drive unit 73 provided gate circuit w'Cd effectively switched to the signal on a to record specified disk drive unit. In order to record the signal supplied by the recording signal branching circuit 89, more than one slice unit 73 can also be selected at the same time. Instead of the signal branching circuit and the associated gate circuit Circuitry can also be provided to reverse the signal from the recording signal branching circuit 89 only to a specific disk drive unit with disk stacks 75 link on which the signal will be recorded. During playback, a signal from one of the disk drive units is fed to a playback switch circuit 90 which switches it to one of couple a plurality of playback channels 91, which each form a video output channel. Regarding the regulation of the overall operation of the various components of the apparatus is with the recording signal processing circuit, the recording signal branching circuit and the drive units as well as the Remote input devices and the device's own input device are coupled to a computer control system 92 As in FIG the following will be explained in more detail, came. an operator selects a particular target, on which an image is to be saved, provided the disk stack is connected, i.e. H. with others In words, it is in one of the disk drive units 73 inserted In this context, it should be noted that the device addresses disk stacks and not disk drive units. that the device is used to identify up to 64 eo separate stacks of discs, only one of which is in a disc drive unit at the same time can be introduced. If the device has two disk drive units, only two disk stacks can be connected at the same time. the The operator can use a keypad 83 of an input device, with the assistance of the Computer system to enter the address of a stack of discs on which an image is to be recorded,

wherein the disk drive unit into which the selected stack is inserted can perform the recording operation on the selected connected disk stack. In a corresponding manner can an operator reproduces an image from the stack of discs in a drive unit and determines the reproduction channel through which the image is to run.

D $., The device has four main operating modes, namely 1. Record / Delete, 2. Playback or Playback, 3. Sequence Composition and 4. Sequence Playback. First, the recording and reproducing operations will be described with reference to FIGS. 6 and 7 described which show simplified block diagrams of the signal flow paths during recording or during playback in cooperation with one of the disk drive units 73. According to the recording signal flow block diagram of FIG. 6, the composite video input signal is fed to an input circuit 93 in which this signal is clamped and the synchronous and subcarrier components are separated. In the The input circuit also includes the synchronous and subcarrier signals for later use Playback recovered. The recovered synchronous and subcarrier signals are combined into one Clock generator 94 fed in, which generates reference signals for controlling subsequent components. The clamped analog video signal with the color sync component is fed to an analog-to-digital converter 95, which has an output signal with a Sampling frequency of 10.7x10 * samples per second with each keying eight information bits The digital video signal is in an NRZ code; H. it is a binary code, which is defined by a one as the high level and a zero as the equivalent low level The digitized Video signal appears on eight parallel lines with one bit per line and is encoded and encoded Synchronized word input circuit 96 fed, which converts it into a special recording code. This code is hereinafter referred to as the Miller code or Miller square code. This code is particularly suitable for a digital magnetic recording, since it contains the direct voltage content of a Data stream is minimal The circuit continues to give in every other television line with respect to one certain phase angle of the color subcarrier represented by the color sync component a sync word. This synchro word serves as a reference for the correction of time base and skew errors, soft when reproduced in the eight parallel data so Data bits occur which are combined to determine the value represented by each keying have to. The digital video formation in the eight parallel lines is then fed into a recording amplifier circuit 151 and a head switch. terkreis 97 fed, which is assigned to the selected disk drive unit 93 and between two groups of eight recording heads for recording the digitized video signal through the Disk drive unit switches over The disk drive unit is servo-controlled so that its shaft speed is related to the vertical synchronous signal, with the disk speed is 3600 revolutions per minute The device records a television field per revolution of the stack of discs and a vertical synchronous signal at the same time eight data sequences on eight disk surfaces. After completely recording a Field, the recording amplifier circuit 151 and the head switch circuit 97 are driven so that that another set of heads for simultaneous recording of the second field on one Another set of eight disk faces is activated, so that a full television picture through 16 heads at two Revolutions of the disk drive unit can be recorded, each disk stack on one Disk drive unit preferably includes 815 cylinders each having 19 recording surfaces and therefore can store 815 digital television pictures. One for each of the 19 disk recording areas Stack of discs a Schretb read head is provided, with all heads vertically aligned on one common carrier are mounted, the position of which is controlled by a linear motor. It is in this It should be noted in the context that a cylinder is defined in such a way that it encompasses all recording surfaces, which are arranged on the same radius of a stack of discs. Instead of the term cylinder however, in the present context the term track is preferably used, which means that such a track all recording areas on an equal radius, i. H. all surfaces of a cylinder Therefore, the term addressed track for recording or reproducing an image refers to the 19 individual surfaces on the cylinder in this radius. Of the 19 on record Available areas are used to record address and other identification information and not to record active video information. This area is specifically referred to as the “data track”. Two of the 19 surfaces are standing for recording a parity bit, while 16 areas are available for recording the video data be available. This fact is explained in more detail below. One of the also runs Heads, which is referred to as the servo head, on the twentieth disk stacking surface, merely give way Contains servo track information prerecorded by the stack manufacturer Performs two functions. First, following a search command, the head track runs through servo stages, which are used to determine the instantaneous position of the Heads are counted. After completion of a search phase, the servo head generates an error signal that is used for Control of the linear motor position is used to center the head carrier on the appropriate servo track keep. When using such a feedback system, it is possible to achieve a radial packing density of about 400 tracks per inch or a total of 815 tracks per disk stack.

Since the device in question does not have any memory because of the frequency limits of disk stacks analog video signals, the video signal is digitized for recording digitized signal is recorded, the signal-to-noise ratio of the system is primarily determined by the Quantization noise and not from the noise of the recording media and preamplifiers determines, as is the case with conventional video tape recorders, that is at issue The device ensures a signal-to-noise ratio of around 58 dB, with effects such as moiré and residual time base errors are absent, so that the digital statistical error of the memory channels is typically small enough to make possible transmission errors virtually invisible.

By recording a digital data sequence with a repetition rate of 10.7 megabits per second Each of the eight disk areas, the linear packing density of the device is roughly equal to 6000 bits per inch, which is around 60% more than the packing density for conventional disk drive units in data processing lies.

Read on re-guoe according to FIG. 7 the heads extract the digital video information from eight areas per field, the recorded coded digital video information per channel being obtained from the odd and even fields. The reproduced signal is fed into a reproduction amplifier circuit 153 and the head circuit 97, which are assigned to the selected disk drive unit 73, the data sequences of the digital video information carried through the eight data bit lines being amplified and fed into an equalizer and data detector circuit 99. The equalization part of this circuit compensates for phase and amplitude distortions in the signal due to band limitation effects of the recording and reproduction processes, whereby it is ensured that the zero crossings of the reproduced signal are precisely defined. After the equalization, the coded signals are processed on each data bit line of the channel in a manner to be described below for transmission to the playback circuit of the signal system via a twisted pair of lines Change in the signal state of the coded channel signal. The twisted wire pairs for the eight data bits of the digital video information carry the processed coded channel signals to a decoding and time base correction circuit 100 of one or more of the playback channels 91 of the device. The decoding and time base correction circuit 100 converts the received signals back into channel code format, decodes the signal into NRZ digital form, and time base correction of the digital signal with respect to a station reference signal to eliminate timing errors between the data bit lines (usually as skew errors and to eliminate timing distortions in the data sequences carried through the data bit lines. The time base correction part of the circuit 100 thus serves to correct the eight bits in the sense of a single keying and to eliminate time distortions in the individual data bit lines relative to the station reference signal. It should be noted that each playback channel 91 includes an equalizer and data detector circuit 100 and that in each playback channel, a sequence of eight bits of data by a separate equalizer and data detector circuit passes the output signal of the circuit 100 is then in a comb filter and Chromainverterschaltung 101 injected which separates the chroma information and selectively inverts the signal to reconstruct an NTSC-rate with four fields and recombined This back formed digital signal to analog converter Digital 102 is then fed into a which an analog video signal returns to produce a composite analog video output signal of the playback channel 91 will be then added by a processing amplifier 103 new sync and color sync signals

Compared to the above explanation of the signal flow paths for both recording and playback operations is: the signal processing system for the composite television signal is far more complex, than the signal flow circuits according to FIGS. 6 and 7 show. The video signal system is as follows on the basis of the block diagrams according to FIGS. 8A and 8B described in more detail. As far as possible, be for yourself corresponding functions the reference symbols already selected above are also used. The block diagrams 8A and 8B also contain more lines to represent the flow of video data through the signal system and other connecting lines that control the timing and synchronization the circuit given by the various blocks. The connection of the signal system with the computer control system explained (on the basis of the block diagram according to FIG. 8) are also shown. The corresponding input and output lines for the various blocks in the Figs. 8A and 8B, which relate to the computer regeneration 32 are marked with an asterisk.

The device according to the invention is described here in connection with the NTSC system in which a TV picture has 525 lines and the horizontal sync pulses with a repetition rate of about 15.734 Hz occur, i.e. H. the period between consecutive Horizontal sync is approximately 633 microseconds. Furthermore, the Vertical blanking frequency in the NTSC system 60 Hz, the chrominance information with a subcarrier a frequency of about 3.58 MHz is modulated. The subcarrier frequency of 3.58 MHz is as follows also referred to simply as SC, by which the simple subcarrier frequency is meant, with others usually necessary clock frequency in the device can be designated accordingly with '/ 2 SC, 3 SC and 6 SC. the triple subcarrier frequency (3 SC) often occurs because during keying of the analog composite Television signal for its digitization a sampling frequency equal to three times the subcarrier frequency, d. i.e. a frequency of 10.7 MHz is used.

Before a detailed description of the block diagram according to FIG. 8A are intended to do some basic Comments on the overall function of the signaling system shown are made. That in the Video input circuit 93Λ fed video input signal is initially an analog signal that is used for Further processing is fed into the analog-digital converter 95. The output of this converter

thus contains the video information in digital format, the digitized data being further processed and recorded in a digital format on a stack of discs. In this form, the signal is also reproduced from the stack of discs, corrected with regard to the time base and the chroma component is separated off, the processing being carried out using digital technology -Analog converters and sync and color sync insertion circuits provide the analog composite video output signal.
In the analog-to-digital converter 96, the analog

F5 composite video signal three times per subcarrier basic period, i.e. sampled with a sampling frequency of 3 SC (10.7 MHz), with each sampling value digitally in a 8-bit digital word is quantized. A tactile clock signal

with a frequency three times or any odd multiple of the NTSC subcarrier frequency is necessarily an odd multiple of half the horizontal line frequency. If such a key clock signal is phase-steady from line to line, its phase changes at the beginning of successive lines. If such scanning clock signals, which are phase-constant from line to line, are used, the instantaneous amplitude of the analog signal is scanned at different times during successive lines relative to the beginning of the successive lines. For this reason, the quantized sample values are shifted vertically from line to line. A vertical alignment of the sample values from line to line is desirable in order to facilitate the use of a digital comb filter which is used to obtain a separated chrominance component of a television signal by quantizing sample values of three consecutive lines of a television field (only odd or only even fields) with one another be combined. These three consecutive lines can be designated with Γ (for the upper edge of the image), M (for the center of the image) and B (for the lower edge of the image), whereby the following relationships apply:

(Chrominance) C ■■ = M-Ui (T + B)
(Luminance) Y = M + UifT + B)

25th

Are the keys of the NTSC television signal with carried out an even multiple of the subcarrier frequency, the comb filter technique is ideal because the The phase of the key clock signal does not change from line to line. The digital code words or the quantized ones Sample values then describe the instantaneous amplitudes of each line of the analog signal at the same points in time relative to the beginning of each line, with all sample values in consecutive lines vertical from the top Edge of the image are aligned over the center of the image to the lower edge of the image.

The lack of a vertical alignment of the sampling values of successive lines when using a sampling clock signal with a frequency of 3 SC which is phase-continuous from line to line can be explained with the aid of the signal diagram according to FIG which are sampled by the positive jump of a sampling clock signal with a frequency of 3 SC (Fig. 8C (3)). The positive jump is identified by an arrow with a »χ« in the touch point. The touch points of the auxiliary carrier for TV line 1 are also identified by the »χ« (Fig. 8C (I)). There are three tactile points in each period of the subcarrier. During a television line 2, ie during the next line, the subcarrier according to FIG. 8C (2) and accordingly also the key clock signal with the frequency 3 SC have opposite phase (FIG. 8C (4)) relative to the phase in the line t (Fig. 8C (1), 8C (3)), so that the sample values during TV line 2 in the points marked with χ of the auxiliary carrier (Fig. 8C (2)) in the event of positive jumps. The sample values marked by χ are shifted from line 1 to line 2 with respect to the subcarrier base frequency by 60 °, which has a disadvantageous effect on the operation of the comb filter by the fact that it instantaneous amphetization of the analog signal according to the equations given above ιχ-ϊ night extraction the Chromfeanzäifofination acsgenbUt will E?

it is therefore to be noted that all sample values in odd lines and all sample values in even lines are vertical are aligned with one another, but the sample values in even lines relative to the sample values in odd lines by 60 ° with respect to the subcarrier fundamental frequency are shifted.

To do this by keying with an odd multiple of the subcarrier frequency, i.e. with the Avoid frequency of 3 SC in the device according to the invention z ", the vertical orientations of the Sampling values achieved in all lines by changing the phase of the sampling clock signal in every second line. In the in Fig. FIG. 8C shows the examples shown in FIG. 8C (5) the key clock signal with the frequency 3 SC for the TV line 2, the phase of which compared to the key clock signal for TV line 2 according to FIG. 8C (4) is inverted. By touching for positive jumps in the touch points marked with "O" result Touch points "O" on the auxiliary carrier for line 2 according to FIG. 8C (2). This means that the touch points are in the Auxiliary carrier for television line 1 (»χ«) aligned vertically to one another relative to the touch points (»O«). This results from the keying with a changed phase of the keying clock signal according to FIG. 8C (5) instead of eggs Keying with the signal according to FIG. 8C (4). This technique is commonly called PAL (Phase Alternative Line coding) In the following, this abbreviation or also the term phase inversion is used or phase reversal is used.

A comb filter technique with a sampling frequency of 3 SC is used in the device according to the invention or 10.7 MHz is used, so that a PAL key clocking is required. However, the phase reversal does not apply, when a keying frequency of 4 SC is used. Such a sampling frequency of 4 SC can be used for the case in device according to the invention can be provided that the frequency characteristics of the recording media, d. H. the disk stack on the disk drive units for operation at a frequency of 4 SC and 143 respectively MHz is sufficient. In this regard it should also be noted that standard disk drive units in data processing usually work in the range of about 6V2 megabits and that the recording with a repetition frequency of 10.7 meg ^ lit a sufficient increase in the packing density of the disk stacks guarantee yourself.

The use of a phase inversion according to FIG. 8C results in another important consideration in the operation of the device according to the invention. By changing the phase of the key clock signal in each successive line, a phase discontinuity necessarily occurs with respect to the subcarrier. However, during the channel coding of the signal for the subsequent recording, it is more expedient to code the digitally quantized sample values with respect to a continuous phase clock so that there are no phase discontinuities from line to line. For this reason, the PAL data at the output of the analog-digital converter from the channel encoder is clocked out with a clock that has a continuous (ie no discontinuities) 3-SC phase from line to line Line phase-continuous clock signal, the data is shifted in time in every second line by half a period of the triple HflfträgerfrequeriE, which disrupts the keying, which is timed by line m Zeüe due to the keying with a PAL clock

t3

2 ^ 59 14 _s

Chroma processing circuit for playback of the sample values of the godparents in a vertically aligned sequence from Zepe to line is required (this is the Giwd wjjx, where a P ^ -Ta ^ t clock signal in the analog-digital converter for the application kpmmtX, it is necessary to transfer the godparents from the confluent phase clock to the PAL clock rtcto5Utakten; sq that the task tone is increased and the chroma processing comb filter can process the data without errors. The analog-digital converter samples the analog signal using _t0 emesPÄL clock with phase discontinuities from line to line KanaJcodierer the PAL data with a phase clock that is continuous from line to line, which makes a reverse clocking of the NRZ information necessary for playback and post-decoding in a PAL clock for use in the chroma processing circuit Data stored in disk memory is played back and used for Aufeefchnung is transferred to another disk storage. In these cases, the phase clock of the reproduced video data, which is continuous from ZeSe to line, is retained, the data being recorded again without disturbing the data clock.

The above explanations are explained below with reference to FIG. 8C, in which the PAL data for lines 1 and 2 in FIG. 8C (6) and 8C (7) are shown. The bits A 1 to E 1 are successive bit cells which represent the instantaneous sample values of the analog video signal, denoted by X in line 1, according to FIG. 8C (1). Each heating cycle lasts for a full working cycle of the 3-SC cycle according to Fig. 8C (3). Correspondingly, the bit cells A 2 to E2 of the line 2 represent data which correspond to the sample values "0" in FIG. For the clocking of the PAL data with a 3-SC phase clock continuous from line to line, the clock points of the phase clock continuous from line to line are indicated by arrows under the bit cells according to FIGS. 8C (6) and 8C (7) This clock generates the shifted BitzeÜen according to the relation according to Fig. SC (8) and 8C (9) Keep timing.

JJm back-clocking the data from the phase clock, which is continuous from line to line, in deo PÄL clock, so that the bit lines (sample values) are aligned vertically to one another in the intended sense (Al is aligned vertically to Al, B1 is aligned vertically to B1 , etc.) , the reverse clocking from the continuous phase clock to the PAL clock must be carried out correctly so that no misalignment of the bit cells occurs to ensure correct playback when reversing from continuous phase to PAL in the left part. In the case of data continuously clocked from line to line in the phase according to FIG. 8C (8 and 8C (9), arrows shown in solid lines therefore reproduce the correct complementary clocking for the two television lines, the back clocking of the data in the PAL clock being vertical to one another aligned cells Al and Al according to Fig.8C (10) and Fig.8C (II) takes place right-clocked BtaeUeB, .which vqn.PAL clocked back to continuous phase, who ^ eiv! ^ e ^ ejj, opposite Unksgettktet, w * s SJch..ajj $ der ^ pj ^ itu ^ g of the Bitzeflen (for example. ^ ^ der Bützelje A ^^ i) mif jpren associated Tai ^ fenengeniäO FIg ^ C (6) .undß ^ (8) results If the complementary clock: jujäjt <ii | r? r? r? led, the bit cells are not r & htjg ^ aligned with each other, as shown by dashed lines, the elite arrows according to FIG. 8C (8) ip ||; i g. 8C (9) is angeäejitet Damh arises the m dä ^ H, ig.8q ^ (i ^ u ^ d JC ^ (I?) Shown connection .-- The Rjickt ^ tnng either from PAL to continuous, Phfse ^ oäeJr'.Vvon continuous phase on PAL is carried out at various points in the system, which is explained in more detail below. _ \

It should be noted that the NTSC television signal has no special defined relationship between the horizontal synchronous pulse occurring in each line and the phase angle of the subcarrier. The phase of the carrier changes by 180 ° from line to line. In other words, the Phsssn ^ iake! of the HÜfsträgersignals change relative to the horizontal sync signal from video source to video source, so that the Horizpntal synchronsignal in the device is not suitable for regulation Basic timing reference is used for the system, defining a new signal related to the horizontal sync signal that is used in place of the horizontal sync signal for timing purposes. The new signal related to the Horäontal Syndiron Impulse will! chosen so that it has a frequency equal to half the nominal horizontal line frequency because, it is an integer number of periods, the subcarrier frequency v φ h. two complete horizontal lines representing the subcarrier frequency or 455 periods Synchronous word inserted into the video signal at a point which roughly corresponds to the point of the horizontal sync pulse, where. phase coherence is guaranteed with respect to a certain phase angle of the subcarrier generated from the color sync signal component of the video signal -Synchronous pulse-related signal, which is related exactly to the phase of the subcarrier of the video signal.For the playback part of the signal system, a signal referred to as HIl is generated based on the horizontal sytichron pulse, which is coherent with a certain phase angle of the input reference subcarrier, whereby this phase angle can be selected by the phase control in the playback system '

The signal Uli related to the horizontal sync pulse serves as the basic reference timing signal for the system in playback operations.

By using the signal related to the horizontal sync pulse as the reference horizontal sync signal for the system, the signal processing for recording, reproduction and others

The system's operations are facilitated because a solid Time connection between the sub-carrier of the Video signal and the signal related to the horizontal sync pulse is guaranteed

By using internal Bessugs horizontal and subcarrier signals that are variable in time relative to the reference sync signal of the television station, In addition, a timing control is possible, based on which the television signal at the right time after the usual propagation delays can arrive at a distant place.

According to the block diagrams according to FIGS. 8A and 8B, the analog video input signal is fed to the input of a video input circuit 93A, in which it is subjected to various processing operations js before it is fed to the analog-digital converter 95. Specifically, the analog video signal is amplified in the video input circuit 93 / t, the DC voltage level is readjusted, the synchronous components contained in the video signal are separated off to generate clock signals for the signal system, a determination of the physical value of the horizontal synchronous pulse and a subsequent limitation of the horizontal -Synchronous pulse. In addition, the horizontal sync pulse is separated by a precision sync stage in order to be able to generate a regenerated sync fan pulse. The circuit still generates a regenerated subcarrier signal derived from the color sync signal in the input video signal or, in the absence of the color sync signal *, from the H / 2 reference signal generated from the input horizontal sync pulse.

It should be noted that the video input circuit 93A and a reference signal input circuit 935 in the lower part of the block diagram of FIG. 9A perform similar functions, with the video input circuit primarily intended for the signal recording part of the signal system and the reference signal input circuit primarily intended for the reproduction part of the signal system. For reasons of convenience in production and maintenance, identical circuits are used those input signals on which NEN Durchfahrung to the corresponding functioning 4 $ are needed. Although both circuits generate the same signals, not all signals from each circuit are used. The reference input signal for the reference signal input circuit is formed by the station reference black signal, which contains all components of a color television signal with the exception of the active video part, which is at black level Therefore, the input signal for the reference signal input circuit 93B as well as the input signal for the video input circuit 93A contain the color system signal, the horizontal synchronizing signal and corresponding signals. In addition, an H-phase position adjustment circuit is provided in the reference signal 935, which receives H-position controller signals, for example from a dial to adjust the to H phase position of the regenerated synchronous signal for the playback part of the signal system

Some of the output signals from the input circuits 93/4 and 935 are fed into reference logic circuits 125, 4 and 1255, which are assigned to the corresponding input circuit. The reference logic circuit 125A processes signals from the video input circuit during the recording operation device S3 A, from the Anatog-Pigitaj converter 95 and from the computer control system 92 and generates a number of recording clock signals with frequencies of 6 SC, 3 SC and 1/2 SC as well as a PAL error indicator signal from the PAL error indicator signal and via precision controls with phase-locked spheres the 3 SC signal is generated in the reference logic circuit 125Λ a 3-SC-PAL key clock signal, the phase of which is adjusted for each line of the video signal by the PAL error flag signal, which has a frequency of HI2. The PAL error flag signal changes its value with this frequency. This change takes place asymmetrically, ie the two values of the PAL error indicator signal have unequal time intervals. The asymmetry is chosen so that the key clock phase for the color sync signal part of the video signal is constant with the phase of the subcarrier and that only that part of the television line then has a key phase which is changed in successive lines. This FAL clock signal is coupled to the analog-digital converter 95 and represents the sampling clock signal for generating the sampling values with a frequency of 3; SC or 10.7 MHz.

The reference logic circuit 1255 generates from signals from the reference signal input circuit 935 and a clock reference signal to the computer control system 92 at a frequency of the high-frequency carrier (SC) and various other timing control signals. These signals are used in other operating modes of the device (non-recording of video input signals)

Generate during recording and playback the reference logic circuits continue to sync servo signals for the disk drive units to operate them in the right phase.

In addition to recording video input signals, a reference clock generator 98 generates at Playback and, in other operating modes, various clock signals and additional clock control signals, which are required for the various parts of the signaling system in these modes. The reference clock generator generates from input signals from the Reference signal input circuit 935 from the reference logic circuit 1255 (reproducing part of the signal system) and a control switch that can be operated by an operator, clock signals with frequencies of 6 SC, 3SC, SC and '/ 2 SC as well as various others Clock control signals, the reference logic circuits 125Λ and 1255 and the reference clock generator 98 together form the clock generator 94 according to FIG. 6, which supplies the timing control signals for the system

The clamped analog video input signal, from which the horizontal sync signal is separated, is fed from the output of the video input circuit into the analog-digital converter 95, which converts it into a binary-coded signal with eight bits in PAL-NRZ format.This coded signal is then converted The analog-digital converter 95 is not described in detail, since it is a known type which is contained, for example, in a device sold by the applicant with the type class TBC-SOO circuit diagrams for the analog-digital converter 95 can be found, for example, in a catalog with the number 7896382-02 from October 1975. Such an analog-to-digital converter can be found in circuit diagram no. 1374256 on page 3-31 / 32 and circuit diagram no. 1374259 on page 3-37 / 38 of the catalog.

The output signal of the analog-digital converter

The receiving encoder switch 126 contains circuitry which either encodes the digitized; Video data with eight bits from the converter or from a data transfer layer 129 as in the following is explained, enables the data remote circuit 129 a transfer of video information from one disk drive unit to another disk drive unit, as described above in relation to the operation of the The device was explained using the remote input devices or the device's own input device, In transfer mode, the digitized information is read out of the disk drive unit, in digital form NRZ format decoded, corrected in the time base and then put on the coding switch, which the Sources for the digitized video information for encoder 96 can select. Since the Disk drive units 73 recorded coded data with a clock of continuous phase are clocked are those of the data transfer circuit 129 recorded NRZ data is also usually clocked with respect to the continuous phase clock the paientrarisferschältang 129 receives a PAL error code signal, which is used to clock the digital NRZ data in relation to a PAL clock signal is used, so that the data fed into the comb filter and chroma inverter circuit 101 is in the correct PAL format are present. This reverse cycle is not required during transfer operation. The coding switch 126 contains a circuit for interrupting the coupling of the PAL error flag signal to the data transfer circuit 129, whereby the reverse clocking of the NRZ data referring to the PAL clock during the Data transfer operation is prevented

The encoding dialer 126 is controlled by the computer control system 92 to manipulate the video data from either the video or the transfer. areg to clock. It also switches between the video and reference timing signals of 6 SC and Ui SC since the reference timing signals are used during the data transfer operation and the video timing signals are used during the recording operation. The coding switch is also used to generate a signal that generates a flashing cross in the TV picture, which is a visual indication that the picture column or an address for a picture is free and thus available for recording. In addition, the coding switch generates signals for implementation of investigation functions.

The eight bit data from the coding switch 126 are then fed into the encoder 96, which initially generates a parity bit and encodes the PAL-Dalen in a Miller square channel code format, where it is a self-clocking, DC-free NRZ code. While PAL data is fed into the encoder, the encoder's output signal is a 9-bit data sequence (for inserted parity bit), which has phase continuity with respect to the frequency 3 SC Continuously phase-clocked data are easier to process, which applies in particular to decoding processes. contain voltage components which could occur over a period of time due to the dominance of a logical state, whereby the data in the Playback process could be disturbed. It is to the US-PS 40 27 335 in this context refer.

As already stated, the code format can be a DC voltage-free, self-clocking NRZ format

are designated, Bs is suitable for the transmission of Binary data over an information channel of limited bandwidth and limited signal-to-noise ratio, in which the data in a voltage-free, self-clocking format can be transmitted *

Binary signals are experienced in information channels with a limited bandwidth that do not transmit direct voltage Signals Distortion in the zero crossing, which cannot be eliminated by linear compensation networks. These distortions become common referred to as base line deviation and reduce the effective signal-to-noise ratio, modifying the zero passages of the signals and thus the Bit accuracy of the decoded signals are adversely affected. A common transmission format or channel data code used in recording and playback systems is disclosed in US Pat U.S. Patent 3108261. In Miller Code become logical ones through signal jumps at a certain point, i. in the middle of the cell, and logical Zeroing through signal jumps at a certain earlier point, ie. in the area of the leading edge of the Bit cell, represented. There are jumps in the Miller code at the beginning of an interval for a 1-bit following an interval containing a jump in its center suppresses asymmetries of the signal generated according to these rules can lead to a direct voltage component in the coiiiert signal so-called square »Miller Code«, which is in the device according to the present invention is used, the DC voltage content of the original Miller code effectively eliminated; without either a large memory or a repetition frequency change in the Encoding and decoding are required

The encoder 96 also generates a unique sync word in the form of a seven-digit binary number and inserts this sync word into every second line at a precise location which is determined by the clock signals with a frequency of 6 SC and ^x 1 SC. In the recording mode, the clock signals generated from the synchronous components of the video input signal by the reference logic circuit 12SA are fed through the coding switch 126 into the encoder 96, whereby the synchronous word is created which is inserted at a point which roughly corresponds to the point at which the horizontal sync pulse of the Video signal was present before. In other operating modes, the clock signals with a frequency of 6 SC and Ui SC are generated by the interaction of the reference logic circuit 1252? and the reference clock generator 98 is generated from the synchronous components of the station reference black video signal. The encoder scans the sync word related to the horizontal sync pulse in every second television line into the data sequence at the correct point in time relative to the regenerated subcarrier phase.

Before the recording, the data track information recorded on the data track of the disk drive units 73 is also encoded via the data track interface circuit 120.

According to FIG. 8B, the ten data sequences of the am Encoded digital data occurring at the output of the encoder 96 is fed into an electronic data interface circuit 89, which merely represents a signal separation and buffer circuit. This circuit couples the coded data to the three slices

Drive units 73 ζμ their recording on a data stack 75, each disk drive unit contains a data interface circuit 151 for this disk drive unit, which receives the data from the electronic line interface circuit 89 and routes them via a recording amplifier 153 and a Kqpfschaüer 97 for recording on an associated disk stack 75 The interface circuit 151 continues to receive reproduced data through the head switch 37 and a playback amplifier 155 and passes it to a data selection switch 128. In addition, the data interface circuit 151 for the disk drive unit receives a multiplex servo reference signal from the electronic data interface circuit 98 and transmits it to a timing generator (Fig. 39) of the disk drive control circuit. This signal is picked up by computer control system 92 from either reference logic circuit 125Λ or 125B. In the timing generator, the muluplex servo reference signal is used to timing the disk drive unit such that recording and playback operations and the speed of the disk stack 75 in the disk drive unit 73 are synchronized with a suitable system timing reference signal.

The disk drive control circuit performs pre-drawn lines Timing and data timing signals through interface circuit 151 for the disk drive unit back to the electronic data interface circuit 89. In the case of the special one at issue here Embodiment of the device according to the invention wjerden only two fields of the NTSC color television signal color code sequence recorded with four fields, the two fields in separate Revolutions of the disk stack 75 are recorded. Immediately before the recording of the two Fields of the video data are generated from the prerecorded timing signal and fed into the electronic data interface circuit 89 fed in This interface circuit transmits the pre-recorded timing signal to encoder 96 to produce an interval two equivalent to the color black Field data represents where this interval is digitally defined by logical zeros This data are fed back via the interface circuits, to be recorded on the disk stack in a track location which is suitable for recording of video data and its data track information. The record of the said Black data occurs during two revolutions of the disk stack 75 immediately before the two Revolutions during which the two fields of the video data are recorded. So that is Track location for the subsequent transfer of video data and data track information prepared Since the dubbing of previously recorded digital data with new digital data to obscure the previously recorded digital data can, with a recorded signal of sufficient quality for playback with acceptable ω Signal-to-noise ratio is guaranteed, the pre-recording cycle can be omitted, so that the recording of the two fields of video data and the associated data track information in just two Revolutions of the disk stack 75 can take place.

The data timing signal is fed back to the electronic data interface circuit 89 to provide the Generation and recording of the data trace information to clock in the second or last field of the two fields of video data. The signal is on Impulse, which after the vertical sync ring impulse e'er Two fields of video data begins and ends at the end of the second field during this interval the data track information is recorded on the data track of the disk stack 75. The electronic Data interface circuit 89 couples the fed back data timing signal to the data track interface circuit 120 of the computer control system 92 to set the system's data track recording interval identify. The computer control system 92 thus maintains the recording of the data track information relevant functions, which include, inter alia. this is what the data track information of the recording is about of video data on a specific track of the selected data stack. The encoder 96 records the data track information and processes it in the sense described for transmission to the Disk drive unit 73 as well as for simultaneous recording with the last HaJb # Jd of the video data, uie recording and playback amplifier 153 and 155, the head switch 97 and the disk drive control circuit of the device are assigned to each other so that the playback amplifier 155 and the Head holder 97 for data playback from the associated Disk stack 75 effective at all times except when a recording operation is being performed are switched. Except during recording, data played back is always from of the interface circuit 151 for the disk drive unit which receive the reproduced In turn, data is coupled to the data selection switch 128. When recording, a record command is issued from the disk drive control circuit to the recording and reproducing amplifiers 153 and 155 coupled to activate the recording amplifier 153 and the playback amplifier 155 to lock. The disk drive control circuit ■■ delivers furthermore, a head switching signal of 30 Hz for the head switch 97 during recording operations, whereby this is to record the data sequences during the first field of the two successive ones Field data on one set of heads and during the second field on the second set of Coupling heads This 30 Hz head switching signal is continuously available and is used for playback operations to control the head switch 97 to set the reproduction amplifier 155 to reproduce two To switch fields of a desired video data signal between the two headers.

In playback operations, the reference signal input circuit generate 93B and the Referenzlogikfch £ .'oijg 1255 according to Figure 8A, the regenerated subcarrier frequency for feeding into the reference clock generator 98, "Jessen output signals rr.k frequencies of 6SC '/ 2 SC and H / 2, the basic Form timing signals for playback operations. The output signals of the reference clock generator are fed into the decoding and time base correction circuit 100, the data transfer circuit 129, the comb filter and chroma inverter circuit 101 as well as a video playback output circuit 127, which inserts the output signal, performs a selective lock and a selected monochrome video signal as the output signal for the Singalsysteme delivers, if the heads, which are assigned to a disk drive unit coupled to the playback channel

are to be moved between the track positions. The eight-bit digital information is then stored in the Digital-to-analog converter 102 and the processing amplifier 103 fed, which synchronize signals and the burst signal starts. The reference clock generator delivers for transfer and examination processes 98 the basic timing signals for the encoder% via the encoder switch 126.

During playback, the parallel data sequence with 10 bits played back from a disk stack, which includes video data with 8 bits, the parity bit and data track information, is amplified, equalized and then detected via the interface circuit 151 for the disk drive unit in the data selection switch 128, which feeds the output signals of the three Disc antenna units can couple on one or more of three channels. The data selection switch can thus switch the information from the disk drive unit No. Iη the channel Λ or in two channels, while at the same time a data sequence is switched from another disk drive unit to another channel. While information from two disk drive units cannot be switched simultaneously into a single channel, the reverse is possible. The data selection switch 128 includes conventional switch circuitry which will not be described in detail here.

The captured data sequences with 9 bits of video data and a parity data are then fed from the data selection switch 128 into nine individual data decoders and time base correction stages in the circuit 100, which decodes the data and then the nine data sequences independently of one another with respect to a common H / 2 reference signal corrected in the time base, the latter signal being fixed with respect to the phase of the regenerated reference subcarrier in order to eliminate timing errors in the nine data sequences. All synchronous words are aligned with one another in such a way that each parallel 9-bit byte contains the correct 9-bit data. The data track information is only passed through the data selection switch to the decoding part of the circuit 100, the decoded data track information being coupled to the data track interface circuit 120 for transmission to the CPU 106. The time base correction is performed using a continuous phase clock. The data, however, is clocked back by the data transfer circuit 129 with respect to a PAL clock. That is, the phase of the signal is changed in each horizontal line by clocking back so that the data sequence coming from the data transfer circuit is again a true PAL signal. The data transfer circuit 129 also carries out a parity check of the data coming from the disk drive units. This is done by covering up individually occurring byte errors by substituting the most similar, previously occurring byte instead of the byte that was identified as an error. The substituted byte is the third preceding byte, which is equal to the earliest sample value which was obtained in relation to the phase on the subcarrier.

The output signal of the data transfer circuit is used in the case in the comb filter and chroma network 101 fed in when the video information are visually displayed soIL There is no recording to another disk drive unit (Transfer). For a transfer, the data are transferred from the data transfer circuit 129 to the coding switch 126 recoupled. The comb filter and chroma inverter circuit 101 separates using a comb filter technique removes the chroma information from the luminance information and inverts the chroma information in every other picture to form a composite NTSC signal with four fields, which then is fed to the video reproduction output circuit 127. In this circuit, during the Blanking period is a reference black level and more consecutive during the interval between displays Images of gray angel signals inserted. If necessary this circuit also performs bit locks. This bit blocking means that all bits or certain bits of an 8-bit television signal are blocked by suppressing the data bit sequence, which means that im resulting television signal special visual effects, such as increased color tones, ghosting and HMiihcMcS can be reached. The exit; s: gna! the Video playback output circuit 127 is then fed to digital-to-analog converter 103. This The digital-to-analog converter receives clock signals from the video playback output circuit 127 and transfers them the data in its analog form, with simultaneous sync and color sync components of the signal can be used to produce a full composite analog television signal.

The signal system of the Device according to the invention generally described in its overall function. Special descriptions of the Blocks according to FIGS. 8A and 8B are described below either with the aid of separate block diagrams or given on the basis of detailed circuit diagrams. For the block diagrams to explain the individual blocks according to the F i g. 8A and 8B, detailed individual circuit diagrams are also given.

A composite color video information signal intended for recording, for example, on a Disc stack 75 of the recording and reproducing device is to be digitized, is a preparation subjected to a number of process steps for recording. This includes generation of a key clock signal that corresponds to the video signal to be digitized and recorded Contained color subcarrier synchronous component is coherent. This key clock signal is used to control the Analog-to-digital converter 95, which is a PAL-coded clock signal, the phase of which is only is reversed every other line during the active phase of the video signal, so that the Color burst component through the Tasi and quantization processes not changed in phase will. The video input circuit 93Λ is used for Generation of a continuous synchronous component with the color subcarrier coherent SC signal in the reference logic circuit 125Λ according to the invention for generating said PAL-coded clock signal is exploited.

According to the block diagram for the video input circuit and the reference signal input circuit of FIG. 9 the video signal on line 200 in a video amplifier 201 is fed, which amplifies the signal and the DC component reset via a clamping stage 202 The clamping stage 202 samples the output signal of the amplifier on a Line 203 and generates a DC voltage component on a line 204, which is fed to the amplifier 201 is fed back The clamped video signal

line 203 is then passed through a low-pass filter 205, the output signal of which is on line 206 in a video control amplifier 207 is fed. This amplifier 207 is coupled to a further video amplifier 208, with a second Terminal stage 209 ensures that the blanking level of the signal has reference potential (ground level). This is done by feeding a DC voltage regulator into the video amplifier 208 via a line 210. The output signal of the video amplifier 208 is via a line 211 and a line 218 in the Key input of terminal stage 209 fed in. The line 211 continues to lead to a keyed one Synchronizing signal limiter stage 212 and a precision synchronizing signal separating stage 213. In the vis deoeingangsschluss 93/4 is still a remote gain control signal on a line 217 in a Comparison stage 216 fed in to control the control amplifier 207 from another point. That Output signal of a synchronous peak detector 2i4, which may still contain a ripple, is converted into a Input of the precision synchronous signal separator 213 fed, the other input via the line 218 is coupled to the output of the video amplifier 208. The two input signals of the Precision synchronizing signal separating stage 213 can also have a ripple, the feed being so takes place that the separation stage generates a ripple-free synchronous signal on a line 220, which on various synchronous stages 221 and an input of a horizontal synchronous phase detector 222 out The line 218 continues from the output of the video amplifier 208 to a less precise synchronizing signal separator 219 which is a less provides exact synchronizing signal This signal is fed into a pulse generator 223, whose The output is coupled via a line 224 to both the clamping stages 202 and 209 as well as the synchronous peak detector 214 the key pulse generator 223 a key signal that the clamping stages and the synchronous peak detector in the correct time during the horizontal blanking interval closes

The clamping stage 209 is not closed in an arbitrary period during the color sync signal time, but for an integer number of periods, so that the blanking level of the video signal can be obtained precisely by an integration technique. This function is described in more detail below. The color sync signal occurs both on line 210 and on a line 225, which is fed to a color sync signal limiter stage 226. This stage 226 is in turn coupled to an amplifier 227, which supplies complementary output signals from the limited input color sync signal. The output of the limiter stage 226 is coupled to a color synchronizing signal detector 228, one output of which is coupled via a line 229 to a precision tactile generator 230 and another output via a line 260 to a phase detector 231. If the presence of a color synchronizing signal is detected, the precision Tastgenerator 230 a precision color burst sampling signal which switches the amplifier 227 effectively, it whereby the middle three periods of the color burst signal are coupled to the phase detector 231st The phase detector yeasts as a result an error signal for a voltage-controlled oscillator 232, which is a measure of the phase difference between the output signal of this oscillator and the phase of the synchronous signal periods supplied by the amplifier 227.The phase detector thus controls the oscillator 232 in order to avoid longer-lasting changes in the phase to correct the three periods of the color sync signal, which are used in each line as a subcarrier reference. The output signal of the oscillator 232 is coupled via a buffer 234 to a line 233. The output signal of the oscillator is a continuous, regenerated subcarrier signal of the frequency SC (3.58 MHz), the phase of which is related to the existing color subcarrier signal. If, however, the color synchronization signal detector 228 does not detect a color synchronization signal, the phase detector 231 compares the phase of a W / 2 signal with the regenerated subcarrier output signal of the oscillator 232, the W / 2 signal being generated by a synchronous generator 255 by an oscillator 236 which is driven by the horizontal synchronous phase detector 222.

In the reference signal input circuit 93S, a horizontal phase position control, generally designated 237, is provided, which is used to adjust the horizontal position of the regenerated synchronous signal.For example, an 8-bit binary number is loaded into holding stages 238 via a dial that can be operated by an operator preset, which is clocked by a clock signal coming from the oscillator 236 at 400 Hz. When the counter reaches its end value, it triggers a sawtooth generator 240 with an output 241, which is fed to a second input of the horizontal synchronous phase detector 222.By setting the hold levels, up to plus or minus 20 microseconds can be set in the feedback loop on line 241 , wherein the phase of the regenerated sync signal can be adjusted for horizontal adjustment of the picture during reproduction. Since a delay in the feedback loop means that the regenerated sync signal is advanced, the horizontal position control can advance the image accordingly to compensate for transmission delays of a signal over cables in a television station. As will be explained in the following on the basis of a detailed description of the reference clock generator 98, this horizontal phase position control works together with a subcarrier phase control, as a result of which the delay can be controlled in small increments. In the embodiment of the device according to the invention in question, values of approximately ± G £ nanoseconds are involved.

The output signal of the oscillator 236 controls the synchronous generator 235, which is conventionally designed for television signal processing, in terms of generation various signals related to the vertical and horizontal synchronizing signal repetition frequencies according to FIG Fig. 9. This on the synchronous signal repetition frequency Related signals are related to the phase of the precisely regenerated horizontal sync signal from Phase detector 222 generated so that they are always related to the phase of the input signal.

An important aspect of the circuit of Figure 9 is that the horizontal sync signal of the video signal is exactly half its Value and the value of the blanking signal is accurate

is clamped to reference potential (ground). The regenerated subcarrier is related to the phase of the color sync signal, a precision horizontal sync signal being obtained by the precision sync signal separator. This signal is used in the synchronous generator 235 to generate a reset pulse (picture index pulse at 30 Hz) to reset a line identification or synchronous word insertion circuit to be described below. Since the clamping stage 209 detects a mean zero level of the video signal during the burst signal time using a clamping pulse which lasts exactly for an integer number of periods of the burst signal, no low-pass filtering of the video signal and switching off of the burst signal is necessary before the clamping process. This is due to the fact that the resulting integration of the burst signal is zero and that no H / 2 ripple is produced by the integration of a signal which does not contain complete periods of the signal.

The block diagram according to FIG. 9 describes the functional mode of operation of the input circuits. Special circuits for performing these functions are shown in FIGS. 1IA to 11D shown which represent a complete schematic of the input circuits as a whole.

With regard to the mode of operation of the clamping stage 209 (see Fig. HC), the voltage is at the output of the Amplifier 208 on lines 211 and 218, the latter of which to the base of an emitter follower transistor 244 is performed, at which a voltage drops. The blanking level is under equilibrium conditions of the video signal on line 218 to reference potential (ground). This signal is due of the voltage drop at the emitter follower 244 shifted by 0.7 volts into the negative. A matching emitter follower transistor 245, the emitter of which is connected via a line 247 to the inverting input of a differential amplifier 246 is coupled, just like transistor 244 shifts the comparison level (ground) into Negatives. The emitter of transistor 244 is connected to the non-inverting input d <: s differential amplifier 246 when a transmission gate or switch 248 is coupled during an integer number of periods of the burst signal is closed by a signal on line 224 which is determined by the in Key pulse generator 223 shown in FIG. 42D is generated. During the burst time is the switch 248 closed, whereby a capacitor 249 to the mean value of the burst signal being charged. The switch is closed for an integer number of periods of the subcarrier. In order to there is no need for low-pass filtering of the video signal in order to avoid the burst before the Switch off the clamping process, which in a known manner eliminates the /// 2 modulation of the clamping level he follows. The charging of the capacitor 249 exactly reproduces the mean value of the color sync signal, wherein the output signal of the differential amplifier 246 represents an error signal which is transmitted via a line 251, a transistor 252 and line 210, which is coupled to the emitter of transistor 252, to the Video amplifier 208 is coupled. The blanking level of the signal on line 211 is therefore due to the high DC voltage gain of the differential amplifier 246 held approximately at reference potential (ground). The mode of operation of the clamping stage 202 shown in FIGS. HA and HB corresponds to the mode of operation the clamping step 209.

According to FIG. IiC, the burst signal is at Closing the switch 248 keyed into the capacitor 249 and fed into the line 225, which from left part of the circuit of Fig. HC to the Circuit according to Fig. HA out and with the emitter of a transistor 254 is coupled so that the burst signal from its collector via a Line 255 is led to the burst signal limiter 226. If the color sync signal is available, so The burst signal detector 228 provides a limited burst signal on line 229 which the precision tactile generator 230 clocks. This key generator is designed as a counter, which periods of the limited burst and counts during the middle three periods from 9 to 11 periods of the Color sync signal interval generates a precision color sync signal key signal, which is transmitted via a line 255 on the. Amplifier 227 is coupled to this to switch effectively. Apart from the three middle periods of the burst signal, the amplifier 227 blocked by the output signal of the burst signal detector 228. Is the color burst present, a diode detector 257 and a subsequent hold circuit 258 of the detector 228 provide one a more negative value on a line 260 which leads to a switching transistor 259 (FIG. 11 B) of the phase detector 231 leads. If the color sync signal is present, the switching transistor 259 is blocked and another one Switching transistor 261 of detector 231 is turned on. If the transistor 261 is switched on, the three periods of the color sync signal v:> m amplifier 227 via a driver stage 277 to a transformer 262 of the detector 231 coupled. The driver stage is on a phase comparison stage 231a coupled to the phase of the burst signal with the phase of the Compare the output signal of the oscillator 232 of 3.58 MHz (SC), the latter signal on the Line 233 stands. If the detector 228 does not detect a burst signal, the transistor 259 becomes switched through, whereby the / ί / 2-Sign-jl on the Another input of the driver stage 277 is coupled, which is also connected to the transformer 262 is, the phase of the oscillator output signal on line 233 then having the phase of the /// 2-signal is compared.

The circuit part for separating the horizontal sync signal according to FIG. HC includes the acceptance of the sync signal from amplifier 208 on line 218 through a low pass filter 264, whose Output signal is coupled to the base of a transistor 265. The emitter of this transistor 265 is connected to coupled to a transmission gate or switch 266 which is activated during the presence of the Synchronization signal via the control line 224 is closed. The value of the synchronous signal is determined via the Charging of a capacitor 267 (Fig. HD) detected, which is coupled to an amplifier 268 at gain 1, where half the DC voltage level the peak of the sync signal along with the full value of those present in the signal Ripple is coupled via the line 215 to one input of the comparison stage 213, the other The input is fed via a line 269 coming from the emitter follower transistor 265. The output signal on the line 220 is therefore a separated synchronous signal, the timing of which is due to the ripple

the video signal is not influenced, since this ripple occurs at both inputs of the comparison stage 213 and no longer appears at the output because of the common mode operation. The synchronizing signal generated on line 220 represents a precision synchronizing signal which is used in other parts of the signal system to generate synchronous signals relating to the horizontal lines which are fixed with respect to a specific phase of the subcarrier signal. These signals serve as timing reference signals for processing the video signals in the signal system. The synchronous signal used in the system and related to the horizontal lines has a repetition frequency of ¹ Zi H, since an integer number of subcarrier periods is available for every two horizontal lines (227.5x2 = 455). This fact is important for the mode of operation of the device according to the invention, as will be explained in more detail below.

A less accurate split sync signal is also generated by the sync signal from the low-pass filter 264 via a line 270 to the less precise synchronizing signal separating stage 219 is, whose output signal is fed via a line 271 to the pulse generator 223, which contains a monostable multivibrator acting as a synchronous detector 276. A generally with 272 designated upper circuit part generates a key signal for the switch 266 to switch it during the Presence of the sync signal to close, while a circle 273 is a Sch yarzschulter key signal and a circle 274 generates a color sync key signal redefined in relation to the SC phase. With regard to the Detector 223 is to be noted that the synchronous detector 276 in the absence of a synchronous signal, which then not even on the line 271 going out from the less precise synchronizing signal detector 219 occurs, both the switch 248 in the clamping stage 209 via the circuit 274 and a corresponding one Switch 275 in the clamping stage 202 closes, so that all Clamping stages operate on a DC feedback loop rather than an open loop. If the sync signal is not present, the level on line 224 is high until the sync signal occurs again and is detected. In the event that the precision key generator 230 does not have the necessary Number of bursts received to it after triggering its counting cycle on its As a safety measure, it is provided that the detector 276 over the circle 274 is switched through in order to couple the color synchronous key signal to the precision key generator 230, whereby the counting cycle is ended and the precision color synchronous key signal is supplied. This ensures that the precision probe generator 230 always responds correctly to every input color sync signal

In order to ensure a picture index signal in the coding switch 126 that is exactly in phase with the Vertical sync signal of the input video signal, the output signal of the precision Synchronous signal separator 213 and an output signal of a Yertical synchronous detector 278 (FIG. 1 IB) NOR gate 279 (Fig.HD) coupled, which dss provides the desired Büdindexsignal.

The reference logic circuits 125Λ and 125B according to the block diagram of FIG. 8A receive various signals from the input circuits 93/1 and 93Ä soft to the horizontal and V? Rtikai synchronizing signals, the regenerated subcarrier and weitei £ corresponding signals are obtained, and generate a plurality of clock and timing control signals for the inventive device Furthermore, the computer control system 92 supplies control signals both for the logic circuit 125/4 and for the logic circuit 1.25, which are used to generate servo synchronizing signals. These signals regulate the functional phases of the disk drive units in the various operating modes, for example during recording, playback, transfer and other operations carried out by the device. The reference logic circuits are duplicated so that one such circuit is provided for the video input circuit 93/4 and another for the reference signal input circuit 935, the function of the reference logic circuits being somewhat different during the various operations of the device mentioned. Since the logic circuits 125/4 and 125β perform different functions, they receive different input signals, all of the available output signals not being used.

The mode of operation of the reference logic circuits is explained in more detail below with the aid of a block diagram according to FIG. 10A. A dashed line running horizontally approximately through the middle of this block diagram separates different functions. The upper part of the circuit is used only in recording, while the lower part of the circuit is used in recording, reproducing and other operations of the signal system. The upper part of the circuit is used to generate various phase-locked clock signals for recording processes using the regenerated subcarrier! The circuit also generates an asymmetrical PAL error identification signal with a frequency of H / 2 which, for the reasons mentioned above, is used to reverse the phase of the duty cycle signal in the analog-digital converter in successive horizontal lines. This PAL error flag signal is also available as the output signal of the reference logic circuit 125B for use in other parts of the signal system, primarily in the parts serving to process the playback signals. The circuit also generates a driver sync signal to control the servo control of the disk drive motors, which is a set of three pulses with a repetition frequency of 15 Hz, which is used several times together with the horizontal sync signal to control the servo control. Further timing control signals are generated by reference logic circuit 125B in a manner to be described in greater detail below

In the upper part of the circuit according to FIG. 1OA is the subcarrier signal (SC) either from the video input circuit 93Λ for the reference logic circuit 125/4 or from the reference signal input circuit 93B to the reference logic circuit 125β on a line 300 fed and fed to a phase comparison stage 302, the output signal on a line 303 in a summation node 304 is fed, the second input signal via a line 305 from a Integrator 365 is delivered. A digital precision color synchronous PheSiSädecad'iT 307 receives the digitized Vkk-odaten from the output of the analog digital £ over a line 308 and determines

whether the sample values are obtained with the correct phase of the color sync signal. This decoder generates a plus or minus error signal for the integrator 306 on a line 309, whereby the phase of the key clock signal is adjusted so that the video signal is always keyed correctly to a loop amplifier and filter stage 311, which is coupled to a voltage-controlled oscillator 312 via a line 313 Frequency of 6SC and is fed to a dividing by 6 counter 316 and a dividing by 2 counter 317, a PAL clock output signal with a frequency of 3 SC being generated on a line 318. The counter dividing by 6 supplies an output signal with a frequency of 1 SC on a line 319, which is fed into a counter 320 dividing by 2 and into the other input of the phase comparison stage 302. The output signal of the divide by 2 counter 320 into a signal with the frequency V2SC on a line 321 which is carried to a pulse shaper 322 in order to set and reset the divide by 2 counter 317 in every other line. Control takes place via a line 323 with a frequency of H / 2, this signal being supplied by a PAL error code generator 324, which will be explained in more detail below.

The operation of the upper part of the circuit is to generate a signal with the frequency 6 SC at the output of the voltage-controlled oscillator 312, which is regulated so precisely that the analog digi 3s talkonverter 95 keying performed at all times done with exactly the same phase of the burst signal This is taking into account the fact important that the phase of the sampled video signal ultimately determines the color produced by the device. The phase comparator 312, one input of which is via - The line 319 with the divided output signal of the voltage controlled oscillator 312 is applied, forms a phase-locked loop, which the phase of the output signal relatively accurately to the phase of the standing on line 300 video or reference subcarrier signal that is fed into the other input of the Phase comparison stage 302 is fed. There * shared The output of the voltage controlled oscillator 312 generates a signal through the phase locked loop with the frequency SC, which is generally within about 10 ° The digitized video output signal from the Aflalog'Digital converter 95 is, however, also over the line 308 is fed into the digital precision color synchronous phase detector 307, which is indicated by ss the precision color synchronous keying signal on a line 307 is activated to generate an error signal to produce that during the color sync interval of the video signal is produced. This error signal is integrated by the integrator 306 in order to produce a signal in the w Sümfnätiöflsknotefl 304 to be fed in produce. So that the voltage value at the output of the loop amplifier and filter stage 311, which controls the voltage controlled oscillator 312 so that changes in the sampling times of the es Video signals, which are represented by the color synchronous sample values supplied by the decoder 307, are corrected. The color synchronous sample values represent the same value «for all lines, if there is no change in the sampling times. By monitoring the sampled data occurring at the output of the analog-digital converter, it can be precisely determined whether the sampling values were obtained with the correct phase. In this way, the output of the voltage controlled oscillator on line 315, which is fed into the divide by 2 counter 317, provides a PAL clock signal of frequency 3 SC on line 318, by which the Aaalog digital converter 95 is so controlled keep the keying in phase. The digital precision color synchronous phase decoder 307 corrects errors which arise due to a temperature drift and the like and are of the order of magnitude of 5 ° to 10 °. In this regard, the phase of the video (or reference) subcarrier on line 300 is the basic definition for voltage controlled oscillator 312, with the precision correction on line 305 in reference logic circuit ί25Β increasing the phase by a few degrees, i.e. up to about 20 °, changes

In the lower part of the block diagram according to FIG. 10A, the PAL error code generator 324 generates a PAL error code signal with the frequency H / 2 for switching a switch 325 which sends pulses with the frequency '/ 2 SC into the set or reset input of the counter 317 which is divided by 2 which supplies the PAL clock signal on line 318. The PAL error flag signal changes state on each line, as explained below with reference to FIG. 11B. The PAL error flag signal is unbalanced so that the phase of the PAL clock signal at the frequency 3 SC is never reversed during the sync interval of the video signal, while it is reversed every other line during the active video signal phase. Essentially, this means that only the part of the line after the color sync signal is scanned with a clock signal, the phase of which is reversed in every second line, that is, it is an asymmetrical signal. As shown in FIG. HA, the PAL error flag generator 324 receives input signals from the video input circuit 93Λ or the reference signal input circuit 93B, which are an H drive signal on a line 326, a picture index pulse on a line 327 and a color sync error The color synchronous error code signal prevents the PAL error code generator from generating a PAL error code signal on the line 323 until the color sync signal has occurred because the sampling phase of the color sync signal for the puncture of the color synch * chron phase detector 307 in the upper part of the detector the F i g. 11A does not need to be changed. The PAL error flag generator also generates a transfer reset pulse at the frequency HIUi for the coding switch 126 on a line 324a, which is used in data transfer operations to generate a signal which is used in the encoder 96 to reset the synchronizing word · insert circuit

The H'driver signal and the picture index signal become fed into a driver servo synchronous generator 330 whose output via a line 332 to a Driver synchronous switch 331 is coupled. This driver sync switch 331 provides the basic Driver sync signals on line 334 for the disk drive units 73, and via a Control line 333 from the computer control system 92

will. DIE synchronizing signals are for all the operations necessary in which the information between a disk stack 75 and the signal system is transferred, Pas eomputerregelsystem 92 determines whether a Aufeeichnungs- or a reproducing operation is desired, the synchronization information is located on the leading to the Scheibenantriebseinhetten lines 334 in Form of a MuMpIex synchronous signal, which contains a set of three consecutive wide pulses with a rate of 15 Hz for indexing the first recorded or reproduced field as well as horizontal synchronizing pulses (with H-rate) and is used to control the spindle servo motor to control the servo drive and for the generation of control signals during playback operations by the reference clock generator, color image-related synchronous signals are also generated ng 327 and divides it by 2 to generate a color image signal at 15 Hz. This color image signal is sent via a line 329 to the disk drive units 73 and to the reference clock generator 98

A special circuit for performing the operations in the block diagram of FIG. 1OA is shown in FIGS. 12A to 12D, which together show a circuit diagram of the reference logic circuits. Since the operation of the circuit shown in these figures generally proceeds in the manner explained above with reference to FIG. 10A, this circuit is not described in detail. With regard to the in the upper part of FIG. Note however 12A shown, digital precision color burst phase detector 307 ki that the digitized video information in the form of 8 bits from the output of the analog-Dtgitalkonverters 95 catenaries 308 is entered which of arithmetic logic stages

335 are coupled, in turn with shift registers

336 are coupled. These shift registers 336 are clocked by a logic generally designated 337, which are activated by the precision color sync key signal on line 307Λ and, together with the arithmetic logic stages 335, the necessary to determine the sign of the phase of the digitized color sync signal on line 309 Carry out arithmetic steps, the error of sample values is determined iladurcfc that the quadrature component of the sample values is examined, which is equal to zero if the sample values were obtained in the correct phase of the subcarrier signal. In particular, the quadrature component is proportional to the function Xl- »/ 2 '(ΧΪ + Χ3), where sample values Xl, X 2 and X3 are 120 ° apart. The logic 337 executes the sequence which activates the arithmetic stages 336 to carry out the arithmetic calculation, which generates either a plus or a minus signal on the line 309, which indicates an error in the phase of the actual sample values.

The circuit of FIG. 12A further includes a circuit 324 for generating the PAL error flag signal on the line 323, the H drive signal being inverted by an inverter 342 and via a line 338 being fed to the clock input of a flip-flop 339 which is on A signal divided by 2 is generated on an output line 340. This signal is fed into the input of a second flip-flop 341 which is clocked by the color synchronous error flag signal on line 328. The line 340 and the output line 344 of the flip-flop 341 lead to a NAND gate 343. The operation of the PAL error code generator 324 is explained below with reference to the signal diagrams according to FIG. 10B. FIG. 10B (1) shows the H driver signal (Line 326), Fig. 10B (2) the signal on line 340, Fig. 10B (3) the signal on line 344, Fig. 10B (4) the color sync error flag signal on line 328 and Fig. 10B ( 5) the initial signa! of the NAND gate on line 345. The PAL error flag signal on line 323 is the inverted signal on line 345 due to the action of inverter 346. The PAL error flag signal occurs at a frequency of H / 2 , FIG. 10B (5) shows that this is an unbalanced signal because the output signal of flip-flop 341 appearing on line 344 and fed into NAND gate 343 is delayed with respect to the signal of first flip-flop 339 that the flip-flop 341 is not clocked by the H drive signal, but by the color sync error flag signal.

16 sheets of drawings

Claims (7)

868 claims; 1. Arrangement for generating a rectangular gen output signal for use in a device for changing the phase line by line of a video signal that has a horizontal blanking interval and in each horizontal blanking interval has a color synchronization signal, for the duration of every te second video line a switching of the output signal from a first or a second level takes place at the respective other level and wherein the output signal during the color sync signal is always on the first level, indicated by a circuit (339) for generating a first symmetrical square wave signal with a period of two video lines in such a way that the level of this w * n symmetrical square-wave signal is in consecutive: video lines at the beginning. of the horizontal blanking interval changes by a circuit (341) for generating a second symmetrical square-wave signal with a period of two video lines such that the second symmetrical square wave signal synchronous with the first symmetrical square wave signal] but so far delayed to this is that the level of this second square wave signal does not change until immediately after the occurrence of the burst signal changes, and by a combination circuit (342) for combining the first and second square wave signals for the purpose of generating the rectangular output signal in such a way that this output signal is then when the first and second square wave signals are at the same predetermined level at which second level and is otherwise at the first level 2. Arrangement according to claim 1, characterized by a responsive to the occurrence of the color synchro signal circuit (328) for activating the circuit (341) generating the second symmetrical square-wave signal in the sense of Generation of the level change when the color sync signal occurs. 3. Arrangement according to claim 1 and / or 2, characterized in that the combination circuit (342) has a logic circuit (343) at least one input (340) for each of the two symmetrical square-wave signals, an output (344) for each of the two square-wave signals and an output (348) at which the square-wave Output signal occurs, has. 4. Arrangement according to one of claims 1 to 3, characterized in that the logic gate scarf Hing (343) has an electronic NAND gate. 5. Arrangement according to one of claims 1 to 4, characterized by a controllable clock gen rator (317) for generating a key clock signal with either a first or a second phase in opposite directions and through a coupling circuit (325) for coupling the square-wave output signal to the clock generator (317) for controlling the Phase of the key clock signal, the key clock signal having the first phase if the square-wave Output signal is at the first level and at other times the second phase in opposite directions 6, arrangement according to one of claims 1 to 5, characterized by an on / ^. dje, clock signals responsive circuit (95) J? wi | ün} conversion consecutive video line ": 'of the video signal between analog and digital signal forms and by a circuit (318) for coupling the Duty cycle signal for converting the video signal between the waveforms, 7. Arrangement according to one of claims 1 to 6, characterized in that the conversion circuit (95) is an analog-digital converter