JPH0233131A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0233131A JPH0233131A JP63182990A JP18299088A JPH0233131A JP H0233131 A JPH0233131 A JP H0233131A JP 63182990 A JP63182990 A JP 63182990A JP 18299088 A JP18299088 A JP 18299088A JP H0233131 A JPH0233131 A JP H0233131A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor
- insulating
- thin film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000003990 capacitor Substances 0.000 claims abstract description 24
- 239000011159 matrix material Substances 0.000 claims abstract description 17
- 239000010408 film Substances 0.000 claims description 104
- 239000010409 thin film Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims 3
- 238000001259 photo etching Methods 0.000 abstract description 11
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 4
- 238000003860 storage Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 229910004481 Ta2O3 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はＭｉｓ（金属−絶縁物一半導体）トランジスタ
アレイを用いたデイスプレィのためのアクティブマトリ
クス基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an active matrix substrate for a display using a Mis (metal-insulator-semiconductor) transistor array.
（従来の技術）
従来のアクティブマトリクスを用いたデイスプレィパネ
ルの１セル分の回路図を第５図に示す。(Prior Art) FIG. 5 shows a circuit diagram of one cell of a display panel using a conventional active matrix.
同図において、走査線６５は薄膜トランジスタ（ＴＰＴ
）５２のゲートに接続されており、ＴＰＴ５２がオンさ
れると信号線６１の信号は、電荷保持容量５３、信号線
６１と走査線６５との交差部分に設けられた電荷保持容
量５５、および信号線６１とＧＮＤ線との交差部分に設
けられた電荷保持容量５６に電荷として蓄積される。信
号線６１からの信号は、再びデータが書込まれるまで、
この容Ｊｉｔ５３，５５．５６により保持され、同時に
液晶５４を駆動する。ここでＶｃは共通電極信号である
。In the figure, the scanning line 65 is a thin film transistor (TPT).
) 52, and when the TPT 52 is turned on, the signal on the signal line 61 is connected to the charge storage capacitor 53, the charge storage capacitor 55 provided at the intersection of the signal line 61 and the scanning line 65, and the signal The charge is stored as a charge in the charge storage capacitor 56 provided at the intersection of the line 61 and the GND line. The signal from the signal line 61 remains unchanged until data is written again.
This capacity is held by Jits 53, 55, and 56, and drives the liquid crystal 54 at the same time. Here, Vc is a common electrode signal.
第６図は従来のアクティブマトリクス基板の１セル分の
構造を示した平面図であり、第７図は第６図のＣ−Ｄ線
断面図である。前記ＴＦＴ５２と電荷保持容量５３の構
造は特開昭６２−１４８９２９号公報に記載されている
。FIG. 6 is a plan view showing the structure of one cell of a conventional active matrix substrate, and FIG. 7 is a sectional view taken along the line CD in FIG. 6. The structure of the TFT 52 and the charge storage capacitor 53 is described in Japanese Patent Laid-Open No. 148929/1983.
ＴＰＴ５２は、基板１上にゲート電極８を形成した後ゲ
ート絶縁膜７４を全面に形成し、さらにトランジスタ５
２の能動領域となる半導体層６３を形成する逆スタガ構
造であり、電荷保持容量５３は、基板１上に形成された
共通電極９の上方に、絶縁膜７４を介して画素電極６４
を配置した構造である。In the TPT 52, after forming the gate electrode 8 on the substrate 1, a gate insulating film 74 is formed on the entire surface, and then the transistor 5 is formed.
The charge storage capacitor 53 is connected to the pixel electrode 64 through an insulating film 74 above the common electrode 9 formed on the substrate 1.
It is a structure in which
この従来構造の作成プロセスでは、ゲート電極８及び共
通電極９を形成するためのホト・エツチング、半導体層
６３を形成するためのホト・エツチング、および画素電
極６４及び信号線６１を形成するためのホト・エツチン
グと、＝１３回のホト・エツチングでＴＰＴ５２及び電
荷保持容量５３が形成される。This conventional structure creation process includes photo-etching to form the gate electrode 8 and common electrode 9, photo-etching to form the semiconductor layer 63, and photo-etching to form the pixel electrode 64 and signal line 61. - TPT 52 and charge storage capacitor 53 are formed by etching and photo-etching 13 times.
また、実際にこの基板をアクティブマトリクス基板とし
て用いる場合は、絶縁膜７４の下に形成されたゲート電
極８及び共通電極９を外部配線と電気的に接続するため
に、絶縁膜７４にコンタクトホールを開けなければなら
ず、計４回のホト・エツチング工程が必要となる。In addition, when actually using this substrate as an active matrix substrate, a contact hole is formed in the insulating film 74 in order to electrically connect the gate electrode 8 and common electrode 9 formed under the insulating film 74 to external wiring. It must be opened, requiring a total of four photo-etching steps.
（発明が解決しようとする課題）
上記した従来技術は、ホト・エツチング工程が多いため
に製造工程が複ＹＬであり、これが歩留りを向」ニさせ
るうえでの大きな障害となっていた。(Problems to be Solved by the Invention) The above-mentioned conventional technology requires multiple photo-etching steps, so the manufacturing process is multi-YL, which is a major obstacle in improving the yield.
本発明は、上記した問題を解決し、ホト・エツチング工
程数を減じ、歩留りを向ｌｒ、させることが可能な半導
体装置およびその製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can solve the above problems, reduce the number of photo-etching steps, and improve yield.
（課題を解決するための手段）
上記した問題点を解決するために、本発明は、絶縁性基
板の主表面に互いに近接して配置された薄膜半導体素子
およびコンデンサ部からなる半導体装置において、
絶縁性基板の主表面に透明導電膜を形成し、その後、該
透明導電膜をパターニングして前記薄膜半導体素子の信
号線および前記コンデンサ部の共通電極を形成し、その
後、前記絶縁性基板、信号線、および下側電極の表面に
、半導体薄膜、絶縁膜、および導電膜を積層し、その後
、前記半導体薄膜、絶縁膜、および導電膜を同形状に工
・ソチングして前記薄膜半導体素子および透明電極コン
デンサを形成するようにした点に特徴がある。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a semiconductor device including a thin film semiconductor element and a capacitor portion disposed close to each other on the main surface of an insulating substrate. A transparent conductive film is formed on the main surface of the insulating substrate, and then the transparent conductive film is patterned to form the signal line of the thin film semiconductor element and the common electrode of the capacitor section, and then the insulating substrate and the signal line are formed. A semiconductor thin film, an insulating film, and a conductive film are laminated on the surfaces of the , and lower electrode, and then the semiconductor thin film, the insulating film, and the conductive film are machined and sown into the same shape to form the thin film semiconductor element and the transparent electrode. The feature is that it forms a capacitor.
（作用）
このような構成によれば、ホト・エツチング工程が、■
薄膜半導体素子の信号線および前記コンデンサ部の共通
電極の形成するための工・ノチング、■前記半導体薄膜
、絶縁膜、および導電膜を同形状に形成するためのエツ
チング、の２回となる。(Function) According to such a configuration, the photo-etching process can be performed as follows.
There are two steps: etching and notching to form the signal line of the thin film semiconductor element and the common electrode of the capacitor section, and (2) etching to form the semiconductor thin film, insulating film, and conductive film into the same shape.
さらに、上記した構成によれば、薄膜半導体素子のゲー
ト電極およびコンデンサ部の共通電極が表面に露出した
構造となるため、これらを外部配線と接続させるスルー
ホールを開孔するためのホト・エツチング工程を省略す
ることができるようになり、製造歩留まりを向上させる
ことができると共に、製造コストをも削減することがで
きるようになる。Furthermore, according to the above structure, since the gate electrode of the thin film semiconductor element and the common electrode of the capacitor part are exposed on the surface, a photo-etching process is required to open a through hole to connect these to external wiring. It becomes possible to omit this, and it becomes possible to improve the manufacturing yield and also to reduce the manufacturing cost.
（実施例） 以ドに、本発明に実施例を図面を用いて説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.
第３図は本発明を適用したアクティブマトリックス基板
を構成するＴＦＴＩセル分の構造を示した平面図、第２
図はその回路図であり、前記と同一の符号は同一または
同等部分を表わしている。FIG. 3 is a plan view showing the structure of TFTI cells constituting an active matrix substrate to which the present invention is applied;
The figure is a circuit diagram thereof, and the same reference numerals as above represent the same or equivalent parts.
ＴＳ２図において、なお、第２図に示した回路のｉｌＩ
、本釣な動作、たとえばデータの書込み方法、および電
荷の保持方法等は前記第５図に関して説明した従来技術
と同じである。In the TS2 diagram, it should be noted that the ilI of the circuit shown in FIG.
The main operations, such as the data writing method and the charge holding method, are the same as those of the prior art explained with reference to FIG.
第１図は第３図のＡ−Ｂ線での断面図である。FIG. 1 is a sectional view taken along line A-B in FIG. 3.
同図において、透明絶縁性基板１の表面には信号線６１
および画素電極６４が透明導？１！膜によって形成され
ている。In the figure, a signal line 61 is provided on the surface of the transparent insulating substrate 1.
Is the pixel electrode 64 a transparent conductor? 1! It is formed by a membrane.
さらに、透明絶縁性基板１の表面に接し、かつ前記信号
線６１および画素電極６４の一部を覆う領域、および画
素電極６４の表面には、それぞれＴＰＴのチャネルとな
る半導体膜４およびＴｓ ４！ｔの保持容量となる半導
体膜５が形成されている。Furthermore, a semiconductor film 4 and Ts 4!, which will become a channel of TPT, are formed in a region that is in contact with the surface of the transparent insulating substrate 1 and covers part of the signal line 61 and the pixel electrode 64, and on the surface of the pixel electrode 64, respectively. A semiconductor film 5 serving as a storage capacitor of t is formed.
さらに、半導体ＩＩ！４および半導体膜５の表面には、
それぞれＴＰＴのゲート絶縁膜６および電荷の保持容量
となる絶縁膜７が、それぞれ前記半導体膜４および半導
体膜５と同形状で形成されている。Furthermore, Semiconductor II! 4 and the surface of the semiconductor film 5,
A gate insulating film 6 of TPT and an insulating film 7 serving as a charge storage capacitor are formed in the same shape as the semiconductor film 4 and the semiconductor film 5, respectively.
さらに、絶縁膜６および絶縁膜７の表面には、それぞれ
ゲート電極８および共通電極９が、それぞれ前記ゲート
絶縁膜６および絶縁膜７と同形状で形成されている。Further, a gate electrode 8 and a common electrode 9 are formed on the surfaces of the insulating film 6 and the insulating film 7, respectively, in the same shape as the gate insulating film 6 and the insulating film 7, respectively.
また、前記透明絶縁性基板１の対向部分には透明対向Ｕ
板１１が設置されており、その表面には対向電極１０が
形成されている。Further, a transparent opposing U is provided on the opposing portion of the transparent insulating substrate 1.
A plate 11 is installed, and a counter electrode 10 is formed on the surface thereof.
このような構成を有する本実施例では、共通電極９と画
素電極６４とによって、第２図に示された電６ｆ保持容
ｆｆｌ （Ｃｓｒｃ ） ５３が形成される。In this embodiment having such a configuration, the common electrode 9 and the pixel electrode 64 form the cell 6f holding capacity ffl (Csrc) 53 shown in FIG.
第４図は第１図に示すアクティブマトリクスセルの製造
プロセスを示した断面図であり、第１図と同一の符号は
同一または同等部分を表わしている。透明基板１として
は、ガラスもしくはパイレックス、コーニングのような
絶縁性の高融点ガラスを用いる。他の絶縁性の小さな透
明基板を用いる場合は、基板１表面に５Ｉ０２膜等の透
明絶縁性膜をＣＶＤ法やスパッタ法等により堆積した後
に用いる。FIG. 4 is a sectional view showing the manufacturing process of the active matrix cell shown in FIG. 1, and the same reference numerals as in FIG. 1 represent the same or equivalent parts. As the transparent substrate 1, glass or insulating high melting point glass such as Pyrex or Corning is used. When using another transparent substrate with small insulating properties, it is used after depositing a transparent insulating film such as a 5I02 film on the surface of the substrate 1 by CVD, sputtering, or the like.
まず、透明基板１上に透明導電膜である、不純物がドー
プされた５ｉｌｆｉ４２０を減圧ＣＶＤ法やプラズマＣ
ＶＤ等により形成する［同図（ａ）］。First, 5ilfi420, which is a transparent conductive film doped with impurities, is deposited on a transparent substrate 1 using a low pressure CVD method or a plasma C.
It is formed by VD or the like [Figure (a)].
次に、該Ｓｌ膜４２０を必要な形状にホト中エツチング
して信号線６１及び画素電極６４を形成する［同図（ｂ
）］。このとき、透明導電膜となるＳｉ膜４２０は、光
が透過するように３００ｎｍ以下の膜厚で堆積する。ま
た、該Ｓ１膜を直接゛基板１に被若する代わりに、従来
から行われているように、金やアルミニウム等の金属膜
を５０ｎｍ以下程度の光を透過するぐらいの膜厚で透明
基板１．トに薄く破着し、さらにその表面に不純物がド
ープされたＳ１膜を３００ ｎ ｒｎ以下の膜厚で形成
したショットキー接合を有する膜を形成するようにして
もよイ。また、ＩＴＯ（Ｉｎｄｉｕｍ Ｔａｎ０ｘｉｄ
） 、あるいは酸化スズ等の透明導電膜に不純物をド
ープした半導体薄膜秀の多層膜を用いてもよい。Next, the Sl film 420 is photo-etched into a required shape to form a signal line 61 and a pixel electrode 64 [FIG.
)]. At this time, the Si film 420, which becomes a transparent conductive film, is deposited to a thickness of 300 nm or less so that light can pass through. In addition, instead of directly covering the S1 film on the substrate 1, it is possible to coat the transparent substrate with a metal film such as gold or aluminum with a film thickness that transmits light of about 50 nm or less, as has been done in the past. ．． It is also possible to form a film having a Schottky junction, in which the S1 film is thinly bonded to the surface and is doped with impurities to a thickness of 300 nrn or less. In addition, ITO (Indium Tan0xid
), or a multilayer film such as a semiconductor thin film in which a transparent conductive film such as tin oxide is doped with an impurity may be used.
次に、チャネル層となる半導体膜（Ｓｌ等）４３０をプ
ラズマＣＶＤ法や減圧ＣＶＤ法等のＣＶＤ法、スパッタ
法等により形成する。さらに、半導体膜４３０上に、ゲ
ート絶縁膜及び電荷保持容量の誘電体となる絶縁膜（Ｓ
１０□膜、ＳＩＮ膜、Ｔａ２Ｏ３膜等）４４０をプラズ
マＣＶＤ法や常圧ＣＶＤ法等のＣＶＤ法、あるいはスパ
ッタ法等により形成する。ここで、前記絶縁膜４４０は
半導体膜４３０を０２プラズマ雰囲気等で表面酸化する
ことにより形成してもよい。また、絶縁＠４４０は半導
体酸化膜上にＴａ２Ｏ３膜等の絶縁膜を積層した多層膜
でもよい。Next, a semiconductor film (Sl or the like) 430 that will become a channel layer is formed by a CVD method such as a plasma CVD method or a low pressure CVD method, a sputtering method, or the like. Further, on the semiconductor film 430, an insulating film (S
10□ film, SIN film, Ta2O3 film, etc.) 440 is formed by a CVD method such as a plasma CVD method or an atmospheric pressure CVD method, or a sputtering method. Here, the insulating film 440 may be formed by surface oxidizing the semiconductor film 430 in an 02 plasma atmosphere or the like. Further, the insulation@440 may be a multilayer film in which an insulating film such as a Ta2O3 film is laminated on a semiconductor oxide film.
その後、前記絶縁膜４４０上に、ゲート電極、走査線配
線となる導電膜（Ａｆｆｉ 、 Ｃｒ、 ｄｏｐｃｄ
ｓｉ 。After that, a conductive film (Affi, Cr, DOPCD) that will become a gate electrode and a scanning line wiring is formed on the insulating film 440.
si.
Ｉ Ｔ Ｏ、Ｓ ｎ ０２膜等）４５０をさらに堆積す
る［同図（Ｃ）］。ITO, Sn 02 film, etc.) 450 is further deposited [FIG. 4(C)].
その後、導電膜４５０をレジストを用いて必要な形状に
マスキングし、該導電膜４５０がＡＩ膜であればＮａ
ＤＨ，Ｓｌ膜であればＨＮＯ３／ＨＦの混合液等の適宜
の薬液によってウェットエツチングし、ゲート電極８及
び電荷保持容量の共通電極９を形成する。更に該ゲート
電極８および共通電極９をマスクにして自己整合的に絶
縁１１％４４０をウェットエツチングし、ゲート絶縁膜
６及び電６ｆ保持容量の誘電体７を形成する。このとき
、絶縁膜４４０が８１０２膜であれば、エツチング液と
してＨＦを用いる。更にゲート絶縁膜６および誘電体７
をマスクとして自己整合的に゛ヒ導体膜４３０をエツチ
ングし、チャネル層４および半導体層５を形成する。こ
のとき、半導体膜が５ｌｌｌＡであれば、エツチング液
としてＨＮＯ３／ＨＦの混合液を用いる。After that, the conductive film 450 is masked into a required shape using a resist, and if the conductive film 450 is an AI film, Na
If it is a DH or Sl film, wet etching is performed using an appropriate chemical solution such as a mixed solution of HNO3/HF to form the gate electrode 8 and the common electrode 9 of the charge storage capacitor. Furthermore, using the gate electrode 8 and the common electrode 9 as masks, the insulating 11% 440 is wet-etched in a self-aligned manner to form the gate insulating film 6 and the dielectric 7 of the capacitor 6f. At this time, if the insulating film 440 is an 8102 film, HF is used as the etching solution. Furthermore, a gate insulating film 6 and a dielectric material 7
The conductor film 430 is etched in a self-aligned manner using as a mask to form a channel layer 4 and a semiconductor layer 5. At this time, if the semiconductor film is 511A, a mixed solution of HNO3/HF is used as the etching solution.
ここで、このプロセスに用いる半導体膜４３０は非晶質
シリコン、多結晶シリコン等の真性半導体ならば何でも
よいが、特に、低温（約６００℃以下）で形成できる減
圧ＣＶＤ法で堆積後、レーザーアニールした多結晶シリ
コン膜が特に良好である。Here, the semiconductor film 430 used in this process may be any intrinsic semiconductor such as amorphous silicon or polycrystalline silicon, but in particular, after being deposited by a low-pressure CVD method that can be formed at a low temperature (approximately 600° C. or lower), laser annealing is performed. A polycrystalline silicon film made of polycrystalline silicon is particularly good.
また、本実施例においては、以下に説明する応用技術を
適用することができる。Further, in this embodiment, the applied technology described below can be applied.
（１）トランジスタ部のオフ電流を保障するために、ト
ランジスタ部の上側および下側の少なくとも一方、また
は、対向基板のトランジスタの投影領域に遮光膜を設け
る。(1) In order to ensure the off-state current of the transistor section, a light shielding film is provided on at least one of the upper and lower sides of the transistor section or the projection area of the transistor on the opposing substrate.
（２）アクティブマトリクス基板の表面を流れるリーク
電流を防止するために、トランジスタ及び電荷保持容量
形成後、この上に絶縁膜を堆積する。(2) In order to prevent leakage current flowing on the surface of the active matrix substrate, after forming the transistor and the charge storage capacitor, an insulating film is deposited thereon.
（３）アクティブマトリクス基板上に、アクティブマト
リクス用の駆動回路、即ちシフトレジスタやサンプルホ
ールド回路及び走査回路を形成する。(3) Forming an active matrix drive circuit, ie, a shift register, a sample hold circuit, and a scanning circuit, on the active matrix substrate.
なお、−１−記した実施例においては、ＴＰＴのゲート
電極および電荷保持容量の共通電極となる導電膜４５０
のみをマスクを用いてエツチングし、その下部に形成さ
れている絶縁膜、半導体膜は自己整合的に順番にエツチ
ングするものとして説明したが、これはサイドエツチン
グを防ぐためのものである。In the embodiment described in -1-, the conductive film 450 serves as the gate electrode of the TPT and the common electrode of the charge storage capacitor.
The explanation has been made assuming that only the etching layer is etched using a mask, and the insulating film and semiconductor film formed below are etched in order in a self-aligned manner, but this is to prevent side etching.
それ故に、サイドエツチングが起こりにくいドライエツ
チングあるいはイオンミリング等の適宜の手段を用いて
エツチングするのであれば、前記マスクを用いて全ての
膜をエツチングするようにしても良い。なお、この場合
も、エツチングしようとする膜の材質に合わせて反応ガ
スを選択する必要がある。Therefore, if etching is performed using an appropriate method such as dry etching or ion milling that is less likely to cause side etching, all the films may be etched using the mask. In this case as well, it is necessary to select the reaction gas according to the material of the film to be etched.
また、上記した実施例においては、基板１を透明基板で
あるものとして説明したが、前記アクティブマトリック
ス基板を反射型の液晶表示装置に用いるのであれば、透
明基板の代わりに、表面が鏡面状であるＳｌ基板等を用
いても良い。Further, in the above embodiment, the substrate 1 was described as being a transparent substrate, but if the active matrix substrate is used in a reflective liquid crystal display device, a mirror-like surface may be used instead of a transparent substrate. A certain Sl substrate or the like may also be used.
（発明の効果）
以−１ユの説明から明らかなように、本発明によれば、
ホト・エツチング工程を減らして製造工程を簡略化する
ことができるので、歩留まりを向」ニさせることができ
ると共に、製造コストをも削減することができるように
なる。(Effects of the Invention) As is clear from the explanation in Part 1, according to the present invention,
Since the manufacturing process can be simplified by reducing the number of photo-etching steps, the yield can be improved and manufacturing costs can also be reduced.
第１図は本発明を適用したアクティブマトリックス型液
晶表示装置の断面図、第２図はアクティブマトリックス
基板の１セル分の回路図、第３図は第１図の平面図、第
４図は本発明の製造工程を示した断面図、第５図は従来
のアクティブマトリックス基板の回路図、第６図は従来
のアクティブマトリックス基板の１セル分の平面図、第
７図は第６図のＣ−Ｄ線での断面図である。FIG. 1 is a cross-sectional view of an active matrix liquid crystal display device to which the present invention is applied, FIG. 2 is a circuit diagram of one cell of an active matrix substrate, FIG. 3 is a plan view of FIG. 1, and FIG. 5 is a circuit diagram of a conventional active matrix substrate, FIG. 6 is a plan view of one cell of a conventional active matrix substrate, and FIG. 7 is a cross-sectional view showing the manufacturing process of the invention. It is a sectional view taken along the D line.
Claims (5)
れた第１の透明導電膜と、 絶縁性基板の主表面に、第１の透明導電膜との間に予定
の間隙をもつように配置された第２の透明導電膜と、 絶縁性基板の主表面に、前記第１の透明導電膜および第
２の透明導電膜の一部、ならびに前記間隙を覆うように
形成された第１の半導体薄膜と、前記第２の透明導電膜
の表面に、前記第１の半導体薄膜と同時に形成された第
２の半導体薄膜と、前記第１の半導体薄膜上に、これと
同形状で形成された第１の絶縁膜と、 第２の半導体薄膜上に、これと同形状で、かつ前記第１
の絶縁膜と同時に形成された第２の絶縁膜と、 前記第１の絶縁膜上に、これと同形状で形成された第１
の導電膜と、 第２の絶縁膜上に、これと同形状で、かつ前記第１の導
電膜と同時に形成された第２の導電膜とを具備したこと
を特徴とする半導体装置。(1) An insulating substrate, a first transparent conductive film formed in a matrix on the main surface of the insulating substrate, and a first transparent conductive film on the main surface of the insulating substrate. a second transparent conductive film arranged with a predetermined gap; and a part of the first transparent conductive film and the second transparent conductive film, and a part of the second transparent conductive film on the main surface of the insulating substrate so as to cover the gap. a first semiconductor thin film formed on the surface of the first semiconductor thin film, a second semiconductor thin film formed on the surface of the second transparent conductive film at the same time as the first semiconductor thin film, and a second semiconductor thin film formed on the first semiconductor thin film; a first insulating film formed in the same shape as the first insulating film, and a second semiconductor thin film formed in the same shape as the first insulating film;
a second insulating film formed at the same time as the insulating film; and a first insulating film formed in the same shape on the first insulating film.
A semiconductor device comprising: a conductive film; and a second conductive film formed on a second insulating film, having the same shape as the first conductive film and at the same time as the first conductive film.
されていることを特徴とする特許請求の範囲第１項記載
の半導体装置。(2) The semiconductor device according to claim 1, wherein a transparent insulating film is adhered to the main surface of the insulating substrate.
許請求の範囲第１項または第２項記載の半導体装置。(3) The semiconductor device according to claim 1 or 2, wherein the insulating substrate is transparent.
クス状に配置して形成された薄膜半導体素子と、該薄膜
半導体素子に近接して配置され、共通電極と画素電極と
によって形成される透明電極コンデンサ部とを有する半
導体装置の製造方法において、 絶縁性基板の主表面に透明導電膜を形成し、その後、該
透明導電膜をパターニングして前記薄膜半導体素子の信
号線および前記コンデンサの画素電極を形成する工程と
、 前記絶縁性基板、信号線、および画素電極の表面に半導
体薄膜を形成する工程と、 前記半導体薄膜の表面に絶縁膜を形成する工程と、 前記絶縁膜の表面に導電膜を形成する工程と、前記半導
体薄膜、絶縁膜、および導電膜を同形状にエッチングし
て、前記薄膜半導体素子および透明電極コンデンサを形
成する工程とからなることを特徴とする半導体装置の製
造方法。(4) An insulating substrate, a thin film semiconductor element arranged in a matrix on the main surface of the insulating substrate, and a common electrode and a pixel electrode arranged close to the thin film semiconductor element. In the method of manufacturing a semiconductor device having a transparent electrode capacitor section, a transparent conductive film is formed on the main surface of an insulating substrate, and then the transparent conductive film is patterned to form a signal line of the thin film semiconductor element and a signal line of the capacitor. forming a pixel electrode; forming a semiconductor thin film on the surfaces of the insulating substrate, the signal line, and the pixel electrode; forming an insulating film on the surface of the semiconductor thin film; Manufacturing a semiconductor device comprising the steps of forming a conductive film and etching the semiconductor thin film, insulating film, and conductive film into the same shape to form the thin film semiconductor element and transparent electrode capacitor. Method.
にエッチングする工程は、 前記導電膜をパターニングして、前記薄膜半導体素子の
ゲート電極および前記コンデンサ部の共通電極を形成す
る工程と、 前記ゲート電極および共通電極をマスクとして前記絶縁
膜を自己整合的にパターニングし、前記薄膜半導体素子
のゲート絶縁膜および前記コンデンサ部の第１の誘電体
膜を形成する工程と、前記ゲート絶縁膜および第１の誘
電体膜をマスクとして前記半導体薄膜を自己整合的にパ
ターニングし、前記薄膜半導体素子の能動領域および前
記コンデンサ部の第２の誘電体膜を形成する工程とから
なることを特徴とする特許請求の範囲第４項記載の半導
体装置の製造方法。(5) The step of etching the semiconductor thin film, the insulating film, and the conductive film into the same shape includes patterning the conductive film to form a gate electrode of the thin film semiconductor element and a common electrode of the capacitor section; patterning the insulating film in a self-aligned manner using the gate electrode and the common electrode as masks to form a gate insulating film of the thin film semiconductor element and a first dielectric film of the capacitor section; The method comprises the step of patterning the semiconductor thin film in a self-aligned manner using the first dielectric film as a mask to form a second dielectric film of the active region of the thin film semiconductor element and the capacitor section. A method for manufacturing a semiconductor device according to claim 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18299088A JP2628072B2 (en) | 1988-07-22 | 1988-07-22 | Liquid crystal display device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18299088A JP2628072B2 (en) | 1988-07-22 | 1988-07-22 | Liquid crystal display device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0233131A true JPH0233131A (en) | 1990-02-02 |
| JP2628072B2 JP2628072B2 (en) | 1997-07-09 |
Family
ID=16127827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18299088A Expired - Fee Related JP2628072B2 (en) | 1988-07-22 | 1988-07-22 | Liquid crystal display device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2628072B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06347821A (en) * | 1990-05-15 | 1994-12-22 | Centre Natl Etud Telecommun (Ptt) | Manufacture of display screen and display screen manufactured by method thereof |
| WO2004110105A1 (en) * | 2003-06-06 | 2004-12-16 | Pioneer Corporation | Organic semiconductor device and its manufacturing method |
| NL1012470C2 (en) * | 1998-07-24 | 2005-02-07 | Nec Lcd Technologies | Liquid crystal display device of the active matrix type. |
| US7381598B2 (en) | 1993-08-12 | 2008-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61183622A (en) * | 1985-02-08 | 1986-08-16 | Seiko Instr & Electronics Ltd | Thin film transistor device and its manufacture |
| JPS61243613A (en) * | 1985-04-20 | 1986-10-29 | コニカ株式会社 | Formation of transparent conducting layer |
| JPS63169616A (en) * | 1987-01-07 | 1988-07-13 | Fujitsu Ltd | Thin film transistor matrix for driving liquid crystal |
-
1988
- 1988-07-22 JP JP18299088A patent/JP2628072B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61183622A (en) * | 1985-02-08 | 1986-08-16 | Seiko Instr & Electronics Ltd | Thin film transistor device and its manufacture |
| JPS61243613A (en) * | 1985-04-20 | 1986-10-29 | コニカ株式会社 | Formation of transparent conducting layer |
| JPS63169616A (en) * | 1987-01-07 | 1988-07-13 | Fujitsu Ltd | Thin film transistor matrix for driving liquid crystal |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06347821A (en) * | 1990-05-15 | 1994-12-22 | Centre Natl Etud Telecommun (Ptt) | Manufacture of display screen and display screen manufactured by method thereof |
| US7381598B2 (en) | 1993-08-12 | 2008-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| NL1012470C2 (en) * | 1998-07-24 | 2005-02-07 | Nec Lcd Technologies | Liquid crystal display device of the active matrix type. |
| WO2004110105A1 (en) * | 2003-06-06 | 2004-12-16 | Pioneer Corporation | Organic semiconductor device and its manufacturing method |
| JPWO2004110105A1 (en) * | 2003-06-06 | 2006-07-20 | パイオニア株式会社 | Organic semiconductor device and manufacturing method thereof |
| US7776645B2 (en) | 2003-06-06 | 2010-08-17 | Pioneer Corporation | Organic semiconductor device and its manufacturing method |
| JP4566910B2 (en) * | 2003-06-06 | 2010-10-20 | パイオニア株式会社 | Organic semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2628072B2 (en) | 1997-07-09 |
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