JPH02290021A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02290021A JPH02290021A JP2090488A JP9048890A JPH02290021A JP H02290021 A JPH02290021 A JP H02290021A JP 2090488 A JP2090488 A JP 2090488A JP 9048890 A JP9048890 A JP 9048890A JP H02290021 A JPH02290021 A JP H02290021A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- lacquer layer
- gas mixture
- plasma
- organic lacquer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000004922 lacquer Substances 0.000 claims abstract description 35
- 239000000203 mixture Substances 0.000 claims abstract description 23
- 239000007789 gas Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 12
- 150000002927 oxygen compounds Chemical class 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 15
- 238000005530 etching Methods 0.000 description 12
- 239000002184 metal Substances 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 150000002366 halogen compounds Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
- G03F7/427—Stripping or agents therefor using plasma means only
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はＣＰ．と酸素化合物とを含む気体混合物中に形
成されるプラズマの成分に有機ラッカー層を接触させる
ことによって、基板上に局部的に存在する有機ラッカー
層をエッチングするようになした半導体装置の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to CP. A method for manufacturing a semiconductor device in which an organic lacquer layer locally present on a substrate is etched by contacting the organic lacquer layer with a component of a plasma formed in a gas mixture containing an oxygen compound and an oxygen compound. .
このラッカー層は例えば通常のトンネル形反応器中でプ
ラズマの非帯電成分とのみならず例えば通常のプレーナ
形反応器中でプラズマの帯電及び非帯電成分の混合物と
接触できる。This lacquer layer can come into contact not only with uncharged components of the plasma, for example in a conventional tunnel reactor, but also with a mixture of charged and uncharged components of the plasma, for example in a conventional planar reactor.
斯の種の方法は、例えば、基板上に導電トラックを形成
するため基板全体を金属又は多結晶珪素の導電層で被覆
しこの導電層の一部分を有機ラッカー層で覆い、然る後
ラッカー層で覆われていない部分を除去するようになし
た半導体装置の製造に特に好適である。最終的にはこの
有機ラッカー層の除去を前述した種類の方法によって行
なう。Such methods include, for example, coating the entire substrate with a conductive layer of metal or polycrystalline silicon in order to form conductive tracks on the substrate, covering a portion of this conductive layer with an organic lacquer layer, and subsequently applying the lacquer layer. It is particularly suitable for manufacturing semiconductor devices in which uncovered portions are removed. Finally, this organic lacquer layer is removed by a method of the type described above.
この場合このラッカー層の下側に在る導電層を局部的に
腐蝕する惧れがある。実際にはこの腐蝕を出来るだけ紡
ぐようにするため、有機ラッカー及？導電層をエッチン
グする速度の比すなわち゛エッチング選択性′゜は出来
るたけ大きい方かよい。In this case, there is a risk that the conductive layer underlying this lacquer layer will be locally corroded. In fact, in order to spin this corrosion as much as possible, organic lacquer and organic lacquer are used. The ratio of etching speeds of the conductive layer, that is, the ``etching selectivity'', should be as large as possible.
米国特許明細書第３８６７２１６号はハロゲン化合物と
してＣＦ４を含みかつ酸素化合物として０■を含む気体
混合物中に形成されるプラズマの成分と有機ラッカー層
とを接触させることによってこの層のエッチングを行な
う前述したような方法を明らかにしている。この方法で
はこの有機ラッカーの除去を多結晶珪素の導電層の除去
に対するよりも約１００倍速く行なうことか出来る。U.S. Pat. No. 3,867,216 describes the etching of an organic lacquer layer by bringing it into contact with components of a plasma formed in a gas mixture containing CF4 as a halogen compound and 0 as an oxygen compound. It reveals a method like this. This method allows the removal of this organic lacquer to be approximately 100 times faster than for the removal of polycrystalline silicon conductive layers.
しかし既知の方法では有機ラッカー及び多結晶珪素をエ
ッチングして除去する速度比か制限を受けるという欠点
かあり、そのため、実際には有機ラッカー層の下側に位
置する多結晶珪素の導電層が腐食されてしまう。導電ト
ラックを導電層中に形成する場合には、形成し得る最小
パターンのディテールがこの腐食のため制限されてしま
う。However, the known method has the drawback of being limited in the rate of etching and removal of organic lacquer and polycrystalline silicon, so that in practice the polycrystalline silicon conductive layer located underneath the organic lacquer layer is corroded. It will be done. When forming conductive tracks in a conductive layer, this corrosion limits the smallest pattern detail that can be formed.
本発明の目的は前述した従来方法の欠点を軽減すること
にあり、この目的を達成するため本発明の方法によれば
、ＣＦ４ と酸素化合物とを含む気体混合物中に形成さ
れるプラズマの非帯電成分に有機ラッカー層を接触させ
ることによって、基板上に局部的に存在する有機ラッカ
ー層をエッチングするようになした半導体装置の製造方
法において、前記プラズマが形成される前記気体混合物
が酸素化合物としてＮＯを５５〜７５容量％だけ含むよ
うにすることを特徴とする。The purpose of the present invention is to alleviate the drawbacks of the conventional methods mentioned above, and to achieve this purpose, according to the method of the present invention, a non-charged plasma formed in a gas mixture containing CF4 and an oxygen compound is provided. A method for manufacturing a semiconductor device, characterized in that an organic lacquer layer locally present on a substrate is etched by bringing the organic lacquer layer into contact with a component, wherein the gas mixture in which the plasma is formed contains NO as an oxygen compound. It is characterized by containing only 55 to 75% by volume.
本発明によれば、混合気体中に形成されるプラズマの帯
電成分は有機ラッカーを多結晶珪素の導電層よりも約５
００倍速く除去出来る。According to the invention, the charged component of the plasma formed in the gas mixture makes the organic lacquer about 50% less than the polycrystalline silicon conductive layer.
It can be removed 00 times faster.
図面につき本発明を説明する。The invention will be explained with reference to the drawings.
第１図〜第５図は基礎材料をＮ形珪素基板１の形態て利
用し、この基板を通常の方法で約１０００ｎｍの厚さを
有しかつフィールド酸化物と称せられるＳＩ０２領域２
によって互いに絶縁されたフィールド（第１図）に副分
割するようになした電界効果トランジスタの製造方法の
順次の段階における断面を示す。図面を明確にするため
、図中唯一個のフィールドを示してあるにすぎないが、
実際にはこの種のＳｉ基板は多くの斯様なフィールドを
含んている。1 to 5, the basic material is utilized in the form of an N-type silicon substrate 1, which is processed in a conventional manner into an SI02 region 2 having a thickness of approximately 1000 nm and referred to as field oxide.
1A and 1B show cross-sections at successive stages of a method for manufacturing a field effect transistor, subdivided into mutually insulated fields (FIG. 1); For clarity, only one field is shown in the diagram.
In reality, this type of Si substrate contains many such fields.
フィールド酸化物２の形成後、基板１に厚さ約１０ｎｍ
のいわゆるゲー１・酸化物３の薄い層を備え、その後に
ゲート電極として供する導電Ｉ・ラックを形成するため
、この組立体を金属又は多結晶珪素の層４及び有機ラッ
カーの層５て被覆する。このラッカー層５はまた電界効
果トランジスタのゲートの位置を画成するために供する
（第２図）。After the formation of the field oxide 2, the substrate 1 is coated with a thickness of approximately 10 nm.
The assembly is then coated with a layer 4 of metal or polycrystalline silicon and a layer 5 of an organic lacquer in order to form a conductive I-rack which serves as a gate electrode. . This lacquer layer 5 also serves to define the location of the gate of the field effect transistor (FIG. 2).
続いて、このラッカー層５によって被覆されていない多
結晶珪素層４の一部分とその下側に位置する例えば８１
０２層のようなゲート酸化物の一部分とを除去し、従っ
てＳｉ基板１のこれらの部分中に、Ｂ−イオンインプラ
ンテーションによって被覆されていないＰ形Ｓｉ領域６
及び７を形成する。これら両領域は後でトランジスタの
ソース及びドレインとして作用する（第３図）。Subsequently, the part of the polycrystalline silicon layer 4 not covered by this lacquer layer 5 and the part located below it, e.g.
02 layer and thus in these parts of the Si substrate 1 a P-type Si region 6 which is not covered by B- ion implantation is removed.
and 7. Both these regions will later act as the source and drain of the transistor (FIG. 3).
ラッカー層５を除去した後、組立体に既知のようにＳｉ
０２の絶縁層８を被覆し、この絶縁層中にフォトラッカ
ーのマスキング層９（第４図）によって通常の方法で窓
１０（第５図）を形成し、これら？をＰ形Ｓｉ領域６及
び７用の接点窓として用いる。After removing the lacquer layer 5, the assembly is made of Si
02 and in which a window 10 (FIG. 5) is formed in the usual manner by means of a masking layer 9 of photolacquer (FIG. 4) in this insulating layer. is used as a contact window for P-type Si regions 6 and 7.
これらの窓１０の形成後、マスキング層９を通常の方法
で除去し、ソース及びドレイン電極として供する導電Ｉ
・ラックを形成するためこの組立体を金属又は多結晶珪
素の導電層１１で再び完全に被覆する。導電層の一部分
を通常の如き有機ラッカー層１２によって覆い（第５図
）、然る後非被覆部分を通常の方法で除去する。最終的
には有機ラッカー層を気体混合物中に形成されるプラズ
マの非帯電成分と接触させることによってこの有機ラッ
カー層を除去するが、この場合、この気体混合物はハロ
ゲン化合物であるＣＦ４及び酸素化合物を含む。After the formation of these windows 10, the masking layer 9 is removed in the usual manner and the conductive layers 9 are removed to serve as source and drain electrodes.
- Completely covering the assembly again with a conductive layer 11 of metal or polycrystalline silicon to form a rack. Parts of the conductive layer are covered with a conventional organic lacquer layer 12 (FIG. 5), after which the uncoated parts are removed in a conventional manner. Finally, the organic lacquer layer is removed by contacting it with the uncharged component of a plasma formed in a gas mixture, which contains the halogen compounds CF4 and oxygen compounds. include.
本発明によれば、気体混合物は酸素化合物としてＮＯを
含み、その結果、有機ラッカーを多結晶珪素よりも約５
００倍早くエッチング除去することが出来る。According to the invention, the gas mixture contains NO as oxygen compound, so that the organic lacquer is about 5
Etching can be removed 00 times faster.
後に説明する実施例の場合には、直径が約１００ｍｍで
Ｍｏ又は多結晶珪素で被覆され、厚さが２５０〜５００
ｎｍでしかもＳｉＯ■の基板上に設けられているＳｉデ
ィスクをバレル型のプラズマエッチング反応＝６
？中でエッチングした。この場合、エッチングをしない
部分には１０００〜１５００ｎｍの厚さの有機ラッカー
を被覆した。基板温度を約１２５°Ｃとし、このように
して処理されたディスクをバレル型の反応器中で周波数
１３．５６ ＭＨｚ ，電力約１５０Ｗ及びガス流量１
００〜３００ ｓｅｃ／ｍｉｎで発生されたエッチング
プラズマと接触させた。In the case of the embodiment described later, the diameter is about 100 mm, the film is coated with Mo or polycrystalline silicon, and the thickness is 250 to 500 mm.
A barrel-type plasma etching reaction is performed on a Si disk provided on a substrate of SiO■ with a nanometer diameter = 6? It was etched inside. In this case, the parts not to be etched were coated with an organic lacquer with a thickness of 1000-1500 nm. The substrate temperature was approximately 125° C., and the disks thus treated were placed in a barrel-type reactor at a frequency of 13.56 MHz, a power of approximately 150 W, and a gas flow rate of 1
It was brought into contact with an etching plasma generated at a rate of 00 to 300 sec/min.
実施例Ｉ
第６図は有機ラッカー（ＰＲ）及び多結晶珪素（Ｓｉ）
が、全圧を６０ＰａとしたＣＦ４及びＮＯの気体混合物
及び比較のための全圧を６０ＰａとしたＣＦ４及び０■
の気体混合物中に形成されるプラズマの非帯電成分て、
エッチング中にエッチング除去されるエッチング速度Ｒ
（ｎｍ／ｍｉｒｉ）をこれら気体混合物にそれぞれ追
加されるべきＮＯ及び０■の容量％で表わした分量の関
数として示す曲線図である。多結晶珪素のエッチング速
度は実際の値のＩＯ倍で示してある。Example I Figure 6 shows organic lacquer (PR) and polycrystalline silicon (Si)
However, a gas mixture of CF4 and NO at a total pressure of 60 Pa and a gas mixture of CF4 and NO at a total pressure of 60 Pa for comparison.
The uncharged component of the plasma formed in the gas mixture of
Etching rate R of etching removal during etching
(nm/miri) as a function of the amount, expressed in volume %, of NO and 0 μ to be added to these gas mixtures, respectively. Etching rates for polycrystalline silicon are expressed as IO times the actual value.
この図から、有機ラッカー及び多結晶珪素のエッチング
速度の比すなわち゛′選択性″はＣＦ４／Ｏ■混合物（
約７０容量％の０■）に対しては１００てあり、？Ｆ４
／ＮＯ混合物（約６０容量％のＮＯ）に対しては最大で
約５００であることが判った。これかためＣＦ４／０２
混合物によって達成出来る選択性は０■の代りにＮＯを
加えることによって著しく増大する。From this figure, it can be seen that the ratio of etching rates of organic lacquer and polycrystalline silicon, or ``selectivity'', is the same as that of CF4/O mixture (
There is 100 for approximately 70% by volume (0 ■). F4
A maximum of about 500 was found for the /NO mixture (about 60% NO by volume). This is hard CF4/02
The selectivity achievable with the mixture is significantly increased by adding NO instead of 0.
第１図〜第５図は本発明による方法を使用して製造され
る半導体装置の一部分を順次の製造工程に対応させて示
した略図的断面図及び第６図はＮＯ及び０２を可変量と
して夫々含むＣＦ４／Ｎｏ及び比較用としてＣＦ４／０
■混合物中に形成されるプラズマ成分によってエッチン
グ中に得られる多結晶珪素及び有機ラッカーのエッチン
グ速度を示す曲線図である。
■・・・基板 ２・・・フィールド酸化物
３・・・ゲート酸化物（又はＳｉＯ■層）４・・・（金
属又は多結晶珪素）層
５．１２・・・ラッカー層 ６，７・・・領域８・・
・絶縁層 ９・・・マスキング層ｌＯ・・・
窓 １１・・・導電層−９＝
Ｌ
ＬＬ
工
匡
Ｌ1 to 5 are schematic cross-sectional views showing a portion of a semiconductor device manufactured using the method according to the present invention corresponding to the sequential manufacturing steps, and FIG. 6 shows NO and 02 in variable amounts. CF4/No including each and CF4/0 for comparison
(2) A curve diagram showing the etching rate of polycrystalline silicon and organic lacquer obtained during etching by the plasma components formed in the mixture. ■... Substrate 2... Field oxide 3... Gate oxide (or SiO ■ layer) 4... (Metal or polycrystalline silicon) layer 5.12... Lacquer layer 6,7...・Area 8...
・Insulating layer 9...Masking layer lO...
Window 11...Conductive layer-9=L LL Work L
Claims (1)
されるプラズマの非帯電成分に有機ラッカー層を接触さ
せることによって、基板上に局部的に存在する有機ラッ
カー層をエッチングするようになした半導体装置の製造
方法において、前記プラズマが形成される前記気体混合
物が酸素化合物としてＮＯを５５〜７５容量％だけ含む
ようにすることを特徴とする半導体装置の製造方法。1. A semiconductor in which an organic lacquer layer locally present on a substrate is etched by contacting the organic lacquer layer with an uncharged component of a plasma formed in a gas mixture containing CF_4 and an oxygen compound. A method for manufacturing a semiconductor device, characterized in that the gas mixture in which the plasma is formed contains 55 to 75% by volume of NO as an oxygen compound.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL8004008A NL8004008A (en) | 1980-07-11 | 1980-07-11 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE |
| NL8004008 | 1980-07-11 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56105745A Division JPS5752136A (en) | 1980-07-11 | 1981-07-08 | Method of producing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02290021A true JPH02290021A (en) | 1990-11-29 |
| JPH0359575B2 JPH0359575B2 (en) | 1991-09-11 |
Family
ID=19835611
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56105745A Granted JPS5752136A (en) | 1980-07-11 | 1981-07-08 | Method of producing semiconductor device |
| JP2090488A Granted JPH02290021A (en) | 1980-07-11 | 1990-04-06 | Manufacture of semiconductor device |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56105745A Granted JPS5752136A (en) | 1980-07-11 | 1981-07-08 | Method of producing semiconductor device |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US4374699A (en) |
| JP (2) | JPS5752136A (en) |
| CA (1) | CA1165902A (en) |
| DE (1) | DE3125052A1 (en) |
| FR (1) | FR2486716B1 (en) |
| GB (1) | GB2081161B (en) |
| IE (1) | IE52045B1 (en) |
| NL (1) | NL8004008A (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59163826A (en) * | 1983-03-08 | 1984-09-14 | Toshiba Corp | Dry etching method |
| US4501061A (en) * | 1983-05-31 | 1985-02-26 | Advanced Micro Devices, Inc. | Fluorine plasma oxidation of residual sulfur species |
| US4431477A (en) * | 1983-07-05 | 1984-02-14 | Matheson Gas Products, Inc. | Plasma etching with nitrous oxide and fluoro compound gas mixture |
| US4544416A (en) * | 1983-08-26 | 1985-10-01 | Texas Instruments Incorporated | Passivation of silicon oxide during photoresist burnoff |
| ES2048158T3 (en) * | 1986-06-26 | 1994-03-16 | American Telephone & Telegraph | PROCEDURE TO MANUFACTURE INTEGRATED CIRCUIT DEVICES USING A MULTI-LEVEL RESIST STRUCTURE. |
| US4836887A (en) * | 1987-11-23 | 1989-06-06 | International Business Machines Corporation | Chlorofluorocarbon additives for enhancing etch rates in fluorinated halocarbon/oxidant plasmas |
| US4845053A (en) * | 1988-01-25 | 1989-07-04 | John Zajac | Flame ashing process for stripping photoresist |
| US4936772A (en) * | 1988-01-25 | 1990-06-26 | John Zajac | Flame ashing process and apparatus for stripping photoresist |
| JP2813703B2 (en) * | 1992-07-20 | 1998-10-22 | 株式会社クボタ | Spiral bevel gear manufacturing equipment |
| US7299805B2 (en) | 2002-06-07 | 2007-11-27 | Marctec, Llc | Scaffold and method for implanting cells |
| US20050136666A1 (en) * | 2003-12-23 | 2005-06-23 | Tokyo Electron Limited | Method and apparatus for etching an organic layer |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3867216A (en) * | 1972-05-12 | 1975-02-18 | Adir Jacob | Process and material for manufacturing semiconductor devices |
| JPS5289540A (en) * | 1976-01-21 | 1977-07-27 | Mitsubishi Electric Corp | Etching gaseous mixture |
| JPS5915174B2 (en) * | 1976-07-26 | 1984-04-07 | 日本電信電話株式会社 | How to make a photomask |
| JPS6019139B2 (en) * | 1976-07-26 | 1985-05-14 | 三菱電機株式会社 | Etching method and mixture gas for plasma etching |
| JPS53112065A (en) * | 1977-03-11 | 1978-09-30 | Toshiba Corp | Removing method of high molecular compound |
| US4260649A (en) * | 1979-05-07 | 1981-04-07 | The Perkin-Elmer Corporation | Laser induced dissociative chemical gas phase processing of workpieces |
| NL8004007A (en) * | 1980-07-11 | 1982-02-01 | Philips Nv | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE |
-
1980
- 1980-07-11 NL NL8004008A patent/NL8004008A/en not_active Application Discontinuation
-
1981
- 1981-06-26 DE DE19813125052 patent/DE3125052A1/en active Granted
- 1981-07-08 CA CA000381351A patent/CA1165902A/en not_active Expired
- 1981-07-08 JP JP56105745A patent/JPS5752136A/en active Granted
- 1981-07-08 GB GB8121035A patent/GB2081161B/en not_active Expired
- 1981-07-08 IE IE1530/81A patent/IE52045B1/en not_active IP Right Cessation
- 1981-07-09 FR FR8113549A patent/FR2486716B1/en not_active Expired
- 1981-07-09 US US06/281,759 patent/US4374699A/en not_active Expired - Fee Related
-
1990
- 1990-04-06 JP JP2090488A patent/JPH02290021A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5752136A (en) | 1982-03-27 |
| IE811530L (en) | 1982-01-11 |
| IE52045B1 (en) | 1987-05-27 |
| FR2486716A1 (en) | 1982-01-15 |
| DE3125052A1 (en) | 1982-03-18 |
| US4374699A (en) | 1983-02-22 |
| GB2081161B (en) | 1984-08-08 |
| GB2081161A (en) | 1982-02-17 |
| JPH0359575B2 (en) | 1991-09-11 |
| FR2486716B1 (en) | 1986-01-24 |
| NL8004008A (en) | 1982-02-01 |
| CA1165902A (en) | 1984-04-17 |
| DE3125052C2 (en) | 1990-06-07 |
| JPH0237091B2 (en) | 1990-08-22 |
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