JPH02224493A - Data signal receiver - Google Patents

Abstract

PURPOSE:To attain the reception of data with much quantity of information such as KANJI (Chinese character) by providing a protection means detecting a framing code so as to apply forward and backward protection processing through the use of the fact that the framing code is multiplexed for each predetermined timing. CONSTITUTION:Output of an internal counter output signal 319 and an output of a framing code detection circuit 305 are always compared. An output signal compared by a coincidence detection circuit 310 becomes noncoincident signals 311 and 312. Till a coincidence counter 314 counts up, the coincidence counter 314 is reset by a signal 317 when the noncoincident signal 311 reaches. That is, the coincidence counter 314 counts the number of consecutive coincident counts and outputs normally a countup signal 316 when 3 consecutive framing codes are received in the same phase. The noncoincidence counter 313 counts the number of consecutive dissident counts and clears the coincidence counter 314 when a signal 315 is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data receiving device that receives and decodes data signals such as character signals multiplexed on PAL television signals. Based on the frequency relationship between the color subcarriers and the color subcarriers, the framing code is
) The present invention relates to a data signal receiving device configured to fully demonstrate its code correction ability.

[Summary of the invention]

The present invention provides a data signal receiving device that decodes a data signal (for example, a character signal using BEST) multiplexed on an l'AL television signal, in which a color burst signal, which is always transmitted in a PAL television signal, is decoded. From this signal, a signal with the same frequency as the clock run-in signal for teletext broadcasting, etc., which is transmitted separately by a PC circuit, etc. is generated, and among the various phase signals of the same frequency generated based on this signal. Select the signal with the closest phase to the clock run-in of teletext etc., use this as the clock signal and count H from the first field of the television signal, and use the framing code if character signals etc. are multiplexed. The system detects this and reproduces the framing code timing using forward and backward protection.

In a preferred embodiment of the present invention, the interval between 8 is set to 361 clocks or 362 clocks, for example.
It is assumed that the signals are multiplexed at a predetermined timing. Further, the second field is received with a character signal multiplexed after a predetermined number of bits. Furthermore, by receiving the frame after one frame as having been sent with a phase shift of half a clock so that it is in the same phase as the first field, reception with forward and backward protection of the framing code is possible, and PAL This system was designed to provide the same powerful error correction effect as Japanese teletext broadcasting even with standard television signals.

[Prior Art] Ceefax, developed in England, is known as a teletext multiplexed on a conventional PAL television signal. FIG. 4 shows an example of this Ceefax multiplexed signal.

To decode a character signal from the signal shown in FIG. 4, a clock signal is first generated using the 16 bits of the clock run-in signal. The bit rate of the clock signal is 6.9
375 Mbps and has no frequency relationship with color subcarriers, etc., so bit synchronization is reproduced only from the clock run-in signal sent as described above.

Therefore, compared to Japanese teletext broadcasting, the reception method is weaker against noise. Also, with Ceefax above, IH
Since the number of bits multiplexed to the receiver is a fixed number of 444 bits, a method of reproducing from H synchronization may be considered, but it is difficult to maintain the a+i accuracy of the horizontal synchronization signal on the receiving side to less than 1 bit. It's impossible.

For the above reasons, the receiving side will operate entirely based on the transmitted clock run-in or lock synchronization signal. For example, the framing code is detected by the timing of this clock signal. If there is an error of one bit or less in the framing code, it can be correctly received, but if there is an error of two or more bits, the framing code cannot be detected, and in that case, the entire packet signal cannot be captured.

In this way, it can be said that Ceefax is not suitable for services that transmit code signals such as computer programs that cannot be established even if there is an error in even one bit.

(Problem to be solved by the invention)
In teletext broadcasting by facsimile, the clock signal is reproduced in units of packets, the framing code is detected, and the code signal is decoded, so there is a drawback that the reproduction of the clock signal is not very resistant to noise.

Furthermore, if there are two or more bit errors in the framing code period, there is a drawback that the framing timing cannot be detected.

Therefore, an object of the present invention is to provide a data signal receiving device that fully utilizes the capabilities of the (272,190) code and is capable of receiving data with a large amount of information such as kanji characters even in PAL television signals. be.

(Means for Solving the Problems) A data signal receiving device according to the present invention is a receiving device that decodes a data signal multiplexed into a PAL television signal, and which receives a signal having the same frequency as the data signal from a color burst signal. forward and backward signals by detecting the framing code and using the fact that the framing code is multiplexed at each predetermined timing. A protection means for performing protection processing is provided to ensure that the framing code can be received against reception errors.

[For production]

In the data signal receiving device according to the present invention, the clock signal is regenerated from the color burst signal, the clock signal is made resilient to noise, and furthermore, the data signal can be received with forward and backward protection against framing code detection. By making full use of the capabilities of the (272,190) code, it is possible to receive data with a large amount of information, such as Chinese characters, even in PAL television signals.

〔Example〕

Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 shows an embodiment of the data signal receiving device according to the present invention, in which 201 is a PAL television signal with a character signal multiplexed (see Japanese Patent Application No. 63-285867). ). That is, the pit rate is (14/11) x fsc. Here fsc is P
This is the subcarrier frequency of the AL television signal, and fsc = 4.43361875 MHz. Therefore, the bit rate of the character signal is 5.6427875
It is Mbps.

Reference numeral 202 denotes a color subcarrier reproducing circuit, which reproduces the color subcarriers 4.0 and 4.2, which are reproduced as continuous signals by an APC circuit or the like from the color burst signals multiplexed in each H.
43361875 Outputs Mllz signal.

Reference numeral 203 indicates a frequency dividing circuit that divides the color subcarrier frequency to 1/11. Therefore, the frequency of the output signal of the frequency dividing circuit 203 is 0.40305625 MHz.

204 is a phase comparator circuit for generating a manual signal to the VCO 205. The output frequency of VC0205 is 5.6
427875 MHz, by frequency divider circuit 206! The frequency is divided by /14. Therefore, the frequency of the output signal of the frequency dividing circuit 206 is 0.40305825 M)lz, which is the same as the frequency of the output signal of the frequency dividing circuit 203.

The output signal of the VC0205 is input to the phase selection circuit 207, and various phase signals are prepared. For example, if the phase is Inn
It may be shifted by 5.

208 is a clock run-in extraction circuit. The frequency of the clock run-in signal 209 is the same as the output signal frequency of the VC0205, and the signal closest to the phase of the clock run-in signal 209 is selected from among the various phase signals prepared by the phase selection circuit 207 and is used as the signal 210. Output. That is, signal 210 and clock run-in signal 209
This is a nearly phase-locked signal.

211 is a vertical synchronization signal detection circuit, in particular, a circuit that detects only the first field. Then, the multiple timing signal of the second field is output from the framing code generation circuit 214 via the H counter 213.

A horizontal synchronization timing signal generation circuit 212 generates a signal for counting H pulses.

215 is a circuit for detecting the framing code of the input signal, and generates a manual signal to the framing code generating circuit 214. This framing code generation circuit 214 specifies H of the output signal 217 of the H counter 213 (no.
5, etc., to perform forward and backward protected reception of the framing code. Based on the timing of the framing code generation circuit output 216, only the data portion (data string after the framing code) of the packet signal (output of the packet signal detection circuit 217) is accurately extracted via the data extraction circuit 218.

The phase selection circuit 207 should automatically invert the phase by 180° in the first field due to the configuration shown in FIG. It's okay.

FIG. 2 shows a detailed circuit configuration of the framing code generation circuit 214 shown in FIG. 1. Here 3Ql is PAL
302 is a signal 210 (a clock signal whose phase is inverted by 180 inches for each first field), 303 is a signal 8 to 251 (and 312-329
■Gate signal indicating period, 304 is gate signal of 8H only, 305 is framing code detection circuit, 306 is 3
61-bit counter, 307 is an AND circuit, 308 is a 113036-bit counter, 309 is an AND circuit,
310 is a coincidence detection circuit, 311 is a mismatch pulse, 312
is a coincidence pulse, 313 is a mismatch counter, 314 is a coincidence counter, 315 is a mismatch counter output signal, 3
1.6 is the coincidence counter output number 3, 317 is an AND circuit, 31B is an AND circuit, 319 is a framing timing signal by an internal counter, 320 is 113036
A power counter output signal and 321 indicate a framing timing output signal, respectively.

The operation of the circuit shown in FIG. 2 will be explained below in order.

In the initial state, the framing code detection circuit 30
The timing signal detected at 5 passes through gate 309 and resets 361 bit counter 306. Therefore, from now on, the 361-bit counter 306 counts the clock signal 302 and generates the internal framing code signal 319. This counter 306 is
It operates only during periods 8-25H and 312-329H when signals are multiplexed.

Internal counter output signal 3tq and the output of framing code detection circuit 305 are constantly compared. Here, the signal indicating whether or not the character signal 303 is multiplexed is determined by detecting clock run-in or the like.

The output signals compared by the coincidence detection circuit 310 become a mismatch signal 311 and a coincidence signal 312. match counter 31
The discrepancy signal 311 is always displayed until 4 counts up.
When the signal 317 arrives, the coincidence counter 314
will be reset. That is, the coincidence counter 314 counts consecutive - political religions, and normally outputs a count-up signal 316 when three consecutive framing codes can be received in the same phase. The other mismatch counter 313 counts the number of consecutive mismatches, and clears the match counter 314 when the signal 315 is output.

In addition, the beginning of the second field is reset according to the timing of the framing code of the first multiplexed H of the first field of the gate signal 304, and 113,036 bits are counted.
6 is reset again to generate an internal framing code.

811 or 312H of the gate signals 303 and 304 shown in FIG. 2 may be interpreted as the first H within a certain field of the multiplexed signal.

As described above, with the configuration shown in FIG. 2, the framing code of the 296-bit character signal multiplexed on the PAL television signal can be reliably received.

However, the line numbers such as 8H mentioned above are based on the counting method shown in FIG.

Note that the data string shown in FIG. 1 is decoded by a (272,190) code and taken in as error-free 190-bit information. The CPU interprets the 190-bit information and displays characters and graphics on the CRT.

〔Effect of the invention〕

The effects of the data signal receiving device according to the present invention will be described below.

Compared to the Ceefax method described above as a prior art, the present invention allows a much more powerful lock regeneration circuit to be constructed. Additionally, the front and rear protection circuits ensure that framing codes can be received.

Therefore, after the framing code (272°19
0) Since code decoding operates at reliable timing, error correction ability can be fully utilized.

[Brief explanation of the drawing]

1 is a block diagram showing an embodiment of a data signal receiving device according to the present invention; FIG. 2 is a block diagram showing a framing code generation circuit; FIG. 3 is a diagram showing line numbers of a PAL television signal; Figure 4 is a diagram showing character No. 18 of "°Ceefax". 202...Color subcarrier regeneration circuit, 203...
- Frequency divider circuit, 204... Phase comparison circuit, 205... VCO (voltage controlled oscillator), 206...
- Frequency dividing circuit, 207... Phase selection circuit, 208... Clock run-in extraction circuit, 211...
Vertical synchronization signal detection circuit, 212...Horizontal synchronization timing signal generation circuit, 213
-H counter 214--Framing code generation circuit, 215...
-Framing code detection circuit, 217... Packet (g minute detection circuit, 21B... Data extraction circuit.

Claims (1)

[Claims] 1) In a receiving device that decodes a data signal multiplexed on a PAL television signal, a signal having the same frequency as the data signal is reproduced from a color burst signal, and the multiplexed clock run-in and comprising a reproduction means for reproducing signals of the same phase, and a protection means for detecting a framing code and performing forward and backward protection processing by utilizing the fact that the framing codes are multiplexed at each predetermined timing, A data signal receiving device characterized in that a framing code can be reliably received even in the case of reception errors. 2) The data signal receiving device according to claim 1, wherein a character signal is used as the data signal.