JPH0779320B2 - Control signal extraction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for decoding and reproducing a signal including a control signal for system control in a frame of a digitalized audio signal, and particularly when a signal is lost. In particular, the present invention relates to a control signal extraction circuit suitable for preventing malfunction of the system due to erroneous extraction of control signals.

[Background of the Invention]

A conventional device detects whether there is an error in transmission data including a control signal periodically inserted in a signal frame as described in JP-A-57-73577, and corrects it by using the result of error detection. By sampling only the control signals that seem to be present, and then making a majority decision on these signals to extract the control signals, erroneous extraction is prevented. However, in a system in which the control signal is not error-detection-correction-coded and errors in the control signal can be eliminated only by making a majority decision, etc., a large number of control signals are continuously converted into the same signal due to bursty signal loss. No consideration was given to the protection of the control signal in case of mistake.

For example, in satellite broadcasting, the control signal is periodically sent repeatedly at a signal frame cycle, but coding is not performed for error detection and correction. By the way, in sanitary broadcasting, when the transmitting station is switched, the carrier is lost for a certain period, and a burst error occurs in the signal. At this time, in order to avoid noise such as shock noise, an output suppression signal is sent to the control signal. However, if the carrier is lost and the input signal is fixed at "0" for a certain period, there is a problem that the output suppression cancellation signal is erroneously extracted and a shock noise is generated even if a majority decision is made. Further, when the control signal is displayed, there is a problem that the display flickers during the carrier missing period.

[Object of the Invention]

An object of the present invention is to provide a control signal extraction circuit which has a simple configuration and can obtain a sufficiently reliable control signal even when there is a burst-shaped signal loss.

[Outline of Invention]

In the present invention, the detection result of the frame synchronization signal included in the signal frame is used to select a control signal that is likely to be correct from the received control signals. That is,
While the frame sync signal is detected, it is judged that the signal is normal, and when the frame sync signal cannot be detected, it is judged that the signal is missing or the reliability of the control signal is low and the control signal extraction malfunction is detected. To prevent.

Example of Invention

 An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows an embodiment according to the basic configuration of the present invention. In FIG. 1, transmission data having a sync signal for each frame input from the signal input terminal 1 and including a control signal having the periodicity of the frame period is first detected by the sync signal detection circuit 2. . The same transmission data is also input to the control signal selection circuit 6. When the sync signal detecting circuit 2 detects a sync signal from the input transmission data, it outputs a detection signal to the set terminal of the RS flip-flop 4. Further, the timing circuit 3 is synchronized with a protection synchronization signal which is protected against loss of the synchronization signal so that the timing of the system is not disturbed even when a synchronization signal is not detected due to a code error in the transmission data. It is input from the signal detection circuit 2. The timing circuit 3 uses the protection synchronization signal as a timing reference,
A timing signal for extracting a control signal from the input transmission data string and an end signal are generated at the timing when the control signal extraction in the signal frame is completed. This end signal is input to the reset terminal of the RS flip-flop 4, and the timing signal for extracting the control signal is input to the AND gate 5. The Q output of the RS flip-flop 4 is connected to the AND gate 5, and the AND gate 5 outputs the timing signal for extracting the control signal from the timing circuit 3 according to the signal from the RS flip-flop 4 to the control signal selection circuit. It is transmitted to the clock terminal of 6. Each time a timing signal is input to the clock terminal, the control signal selection circuit 6 fetches a signal from the transmission data of the input terminal into an internal register, and outputs a correct control signal by a majority decision or continuity decision to the control signal output terminal 7
Selectively output to.

In this embodiment, the RS flip-flop 4 is set only when the sync signal is detected, and the AND gate 5 transmits the timing signal for extracting the control signal. Therefore, when the transmission data is lost in bursts over a plurality of frames, the sync signal is not detected, the RS flip-flop 4 remains reset, the AND gate 5 remains closed, and the timing signal becomes It is not transmitted to the control signal selection circuit 6. Therefore, the control signal selection circuit 6 holds the state before the loss of the transmission data,
No wrong control signal is extracted and output.
When the loss of the transmission data ends and the synchronization signal is detected again, the AND gate 6 transmits the timing signal to the control signal selection circuit 6 and starts the extraction of the correct control signal.

Next, the present invention will be described more specifically with reference to the embodiment of FIG. 2 and FIG. FIG. 2 shows an example in which the control signal selecting means of the present invention is constituted by a circuit based on majority decision,
FIG. 3 shows a decoder (Fig. 2a, 11a,
It is a figure which shows the truth value of 11b).

In the embodiment shown in FIG. 2, the transmission data has a control signal of 16 bits which is continuous for each frame divided by the synchronizing signal. In this example, the shift register 10, the decoder 11, and the control signal output terminal 7 for majority decision are shown only for 2 bits and the other 14 bits are omitted. As a result, the operation is shown in the figure. It is similar to 2 bits.

The signal from the signal input terminal 1 is input to the sync signal detection circuit 2 and simultaneously input to the 16-bit shift register 8. The clock simultaneously with the signal bits is supplied to the shift register 8 from the clock terminal 9, and the input signal is serially shifted. The timing circuit 3 uses the synchronization signal as a timing reference and sets the leading bit of the control signal sequence to 16 bits.
To Q _P of bit shift register 8, the final bit outputs a timing clock for the control signal extracted by the timing output to Q _A. This timing clock is connected to the clock terminals of the majority decision 5-bit shift registers 10a, 10b ...
Only the control signal of the frame in which the sync signal is detected is input to the shift registers 10a, 10b, ... For each bit.
The majority logic of this embodiment takes 3 bits or more out of 5 bits, and Y of the majority decision decoders 11a, 11b ... To which Q _{A to} Q _E of the 5 bit shift registers 10a, 10b.
The outputs are as shown in the truth table shown in FIG. 3 for the inputs A to E. Each bit of the control signal which is majority-judged by the decoders 11a, 11b ... Is output from the control signal output terminals 7a, 7b ... For each bit. In the present embodiment, a 5-bit shift register 10 in which a majority decision is made
The clocks a, 10b, ... Are inserted through the AND gate 5 only when the sync signal is detected, so that the contents cannot be replaced if the sync signal is not detected. Therefore, it is possible to prevent an erroneous operation in which an erroneous control signal is extracted when the signal is missing.

The above is an example in which the majority decision circuit is used as the control signal selection means. However, when a predetermined number or more of the same signals are continuously detected, it can be determined as a correct control signal, and the present invention can be applied to that case as well. In that case, a timing signal for determining whether or not the transmission data input to the control signal selecting means periodically and continuously match,
When the sync signal is not detected, the clock of the counter that counts consecutive matches up to a predetermined number, the reset pulse that resets the counter when the data do not match, and the clock of the control signal match determination and output registers are blocked. You can do this. Such an example is shown in FIG.

In the embodiment shown in FIG. 4, the timing circuit 3 outputs three kinds of timing pulses. The first timing pulse controls the control signal bit from the transmission data to the first D latch 12
Store in a. The second timing pulse is the first D
Detects a match between the contents of the latch 12a and the second D latch 12b.
The output of the E _X -R gate 13a, the first D latch 12a and the third
E _X -R gate 1 for detecting the coincidence of the contents of D latch 12c of
The output of 3b is stored in the fourth D latch 14a and the fifth D latch 14b. The third timing pulse is applied to the second and third D latches 12b and 12c, respectively, and the first and second D latches 12a and 12b.
Is stored and used for the reset and count clock of the counter 16. The counter 16 has a first D
If the contents of the latch 12a and the second D latch 12b are different, they are reset by the reset pulse from the AND gate 15a, and if the contents of the first D latch 12a and the second D latch 12b match, by the clock pulse from the AND gate 15b. Count up. Therefore, the counter 16 continues to count up while the same control signal as the contents of the second D latch 12b is continuously input to each first frame to the first D latch 12a. When the same control signal and the contents of the second D latch 12b successively four frames in this embodiment is input to the first D latch 12a, Q _c is "1" of the counter 16 becomes, the AND gate 17 A clock pulse is supplied to the third D latch 12c via the, and the contents of the second D latch 12b are stored in the third D latch 12c, and output from the control signal output terminal 7 as a correct control signal. When a new control signal different from the content of the third D latch 12c is input to the first D latch 12a via the AND gate 15c, the second D latch 12b is supplied with the clock and the first D latch 12b. The contents of 12a are stored in the second D latch.

As described above, in the embodiment of FIG. 4, the first D latch 12a
And the contents of the second D latch 12b match four times, that is, if the control signals match for five consecutive frames, the value is stored in the third D latch 12c and output. By the way, timing signals such as clocks and reset pulses to the second to fifth D latches 12b, 12c, 14a, 14b and the counter 16 are supplied from the timing circuit via the AND gates 5a, 5b. Therefore, as in the embodiment of FIGS. 1 and 2, the RS flip-flop 4 and the AND set by the sync detection signal are ANDed.
A latch that checks the continuity of the signal when the sync signal is not detected, such as when transmission data is lost, by the function of the gates 5a and 5b. Since the counters do not operate, it is possible to prevent the control signal from being erroneously extracted.

〔The invention's effect〕

According to the present invention, the control signal extraction operation can be stopped when a burst-like signal is lost with a simple configuration, and the control signal extraction operation can be continued immediately when the signal is restored. This is effective in preventing the occurrence of shock noise and display flicker due to erroneous extraction of the control signal when missing.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an embodiment showing a basic configuration of the present invention, FIG. 2 is a diagram showing a concrete embodiment, and FIG. 3 is a diagram showing the decoder of FIG. FIG. 4 is a diagram showing a truth value for this, and FIG. 4 is a diagram showing a concrete other embodiment. 1 ... Signal input terminal, 2 ... Synchronous signal detection circuit, 3 ... Timing circuit, 4 ... RS flip-flop, 5,5a, 5b, 15a, 15b,
15c, 17 ... AND gate, 6 ... Control signal selection circuit,
7,7a, 7b ... Control signal output terminal, 8,10a, 10b ... Shift register, 9 ... Bit clock input terminal, 11a, 11b ...
Decoder, 12a, 12b, 12c, 14a, 14b ... D latch, 13a, 13b ...
E _X -R gate, 16 ... counter

Claims (6)

[Claims] 1. A synchronization signal pattern is periodically provided for each frame of a transmission data string, and the presence or absence of the synchronization signal pattern is detected from the transmission data of one frame unit including a control signal having the periodicity of the frame period to perform synchronization. A means for generating a detection signal, a means for inputting the output of the synchronization signal detection means, a means for sampling only a control signal in a frame in which a synchronization signal pattern is correctly detected using this synchronization detection signal, and a synchronization signal pattern A control signal extracting circuit, comprising: a selecting unit for discriminating a correct control signal from a plurality of control signals for each frame sampled from a plurality of correctly detected frames, and selectively outputting the control signal. 2. A control signal extracting circuit according to claim 1, wherein said selecting means discriminates a correct control signal by a majority decision and selectively outputs it. 3. The selection device according to claim 1, wherein the selection means discriminates the signal as a correct control signal and selectively outputs the same control signal only when the same control signal is continuously obtained by a predetermined number or more. A control signal extraction circuit characterized by the above. 4. A synchronization signal pattern is periodically provided for each frame of a transmission data string, and the presence or absence of the synchronization signal pattern is detected from the transmission data of one frame unit including a control signal having the periodicity of the frame period to synchronize. A means for generating a detection signal, a means for inputting the output of the synchronization signal detection means, a means for sampling only a control signal in a frame in which a synchronization signal pattern is correctly detected using this synchronization detection signal, and a synchronization signal pattern The correct control signal is discriminated from the multiple control signals, one for each sampled frame, from the correctly detected multiple frames, and the selected control signal is output. If the correct control signal cannot be selected, the next correct control is performed from that point. Until the signal can be identified and selected, the control signal Stores the control signal output it previously, control signal extraction circuit, characterized in that a selection means for outputting the stored control signals. 5. A control signal extraction circuit according to claim 4, wherein said selection means discriminates a correct control signal by a majority decision and selectively outputs it. 6. The selecting device according to claim 4, wherein the selecting means discriminates the same control signal as a correct control signal and outputs it only when the same control signal is continuously obtained by a predetermined number or more. A control signal extraction circuit characterized by the above.