JPH02222029A - Animation/still picture display device - Google Patents

Abstract

PURPOSE:To display both an animation and a still picture at one time on a screen of a personal computer via a simple constitution by writing the animation data into a 2nd memory from a 1st memory and writing the still picture data via a CPU data bus. CONSTITUTION:The video signal is not written directly into a display memory (2nd memory 23) and stored once into a buffer memory (1st memory 22). The animation data is written into the memory 23 from the memory 22 and at the same time the still picture data is written via a CPU data bus 26 after the interruption of the vertical synchronizing signal received from a synchronizing separator 4 and the transfer of the animation to the memory 23 from the memory 22 under the time division control of a CPU 25 receiving a transfer end interruption from an address generating circuit 24. In such a constitution, an external access is possible to the memory even in an animation display mode and a still picture can be written. Thus both an animation and a still picture are simultaneously shown at a display part of a personal computer.

Description

[Detailed Description of the Invention] [Summary] Regarding a video/still image display device that displays a video and a still image on a display image of a personal computer, the video and still image can be displayed simultaneously on a computer image with a simple configuration. a digital image converter that receives a video signal and converts it into a digital image signal; a first memory that stores the output of the digital image converter; a second memory that stores image data corresponding to the display screen; a sync separation circuit that receives the video signal and separates and outputs a horizontal sync signal and a vertical sync signal; an address generation circuit that receives the signal and the vertical synchronization signal and provides a write or transfer address to the first and second memories, and a D/A converter that converts the second memory output into an analog signal and outputs it as a video signal. Then, in response to a vertical synchronization interrupt and a transfer end interrupt given from the address generation circuit after the end of video data transfer from the first memory to the second memory, the video data and still image data are written to the second memory. It is composed of a CPU that performs time division control.

[Industrial Field of Application] The present invention relates to a moving image/still image display device that displays moving images and still images on a display image of a personal computer.

There is a demand for displaying natural images (moving images, still images) along with character and graphic information on a personal computer (hereinafter referred to as a personal computer). However, there is no device that can handle moving images and still images at the same time, and it is necessary to install multiple devices to meet the demand, resulting in problems such as an increase in installation area and an increase in cost.

[Prior Art] FIG. 5 is a block diagram of a conventional moving image display device, and FIG. 6 is a block diagram of a conventional still image display device. First, the moving image display device shown in FIG. 5 will be explained. A video signal of the NTSC system, which is a standard moving image system in Japan, enters an image converter 1 and is converted from NTSC to RGB. The converted RGB image signal is sent to an A/D converter 2 for each color component.
After being converted into digital data, it is stored in the memory 3. The memory 3 is composed of a random memory (RAM) 3a and a serial memory 3b, and the random memory 3a is a display memory that has one-to-one correspondence with the personal computer display section, and images once stored in the random memory 3a are stored in the random memory 3a. The data is transferred to the serial memory 3b and then output.

On the other hand, the video signal enters the sync separation circuit 4, where the horizontal sync signal and vertical sync signal are separated from the image signal.
C is output as a horizontal/vertical synchronization signal. This NTSC
The horizontal and vertical synchronization signals enter the address generator 5. The address generator 5 generates a write address from the NTSC horizontal/vertical synchronizing signal and supplies it to the memory 3. The address generating section 5 also contains horizontal and vertical synchronizing signals from the personal computer video signal, and the address generating section 5 generates a transfer address from the personal computer horizontal and vertical synchronizing signals and supplies it to the memory 3.

The period of the video signal is (1/60) second, and the period of the personal computer video signal is (1/80) second. In this way, in order to display a video signal having a period different from the synchronization signal of the personal computer, which is a computer device, on the personal computer display section, it is necessary to perform speed conversion (scan conversion). That is, when writing a video signal, the address taken from the video signal is used as the write address given to the random memory 3a, and when transferring data read from the random memory 3a to the serial memory 3b, the address taken from the PC video signal is used as the transfer address. Use the specified address. This allows speed conversion.

The output of the serial memory 3b is sequentially read out and converted into an analog signal by the D/A converter 6.

Then, the output of this D/A converter 4 is converted into a video signal.
It is displayed on a personal computer display unit (not shown) such as RT. When displayed on the computer display section, the video signal (scan-converted video signal) output from the D/A converter 6 and the computer video signal synthesized by the superimposition circuit 7 are displayed. . As a result, the moving image is displayed on the display unit together with the character 5 graphic information.

Next, the still image display device shown in FIG. 6 will be explained.

Components that are the same as those in FIG. 5 are designated by the same reference numerals. In this case, there is no need for scan conversion, so CP
U can be used to write still image data to the display memory (random memory) 3a. The CPU 1 writes a still image digitizing signal (still image data) manually input via the CPU bus 12 to the random memory 3a. At this time,
The address given to the memory 3 is given from the address generation section 12 which receives a still image write request command from the CPU 11.

When reading image data stored in the random memory 3a, a transfer address output from the address generator 12 is given to the memory 3 in response to a personal computer horizontal/vertical synchronizing signal. Image data read from random memory 3a is transferred to serial memory 3b. The image data output from the serial memory 3b is converted into an analog signal by a D/A converter 6, then combined with a personal computer video signal by a superimposing circuit 7, and then provided to a personal computer display section.

[Problems to be Solved by the Invention] In the video display device shown in FIG. 5, writing to the memory is restricted by the synchronization signal of the video signal, and reading is restricted by the video signal of the personal computer. There was a problem in that the memory could not be accessed and still images could not be written. On the other hand, the still image display device shown in FIG. 6 lacks a circuit for digitizing video signals in real time, and therefore has the problem of not being able to handle moving images.

The present invention has been made in view of these problems, and an object of the present invention is to provide a moving image/still image display device that can simultaneously display moving images and still images on a personal computer image with a simple configuration.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. Components that are the same as those in FIG. 5 are designated by the same reference numerals. In the figure, 21
2 is a digital image converter that receives a video signal and converts it into a digital image signal; 22 is the digital image converter 2;
The first memory 23 stores the output of the first memory 22 or the image data of a still image, and the second memory 23 stores the image data corresponding to the display screen. These first and second memories 22 and 23 are two-port memories in which data can be written and read independently.

4 is a sync separation circuit that receives the video signal and separates and outputs a horizontal sync signal and a vertical sync signal; 24 receives the horizontal sync signal and the vertical sync signal and connects the first and second memories 2;
2. 23 is an address generation circuit that provides a write or transfer address; 6 is a D/A converter that converts the output of the second memory 23 into an analog signal and outputs it as a video signal; 25 is a vertical synchronization interrupt and the first memory; 22 to second memory 2
A CPU 26 performs time-sharing control of writing video data and still image data into the second memory 23 in response to a transfer end interrupt given from the address generation circuit 24 after the end of the video data transfer to the second memory 23. A CPU data bus to which image data is input, 27 is a CPU 25 and a synchronization separation circuit 4
This is a CPU control/address bus that connects the address generation circuit 24 and the address generation circuit 24.

[Operation] The video signal is not directly written into the display memory (second memory 23), but is first stored in the buffer memory (first memory 22). Then, the CPU receives a vertical synchronization signal interrupt given from the synchronization separation circuit 4 and a transfer end interrupt given from the address generation circuit 24 after the video transfer from the first memory 22 to the second memory 23 is completed.
By time-sharing control of 25, video data is written from the first memory 22 to the second memory 23, and the CPU data bus 2
The still image data from 6 is written.

With this configuration, it is possible to access the memory from the outside even while a video is being displayed, and still images can be written, making it possible to display videos and still images simultaneously on the computer display. .

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals. The digital image converter 21 includes a converter 21a that converts from the NTSC system to the RGB system, and an A/D converter 21b that converts the output of the converter 21a into digital data. The first memory 22 is a random memory 22a
and a serial memory 22b, and the second memory 23 is composed of a random memory 23a and a serial memory 23b.

The output of the A/D converter 21b first enters the serial memory 22b, and the data read from the serial memory 22b enters the random memory 22a. On the other hand, in the case of the second memory 23, the random memory 23
The configuration is such that data is moved from a to the serial memory 23b.

The capacities of these memories are, for example, 680 dots x 480 lines for the first memory 22 and 1024 dots x 768 lines for the second memory 23.

30 is a hard disk for storing still image data; 31
is a color scanner that reads still images and outputs them as color image data. 32 is a bidirectional buffer connected between the CPU data bus 26 and the second memory 23. To explain the operation of a circuit configured in this way,
It is as follows.

(Video writing) The conversion unit 21a converts the input video signal from NTSC to RG.
Convert to method B. The converted image signal is converted into digital data by the A/D converter 21b. on the other hand,
The synchronization separation circuit 4 separates a horizontal synchronization signal and a vertical synchronization signal from the video signal and outputs them to the address generation circuit 24. The address generation circuit 24 provides a write/transfer address to the first memory 22. As a result, A/D converter 2
The output of 1b is written for one line into the serial memory 22b in synchronization with the pixel clock. This one line of data is then transferred to the random memory 22a in synchronization with the horizontal synchronizing signal. By repeating this operation for one screen, image data for one screen is stored in the random memory 22a.

The CPU 25 always receives interrupts synchronized with the vertical synchronization signal from the synchronization separation circuit 4, and upon receiving this vertical synchronization signal interrupt, the random memory 22a of the first memory 22 is
The image data is transferred from there to the random memory 23a of the second memory 23. At this time, each memory 22, 23 is given an address from the address generation circuit 24. In this case, the condition is that the transfer time for one screen is completed within 1/60 seconds, and there is no particular need to synchronize with the horizontal and vertical synchronization signals of the video and the personal computer. Address generation circuit 2
4 generates a transfer end interrupt to the CPU 25 when data transfer for one screen is completed. Upon receiving this transfer end interrupt, the CPU 25 moves on to the next operation, for example, writing a still image.

(Still Image Writing) When the CPU 25 receives the transfer end interrupt, it requests the color scanner 31 to transfer data. Upon receiving an image data transfer request from the CPU 25, the color scanner 31 scans the image and sequentially writes the image data into the random memory 23a of the second memory 23. CPU
25 ends the data writing at the time when the vertical synchronization signal interrupt is accepted from the synchronization separation circuit 4. Then, when the transfer end interrupt from the address generation circuit 24 is accepted, the still image writing operation is performed again. That is, if writing of a still image is not completed in one write operation, the above-described write operation is repeated in a time-sharing manner.

(Natural Image Display) The moving image or still image written in the random memory 23a of the second memory 23 is transferred to the serial memory 23b in synchronization with the horizontal synchronization signal of the personal computer. The data transferred to the serial memory 23b is read out in synchronization with the pixel clock of the personal computer, and converted into an analog image signal by the D/A converter 6. This image signal is synthesized with a personal computer video signal by a superimposing circuit 7, and then displayed on a display section (not shown, for example, a CRT) of the personal computer. As a result,
The state of the display section is as shown in FIG. 3, in which a moving image and a still image C are simultaneously displayed in addition to the original image a of the computer.

FIG. 4 is a timing chart showing the operation of the circuit of FIG. 2. (a) is the video vertical synchronization signal, whose period is 1
/60 seconds. A vertical synchronization signal interrupt occurs every 1/60 seconds and is given to the CPU 25. (B) is the video input, and the screen is synchronized with the vertical synchronization signal shown in (B).
1. #2... has changed. (C) shows inter-memory data transfer from the random memory 22a of the first memory (memory 1) to the random memory 23a of the second memory (memory 2). #0. #1... Each time a data transfer is completed, a transfer end interrupt is generated and given to the CPU 25.

(D) indicates a still image writing state. A still image is written to the memory 2 after the transfer end interrupt occurs until the vertical synchronization signal interrupt occurs. In other words, the NOI occurs after the transfer end interrupt occurs until the vertical synchronization signal interrupt occurs.

No. 2, ... and still images are written in a time-sharing manner. For example, one still image is composed of NOI to NO3.

According to the present invention, when data is transferred from the random memory 22a of the memory 1 to the random memory 23a of the memory 2, image data can be enlarged or reduced. When enlarging, the same pixel is transferred horizontally repeatedly,
This can be achieved by repeatedly transferring the same line in the vertical direction.

When shrinking, this is achieved by skipping and increasing transfer addresses, which normally increase by 1, in the horizontal direction to reduce the amount of transfer, and in the vertical direction by skipping lines to reduce the amount of transfer. be able to.

In the above-mentioned embodiment, a case has been described in which still images are read from the color scanner 31, but still image data may be stored in the hard disk 30 in advance and read out sequentially. Further, the contents of the second memory 23 can be transferred to the hard disk 30 while the transfer of the moving image is stopped, and the moving image can be saved as a still image.

[Effects of the Invention] As described above in detail, according to the present invention, video signals are directly displayed in the memory for display (second memory 23).
-1 buffer memory (first memory 2) without writing to
2). Then, after the vertical synchronization signal interrupt given from the synchronization separation circuit 4 and the end of video transfer from the first memory 22 to the second memory 23, the address generation circuit 24
The data is transferred from the first memory 22 to the second memory 23 by time-sharing control of the CPU 25 upon receiving a transfer end interrupt from the CPU 25.
To provide a moving image/still image display device capable of simultaneously displaying moving images and still images on a personal computer image with a simple configuration by writing moving image data to the computer and still image data from a CPU data bus 26. Can be done.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a configuration block diagram showing an embodiment of the invention, Fig. 3 is a diagram showing the display state of a personal computer, and Fig. 4 shows the operation of the circuit shown in Fig. 2. FIG. 5 is a block diagram of a conventional moving image display device, and FIG. 6 is a block diagram of a conventional still image display device. In FIG. 1, 4 is a synchronization separation circuit, 6 is a D/A converter, 21 is a digital image converter, 22 is a first memory, 23 is a second memory, 24 is an address generation circuit, and 25 is a CPU. 26 is a CPU data bus, and 27 is a CPU control/address bus.

Claims (1)

[Claims] A digital image converter (21) that receives a video signal and converts it into a digital image signal, and a first digital image converter (21) that stores the output of the digital image converter (21).
a second memory (23) that stores image data corresponding to a display screen that stores the output of the first memory (22) or image data of a still image; and a second memory (23) that stores image data corresponding to the display screen; a synchronization separation circuit (4) that separates and outputs a horizontal synchronization signal and a vertical synchronization signal;
2), an address generation circuit (24) that provides a write or transfer address to (23), and a D/A converter (6) vertical that converts the output of the second memory (23) into an analog signal and outputs it as a video signal. Synchronous interrupt and first memory (22) to second memory (23)
Address generation circuit (24) after video data transfer to
A moving image/still image display device comprising a CPU (25) that performs time-sharing control of writing moving image data and still image data into a second memory (23) in response to a transfer end interrupt given from a CPU.