JPH08328528A - Picture processing device - Google Patents

Abstract

PURPOSE: To output full-color or monochromatic picture data as video data by performing the picture processing of inputted full-color or monochromatic picture data at high speed. CONSTITUTION: This device is provided with a full-color picture processing circuit 9 and a monochromatic picture processing circuit 10 respectively performing prescribed picture processings with respect to full-color data having a stipulated bit constitution and monochromatic data having one bit constitution, a first DMA control circuit 6a transferring inputted full-color data or monochromatic data to respective picture processing circuits 9, 10, a first picture transformation circuit 12 transforming the full-color data subjected to the picture processing in the full-color picture processing circuit 9 into pseudo color data, a second picture transformation circuit 13 transforming the monochromatic data subjected to the picture processing in the monochromatic picture processing circuit 10 into pseudo color data and a second DMA control circuit 16b transferring pseudo color data transformed in respective picture transformation circuits to an intermediate bit frame buffer 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs predetermined image processing on input image data, converts the image-processed image data into video data to be sent to a display device such as a CRT, and outputs the video data. An image related to an image processing device, in particular, an image for performing image processing (compression / expansion, enlargement / reduction / rotation) on full-color data and monochrome data at high speed by DMA transfer, and efficiently creating video data for display. Regarding a processing device.

[0002]

2. Description of the Related Art When image data is handled as digital data, data in which the color of one pixel is handled by 24 bits which is a prescribed bit is called full color data. In this case, the color is separated into three colors of R, G and B, and each color is represented by 8-bit data (256 levels).

However, when the specified 24-bit full color data is handled by a personal computer or a workstation, the data processing load is significantly increased. Therefore, in a computer such as a personal computer or a workstation, the color of one pixel is 4 bits (16
Color) or pseudo-color data having an intermediate bit structure smaller than the specified bit such as 8 bits (256 colors).

An image processing apparatus which handles such color data as pseudo color data is constructed as shown in FIG. 3, for example. To the system bus 1, a CPU 2 that executes various types of information processing, a main memory 3, and an intermediate bit frame buffer 4 are connected. Further, an input bus 7 and an output bus 8 are connected to the system bus 1 via a pair of FIFO memories 5a and 5b. Further, a full-color image processing circuit 9 and a monochrome image processing circuit 10 are connected between the input bus 7 and the output bus 8. Furthermore, each FI
First and second DMA control circuits 6a and 6b are connected to the FO memories 5a and 5b.

Also, the intermediate bit frame buffer 4
D / A via an image conversion circuit 11 (third image conversion circuit) for converting pseudo color data into full color data.
The conversion circuit 12 is connected.

[0006] Digital full-color data having a specified bit (24 bits) or digital monochrome data having a 1-bit structure is input to the input device (not shown) from the outside of the image processing device having the above structure. The first DMA control circuit 6a sends out the input full-color data or monochrome data to the input bus 7 via the FIFO memory 5a.

The full-color data sent to the input bus 7 is subjected to the above-mentioned predetermined image processing (compression / expansion, enlargement / reduction / rotation) in the full-color image processing circuit 9, and the image-processed full-color data is output to the output bus 8. Output up. Similarly, the monochrome data sent to the input bus 7 is subjected to the above-described predetermined image processing in the monochrome image processing circuit 10, and the image-processed monochrome data is output to the output bus 8.

The second DMA control circuit 6b sends out the full-color data or monochrome data output onto the input output bus 8 onto the system bus 1 via the FIFO memory 5b.

The CPU 2 converts the image-processed full-color data having a defined bit (24 bits) transmitted to the system bus 1 into pseudo-color data having an intermediate bit (8 bits) and converts one display screen ( The image data of one frame is written in the intermediate bit frame buffer 4.

Further, the CPU 2 converts the image-processed 1-bit monochromatic data sent to the system bus 1 into intermediate-bit (8-bit) pseudo-color data to convert one display screen (one frame). Min) image data is written in the intermediate bit frame buffer 4. In addition,
When the monochrome data of 1-bit structure is converted into the pseudo color data of the intermediate bit (8 bits), the converted 8-bit pseudo color data is composed of only two kinds of values.

The CPU 2 sends out a read command for one screen worth of pseudo color data written in the intermediate bit frame buffer 4 as required. Then, the pseudo color data written in the intermediate bit frame buffer 4 is sequentially read and input to the next image conversion circuit 13.

The image conversion circuit 13 converts the input pseudo color data having an intermediate bit (8 bits) into regular bits (2
Convert to full color data of 4 bits). In addition,
When 8-bit pseudo color data is converted to 24-bit full color data, the converted 24-bit full color data is composed of only 256 kinds of values. The full-color data output from the image conversion circuit 11 is output to an external CRT display device, for example, as an analog video signal in the next D / A conversion circuit 12.

[0013]

However, the image processing apparatus shown in FIG. 3 still has the following problems to be solved. That is, the specified bit (2
In order to image-process and display 4-bit full-color data or 1-bit monochrome data, it was necessary to temporarily convert the data to pseudo-color data having an intermediate bit (8 hits) structure after image processing.

In this case, regarding image processing, hardware dedicated to image processing for full-color data and monochrome data represented by the full-color image processing circuit 9 and the monochrome image processing circuit 10 has already been developed.

Regarding display, the intermediate bit frame buffer 4 for pseudo color data and the display circuit have already been developed. However, even if the dedicated image processing circuit 9,
Even if image processing is performed at high speed using 10, when displaying, once converted to displayable pseudo color data,
It is necessary to temporarily store in the intermediate bit frame buffer 4 for display. Therefore, not only the processing load on the CPU 2 is increased, but also the data processing efficiency of the entire image processing apparatus is lowered.

Further, although the image data finally output from the image processing apparatus is full color data having a defined bit (24 bits), it is equal to or larger than the number of bits (intermediate bit = 8 bits) of the pseudo color data. Since there is no color type, there is a problem that the color image quality is significantly reduced as compared with the full-color image data input to the image processing apparatus.

The present invention has been made in view of the above circumstances, and can reduce the processing load on the CPU and can perform high-speed video data for displaying image processing of full-color data and monochrome data and image-processed data. An object of the present invention is to provide an image processing device that can be created by It is another object of the present invention to provide an image processing device capable of outputting high quality video data as needed.

[0018]

In order to solve the above-mentioned problems, the invention of claim 1 is directed to a full-color image processing circuit or a monochrome for full-color data of a specified bit structure or monochrome data of a 1-bit structure inputted from the outside. After performing a predetermined image processing in the image processing circuit, each is converted into pseudo color data of intermediate bit configuration less than the specified bit and stored in the intermediate bit frame buffer, and then
In the image processing apparatus for reading out the pseudo color data stored in the intermediate bit frame buffer as necessary, converting it into full color data and outputting it as video data, the input full color data or monochrome data is transferred to each image processing circuit. A first DMA control circuit, a first image conversion circuit for converting full-color data image-processed by the full-color image processing circuit into pseudo color data, and monochrome data image-processed by the monochrome image processing circuit for pseudo-color data. And a second DMA control circuit for transferring the pseudo color data converted by each image conversion circuit to the intermediate bit frame buffer.

According to a second aspect of the invention, there is provided a third image conversion circuit according to the first aspect of the invention, which converts the pseudo color data read from the intermediate bit frame buffer into full color data, and the third image. A full color data selection circuit that selects one full color data from the full color data converted by the conversion circuit and the full color data image-processed by the full color image processing circuit, and the full color data selected by this full color data selection circuit is stored, A full-color frame buffer that outputs the stored full-color data as video data is provided as necessary.

Further, according to the invention of claim 3, in the invention of claim 2, there is provided a fourth image conversion circuit for converting the monochrome data image-processed by the monochrome image processing circuit into full color data, and further, full color The data selection circuit includes one full color data from the full color data converted by the third image conversion circuit, the full color data image-processed by the full color image processing circuit, and the full color data image-processed by the third image conversion circuit. Select.

According to a fourth aspect of the present invention, in the second aspect of the present invention, an image conversion processing unit for converting an externally input analog video signal into full color data having a prescribed bit structure is provided, and further full color data selection is performed. The circuit selects one full color data from the full color data converted by the third image conversion circuit, the full color data image-processed by the full color image processing circuit, and the full color data converted by the image conversion processing unit.

[0022]

In the image processing apparatus thus constructed, the full color image data or monochrome image data input from the outside is transferred to the full color image processing circuit or the monochrome image processing circuit by the first DMA control circuit, and the full color image processing is performed. After the image is processed by the circuit or the monochrome image processing circuit, it is converted into pseudo color data having an intermediate bit configuration by the first image conversion circuit or the second image conversion circuit. The converted pseudo color data is transferred to the intermediate bit frame buffer by the second DMA control circuit.

Therefore, the image-processed full-color data or monochrome data is converted into pseudo-color data by a dedicated conversion circuit, so that no processing load is imposed on the CPU. In addition, the converted pseudo color data is the second DM.
Since it is transferred to the intermediate bit frame buffer by the A control circuit, the processing load on the CPU is further reduced. As a result, the processing speed of the entire image processing apparatus increases.

According to the second aspect of the invention, in addition to the intermediate bit frame buffer, a full color frame buffer for storing full color data is provided. Also,
A full color data selection circuit for selecting full color data to be written in this full color frame buffer is provided.

The full color data to be written in the full color frame buffer is selectively set between the full color data data converted from the pseudo color data in the intermediate bit frame buffer or the full color data image-processed by the full color image processing circuit. .

That is, an image reproduced from the pseudo color data or a high quality image reproduced from the original full color data can be selected as needed. According to the invention of claim 3, full color data written into the full color frame buffer is converted from pseudo color data in the intermediate bit frame buffer, full color data image-processed by the full color image processing circuit, and a monochrome image processing circuit. The output monochrome data can be selected from the full-color data converted by the fourth image conversion circuit.

Further, in the invention of claim 4, full color data to be written in the full color frame buffer is converted from pseudo color data in the intermediate bit frame buffer, full color data image-processed by the full color image processing circuit, and It is possible to select between full color data obtained from an analog video signal input from the outside. Therefore, the selection range of the video data output from this image processing device is further expanded.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the schematic arrangement of the image processing apparatus according to the embodiment. The same parts as those of the conventional image processing apparatus shown in FIG. 3 are designated by the same reference numerals. Therefore, detailed description of the overlapping portions will be omitted.

The output terminal of the full-color image processing circuit 9 is connected to a first image conversion circuit 12 for converting full-color data having a specified bit (24 bits) into pseudo-color data having an intermediate bit (8 bits). The display bus 15 is connected to the output terminal of the first image conversion circuit 12. Further, a bypass circuit for outputting the output of the full-color image processing circuit 9 directly to the display bus 15 is provided.

Similarly, the output terminal of the monochrome image processing circuit 10 has a second image conversion circuit 13 for converting monochrome data of 1-bit structure to pseudo color data of intermediate bit (8 bits), and 1-bit structure. A fourth image conversion circuit 14 for converting monochrome data into full-color data having a defined bit (24 bits) is connected, and a display bus 15 is connected to the output terminals of the second and fourth image conversion circuits 13, 14. It

The display bus 15 is connected to a full color data selection circuit 17 via an address generation circuit 16.
The full color data selection circuit 17 is connected to the full color frame buffer 18. Address generation circuit 16
Is a specified bit (24 bits output on the display bus 15).
An address is generated when full-color data of bit structure is written in the full-color frame buffer 18.

The system bus 1 has the above-mentioned CPU 2,
In addition to the main memory 3 and the intermediate bit frame buffer 4, a mask frame memory 19, a cursor frame memory 20 and a memory control circuit 24 are connected.

The masking frame memory 19 is used to set a masking area when a part of the display screen is masked when another data such as a message or a window is displayed on the display screen. For example,
It is possible to mask a part of the intermediate bit frame buffer 4 with an arbitrary graphic (rectangular) pattern in the frame memory of 1 bit length corresponding to the intermediate bit frame buffer 4. CPU 2 to mask frame memory 1
The mask data set to 9 is sent to the mask circuit 21.

One frame of pseudo color data output from the intermediate bit frame buffer 4 is masked by the mask circuit 21.
Then, the mask area portion is removed and input to the next third image conversion circuit 11. The third image conversion circuit 11 converts the input pseudo color data having an intermediate bit (8 bits) structure into full color data having a specified bit (24 bits) structure.

1 output from the third image conversion circuit 11
The full color data for the frame is generated by the address generation circuit 22.
Is input to. The address generation circuit 22 generates an address for writing the input full-frame data for one frame into the full-color frame buffer 18 described above.

The cursor frame memory 20 connected to the system bus 1 stores a cursor image when the cursor is displayed on the display screen. The full color data indicating the cursor image stored in the cursor frame memory 20 is input to one end of the display priority circuit 23.

The memory control circuit 24 controls the read timing of the frame buffers 4 and 18 and the frame memories 19 and 20 based on the instruction from the CPU 1. Also,
A selection command is sent to the full color data selection circuit 17.

When the full-color data read from the full-color frame buffer 18 and the cursor image data read from the cursor frame memory 20 conflict with each other, the display priority circuit 23 gives priority to the cursor image data and moves to the next. It is sent to the D / A conversion circuit 12.

The D / A conversion circuit 12 is a display priority circuit 23.
The full-color data as the video data output from the device is converted into an analog video signal, for example, C (not shown).
Output to RT display device.

Next, the operation of the image processing apparatus thus configured will be described. (1) First, a case will be described in which digital full-color data having a specified bit (24 bits) structure input from the outside is once converted into pseudo-color data and then displayed in full-color data.

In this case, the first DMA control circuit 6a sends the full color data input to the input device to the input bus 7 via the FIFO memory 5a. The full-color data sent to the input bus 7 is subjected to predetermined image processing (compression / expansion, enlargement / reduction / rotation) in the full-color image processing circuit 9.
Is applied. The full-color data image-processed by the full-color image processing circuit 9 is converted into pseudo-color data having an intermediate bit (8 bits) by the first image conversion circuit 12 and sent to the image bus 15.

The pseudo color data on the image bus 15 is transferred to the output bus 8. The second DMA control circuit 6b writes the pseudo color data on the output bus 8 into the intermediate bit frame buffer 4 via the FIFO memory 5b and the system bus 1.

The CPU 2 controls the memory control circuit 24 to read the pseudo color data written in the intermediate bit frame buffer 4. At the same time, the full color data selection circuit 17 is instructed to select full color data from the address generation circuit 22.

The pseudo color data read from the intermediate bit frame buffer 4 is subjected to a masking process on a necessary area by a mask circuit 21, and then converted into full color data of a prescribed bit (24 bits) by a third image conversion circuit 11. The address generating circuit 22 adds a necessary address value to the full-color data selecting circuit 17.

Since the full color data selection circuit 17 selects the color data from the intermediate bit frame buffer 4, the full color data output from the address generation circuit 22 is written in the full color frame buffer 18.
The full-color data read from the full-color frame buffer 18 is replaced with a cursor image in the display priority circuit 23 when necessary, converted into an analog video signal in the D / A conversion circuit 12, and displayed on a CRT display device (not shown). To be done.

(2) Next, a case will be described in which the digital full-color data of a specified bit (24 bits) structure input from the outside is directly displayed without being converted into the pseudo-color data.

In this case, the CPU 2 has the memory control circuit 2
4, the full color data selection circuit 17 is instructed to select the full color data from the address generation circuit 16. Then, the full color data subjected to the image processing by the full color image processing circuit 9 is directly sent to the image bus 15. The full-color data output to the image bus 15 is added with a necessary address value in the address generation circuit 16 and input to the full-color data selection circuit 17.

Since the full-color data selection circuit 17 selects the full-color data from the full-color image processing circuit 9, the full-color data output from the address generation circuit 16 is written in the full-color frame buffer 18.
The subsequent steps are the same as in (1).

(3) Next, a case will be described in which digital monochrome data of 1-bit structure inputted from the outside is once converted into pseudo color data and then displayed in full color data.

In this case, the first DMA control circuit 6a converts the monochrome data input to the input device into the FIFO memory 5
It is sent to the input bus 7 via a. The monochrome data sent to the input bus 7 is subjected to predetermined image processing (compression / expansion, enlargement / reduction / rotation) by the monochrome image processing circuit 10. The monochrome data image-processed by the monochrome image processing circuit 10 is converted by the second image conversion circuit 13 into pseudo color data having an intermediate bit (8 bits) and sent to the image bus 15.

The pseudo color data on the image bus 15 is transferred to the output bus 8. The second DMA control circuit 6b writes the pseudo color data on the output bus 8 into the intermediate bit frame buffer 4 via the FIFO memory 5b and the system bus 1.

The subsequent steps are the same as in the case of (1). (4) Next, the monochrome data input from the outside is
A case will be described in which the data is directly converted into full-color data and displayed without being converted into pseudo-color data.

In this case, the CPU 2 uses the memory control circuit 2
4, the full color data selection circuit 17 is instructed to select the full color data from the address generation circuit 16. Then, the 1-bit monochromatic data image-processed by the monochromatic image processing circuit 9 is converted by the fourth image conversion circuit 14 into full-color data of a prescribed bit (24 bits), and then sent to the image bus 15. The full-color data output to the image bus 15 is added with a necessary address value in the address generation circuit 16 and input to the full-color data selection circuit 17.

Since the full-color data selection circuit 17 selects the full-color data from the full-color image processing circuit 9, the full-color data output from the address generation circuit 16 is written in the full-color frame buffer 18.
The subsequent steps are the same as in (1).

In the explanation of (1) to (4),
Initially, full-color data or monochrome data is input to an input device (not shown), and the case where it is transferred from the input device to the input bus 7 by the first DMA control circuit 6a has been described. For example, each image data is input. In some cases, it has been written and already written in the main memory 3. In this case, the data is transferred from the main memory 3 onto the input bus 7 by the first DMA control circuit 6a.

The image processing apparatus configured as described above has the following features. (A) Full-color image processing circuit 9 input from the outside
Alternatively, full-color data or monochrome data image-processed by the monochrome image processing circuit 10 is converted into pseudo color data having a specified bit (8 bits) by dedicated first and second image conversion circuits 12 and 13, respectively. And
The data is directly transferred to the intermediate bit frame buffer 4 by the second DMA control circuit 6b.

Therefore, the CPU 2 does not need to execute the image conversion process and the image data transfer process.
The processing load of No. 2 can be greatly reduced, and the image processing speed can be greatly improved because the dedicated image conversion circuit and DMA control circuit are used.

(B) The purpose of temporarily converting the image-processed full-color data or monochrome data into pseudo-color data having an intermediate bit structure and storing it in the intermediate-hit frame buffer 4 is that the CPU 2 compresses / expands / expands / decompresses as described above.
This is to improve the efficiency of data processing when executing processing other than standardized image processing such as reduction / rotation. However, when the CPU 2 does not need to process the data separately, it is not necessary to go through the intermediate hit frame buffer 4.

In this case, the full color data image-processed by the full color image processing circuit 9 is directly supplied to the full color frame buffer 18 via the full color data selection circuit 17.
Is written to. Since the full-color data written in the full-color frame buffer 18 has the color type 2 ²⁴ of the original full-color data that has been input, it is once compressed (converted) into 8-bit (intermediate bit) pseudo-color data and then re-converted. compared to the color type 2 ⁸ when elongated to full-color data (conversion), the image quality of the final image displayed on the CRT ideographic device can be greatly improved.

(C) Further, it is necessary to output the full color data subjected to the image processing in the full color processing circuit 9 directly as video data, or to once convert it into pseudo color data and then convert it into full color data again and output it. It can be arbitrarily selected according to.

(D) Further, the mask frame memory 1
Since 9 and the frame memory 20 for cursor are provided,
It is also possible to partially trim the display screen or display a cursor on the display screen based on an instruction from the CPU 2.

FIG. 2 is a block diagram showing the schematic arrangement of an image processing apparatus according to another embodiment of the present invention. The same parts as those of the apparatus of the embodiment shown in FIG. 1 are designated by the same reference numerals. Therefore, detailed description of the overlapping portions will be omitted.

In the apparatus of this embodiment, the pseudo color data having the intermediate bit (8 pits) read from the intermediate bit frame buffer 4 is converted into the third image conversion circuit 11.
Is immediately converted into full color data having a specified bit (24 bits) structure. Converted full color data is D / A
The conversion circuit 25 converts the analog video signal.

This intermediate bit frame buffer 4, third
The analog video signal supplied from the video signal supply circuit 29 including the image conversion circuit 11 and the D / A conversion circuit 25 of FIG. 1 is sent to the A / D conversion circuit 27 after the sync signal is extracted by the sync signal separation circuit 26. Is entered. A / D circuit 27
Synchronizes with the horizontal and vertical synchronizing signals which are correctly synchronized and controlled by the PLL circuit 28, and converts the input analog video signal into full color data having a prescribed bit (24 bits) and sends it to the mask circuit 21.

The mask circuit 21 masks the full color data corresponding to the mask area designated in the mask frame memory 19 and sends it to the next address generation circuit 22. Subsequent configurations and operations are the same as those of the practical example device of FIG.

In this image processing apparatus, the video signal from the TV camera 30 arranged outside is input to the A / D conversion circuit 32 after the sync signal is extracted by the sync signal separation circuit 31. . The A / D circuit 32 is the PLL circuit 3
In synchronism with the horizontal and vertical synchronizing signals correctly controlled in 3, the input analog video signal is converted into digital color data and input to the next color conversion circuit 34.

The color conversion circuit 34 converts the input digital color data into R. Each of the G and G colors is converted into full-color data having a total of 24 bits with 8 bits each and sent to the address generation circuit 35. The address generation circuit 35 sets a storage address in the full-color frame buffer 18 of full-color data for one screen obtained by the TV camera 30, and sends it to the next full-color data selection circuit 17.

Sync signal separation circuit 31, A / D conversion circuit 3
2, the PLL circuit 33, and the color conversion circuit 34 constitute an image conversion processing unit that converts an analog video signal into full color data having a specified bit configuration.

In the video processing device having such a configuration, the video signal supply circuit 29 is provided with a T such as a VTR device.
By using a device that outputs a video signal that has been captured by the V camera, it is possible to display and output the reproduced image of the VTR on the CRT display device via this video processing device.

Further, the CPU 2 uses the memory control circuit 24 in advance.
To the full color data selection circuit 17 via the TV
If a command for selecting full-color data from the camera 30 is sent, the image captured by the TV camera 30 will be transferred to the full-color frame buffer 1 via the color conversion circuit 34, the address generation circuit 35, and the full-color data selection circuit 17.
Written to 6. Therefore, the image taken by the TV camera 30 can be CR-reproduced in real time through this video processing device.
Display output is possible on the T display device.

[0071]

As described above, in the image processing apparatus of the present invention, dedicated image conversion for converting the image-processed full-color data and monochrome data into intermediate-bit pseudo-color data is provided, and the converted pseudo-data is converted. The color data is directly transferred to the intermediate bit frame buffer using the DMA control circuit.

Therefore, the processing load on the CPU can be reduced, and the video data for displaying the image processing of the full-color data and the monochrome data and the image-processed data can be created at high speed.

Further, the image-processed full color data is directly output as video data without being once converted into pseudo color data. Therefore, high-quality video data can be output as needed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of an image processing apparatus according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of a conventional image processing apparatus.

[Explanation of symbols]

1 ... System bus, 2 ... CPU, 3 ... Main memory, 4 ... Intermediate bit frame buffer, 5a, 5b ... FIFO memory, 6a ... 1st DMA control circuit, 6b ... 2nd DMA
Control circuit, 9 ... Full color image processing circuit, 10 ... Monochrome image processing circuit, 11 ... Third image conversion circuit, 12 ... First image conversion circuit, 13 ... Second image conversion circuit, 14 ...
Fourth image conversion circuit, 16, 22, 35 ... Address generation circuit, 17 ... Full color data selection circuit, 18 ... Full color frame buffer, 24 ... Memory control circuit, 30 ...
TV camera

Claims (4)

[Claims] 1. A full-color image processing circuit or a monochrome image processing circuit performs predetermined image processing on full-color data having a specified bit structure or monochrome data having a 1-bit structure, which is input from the outside. Converted to pseudo color data with a small number of intermediate bits and stored in the intermediate bit frame buffer, and then read the pseudo color data stored in this intermediate bit frame buffer as necessary and converted to full color data as video data. In an image processing apparatus for outputting, a first DMA control circuit for transferring the input full color data or monochrome data to each of the image processing circuits, and full color data image-processed by the full color image processing circuit for the pseudo color data. A first image conversion circuit for converting to A second image conversion circuit for converting the monochrome data image-processed by the monochrome image processing circuit into the pseudo color data, and the pseudo color data converted by each image conversion circuit is transferred to the intermediate bit frame buffer. Second DM
An image processing apparatus including an A control circuit. 2. A third image conversion circuit for converting pseudo color data read from the intermediate bit frame buffer into full color data, full color data converted by the third image conversion circuit, and the full color image processing circuit. A full color data selection circuit that selects one full color data from the image processed full color data, and the full color data selected by this full color data selection circuit is stored. The image processing apparatus according to claim 1, further comprising a full-color frame buffer that outputs the image. 3. A fourth image data converting device for converting monochrome data image-processed by the monochrome image processing circuit into full-color data.
The full-color data selection circuit includes full-color data converted by the third image conversion circuit, full-color data image-processed by the full-color image processing circuit, and the third image conversion circuit. 3. The image processing apparatus according to claim 2, wherein one full color data is selected from the full color data subjected to the image processing in. 4. An image conversion processing unit for converting an analog video signal input from the outside into full color data having a specified bit configuration, wherein the full color data selection circuit is converted by the third image conversion circuit. 3. The image processing apparatus according to claim 2, wherein one full color data is selected from full color data, full color data image-processed by the full color image processing circuit, and full color data converted by the image conversion processing unit. .