JP3855988B2 - Video display method - Google Patents

Description

  The present invention relates to a method for simultaneously displaying a moving image and a still image on a display device of a computer system.

  FIG. 12 is an explanatory diagram illustrating a state in which a still image and a moving image are simultaneously displayed in one window of the display device. In order to realize such display, conventionally, an overlay technique is used in which a still image and a moving image are stored in separate video memories and are combined at the time of display.

  By the way, in a multi-window system such as MS-WINDOWS (trademark of Microsoft Corporation), the size of each window can be changed. When changing the size of the window, there are a method of widening the range of the video displayed in the window without changing the magnification of the video and a method of scaling the video without changing the display range of the video .

  However, with the conventional overlay technology, it is difficult to display a still image and a moving image while simultaneously scaling when changing the window size.

The present invention has been made to solve the above-described problems in the prior art, and an object thereof is to provide a new technique for displaying still images and moving images.

In order to solve at least a part of the problems described above, the video display method of the present invention is a method of displaying video on a display device,
(A) preparing in advance a plurality of still images and a moving image corresponding to each still image;
(B) displaying the plurality of still images on the display device;
(C) receiving a selection of one still image from the plurality of still images by a user;
(D) displaying a moving image corresponding to the selected still image on the display device;
Is provided .

The moving image may be displayed simultaneously with the plurality of still images.

  In addition, the step (a)
  A step of writing key data indicating a superimpose area in a first video memory having a memory space corresponding to a display screen of the display device;
  The step (b)
  Writing still image video signals of the plurality of still images in a still image area in a second video memory;
With
  The step (d)
(D1) The video image signal is continuously written in the moving image area in the second video memory, and is written in the area including the still image area and the moving image area in the second video memory. Reading out the video signal of 1;
(D2) obtaining a second video signal by scaling the video represented by the first video signal;
(D3) A fourth video signal is obtained by synthesizing the second video signal in the superimpose area of the video represented by the third video signal read from the first video memory. Process,
(D4) displaying the scaled moving image and still image on the display device by supplying the fourth video signal to the display device;
(D5) changing the key data stored in the first video memory so as to scale the superimpose area with the changed magnification when the scaling magnification is changed;
May be provided.

In this way, even if the scaling ratio of the still image and the moving image is changed, the superimpose area is scaled at the same magnification, so that the display portion of the still image and the moving image is kept the same as before the scaling.

A. Overall configuration of the device:
Next, embodiments of the present invention will be described based on examples. FIG. 1 is a block diagram showing the configuration of a computer system to which one embodiment of the present invention is applied. The computer system includes a bus 610, a CPU 620, a main memory 630, a peripheral controller 640, a composite I / O port 650, a network interface 656, a video controller 660, and a first video RAM (VRAM) 670. The video transfer controller 680 and the video processing circuit 800 are connected. The video processing circuit 800 has a second video RAM 310 therein. The first VRAM 670 has a memory area corresponding to the display area of the color CRT 701 on a one-to-one basis.

  A keyboard 642 and a mouse 644 are connected to the peripheral controller 640. Further, a floppy disk device 652 and a hard disk device 654 are connected to the composite I / O port 650.

  A color CRT 701 (or color liquid crystal display) as a display device is connected to the video controller 660. The video controller 660 has a function of writing video data of a still image in the first VRAM 670 and reading a video signal from the first VRAM 670 and supplying the video signal to the video processing circuit 800. The video controller 660 further has a function of generating a synchronization signal SYNC (vertical synchronization signal VSPC and horizontal synchronization signal HSPC) and supplying the same to the color CRT 701 and the video processing circuit 800.

  Connected to the video transfer controller 680 is a CD-ROM device 682 as a moving image video data supply device. The video transfer controller 680 has a function as a processor that transfers moving image video data given from the CD-ROM device 682 to the second VRAM 310 via the bus 610.

  The video processing circuit 800 has a function of combining a moving image video signal and a still image video signal and supplying a video signal representing the combined video to the color CRT 701. The video processing circuit 800 has a function of simultaneously enlarging / reducing a still image and a moving image by scaling the synthesized video signal.

B. Internal configuration of the video processing circuit 800:
FIG. 2 is a block diagram showing the internal configuration of the video processing circuit 800. The configuration of the video processing circuit 800 is the same as that shown in FIG. 4 of Japanese Patent Laid-Open No. 2-298176 disclosed by the applicant.

  The video processing circuit 800 includes an audio unit ACU that handles audio signals, an analog unit ANU that handles analog video signals such as television signals, a video memory unit IMU, and a writing that controls writing of video data to the video memory unit IMU. It has a control unit WCU, a read control unit RCU that reads out video data stored in the video memory unit IMU, and a video playback unit IRU that plays back video.

  The audio unit ACU includes an audio input terminal 101, an audio signal selection circuit 110, a volume control circuit 120, and an audio output terminal 102. The audio input terminal 101 receives an audio signal ASEX given from a video signal supply device such as a video player. The audio signal selection circuit 110 selects and outputs one of the audio signal ASEX and the audio signal ASTV input from the TV tuner 710 of the analog unit ANU. Note that the channel selection in the TV tuner 710 is instructed by the CPU 620. The volume of the selected audio signal is adjusted by the volume control circuit 120 and output from the audio output terminal 102. The audio signal ASMON output from the audio output terminal 102 is given to the audio input terminal of the color CRT 701 or the speaker.

  The analog unit ANU includes a TV tuner 710, a TV antenna 711, a video input terminal 103, a video signal selection circuit 130, a video signal decoder 140, an AD converter 210, and a digitizing control circuit 220. . The video signal VSEX given from the moving picture signal supply device is input to the video input terminal 103. The video signal selection circuit 130 selects and outputs one of the video signal VSEX and the video signal VSTV given from the TV tuner 710 instructed by the CPU 620. The selected video signal is separated by the video signal decoder 140 into a video signal LSTV and a synchronization signal SSTV. This video signal LSTV is a color signal of three primary colors of RGB. The AD converter 210 converts the video signal LSTV, which is an analog signal, into a digital signal and supplies it to the write control unit WCU. The digitizing control circuit 220 controls the AD converter 210 based on the synchronization signal SSTV, and controls the VRAM 310 via the write control unit WCU.

  The write control unit WCU includes a video data selection circuit 320, a video memory control signal selection circuit 330, and a write control circuit 340. The video data selection circuit 320 outputs the output of the AD converter 210 that receives the video signal LSTV in response to the write selection signal CC output from the write control circuit 340 and the CPU 620 from an external device such as an external storage device. One of the read video signals LSWPC is selected and output. The video memory control signal selection circuit 330 selects one of the video memory control signal WETV output from the digitizing control circuit 220 and the video memory control signal WEPC output from the write control circuit 340 according to the write selection signal CC. And output. The write control circuit 340 controls the operation of writing the video signal LSWPC supplied from the CPU 620 or the video transfer controller 680 to the video memory unit IMU.

  The read control unit RCU includes a read control circuit 350, a first-in first-out memory (FIFO memory) 360, and a FIFO read control circuit 370. The video signal LSFIF read from the video memory unit IMU by the FIFO read control circuit 370 is stored in the FIFO memory 360. Video signal LSFIF stored in FIFO memory 360 is read out externally by read control circuit 350. The read control unit RCU is used when video data stored in the video memory unit IMU is output to an external device in accordance with a command from the CPU 620.

  The video memory unit IMU has a 3-port VRAM 310 having one write port and two read ports. As the 3-port VRAM 310, CXK1206 manufactured by Sony Corporation or MB81C1501 manufactured by Fujitsu Limited can be used. The configuration and function of the 3-port VRAM 310 are described in Japanese Patent Laid-Open No. 2-298176 disclosed by the applicant of the present invention, and thus the description thereof is omitted here. The VRAM 310 is not particularly limited to three ports and may be any memory that stores video data.

  The video reproduction unit IRU has a function of synthesizing the video signal LSPC output from the video controller 660 and the video signal LSMEM output from the VRAM 310 to generate a composite video signal LSMON and outputting this to the color CRT 701.

Each signal in the video reproduction unit IRU represents the following contents.
LSPC: a video signal output from the video controller 660.
LSMEM: a video signal read from the VRAM 310.
LSDA: Analogized video signal.
LSMON: A composite video signal representing video displayed on the color monitor 701.

  CNT: a switching signal for switching the video switch 510. When the switching signal CNT is at the H level, the video signal LSDA is selected, and when the switching signal CNT is at the L level, the video signal LSPC is selected.

SENBL: A first permission signal for designating whether or not superimposition is possible. The first permission signal SENBL is switched to the H level when the operator designates the superimpose mode using the keyboard 642 or the mouse 644, and is switched to the L level when the superimpose mode is designated.
SSENBL: a second permission signal indicating the timing corresponding to the superimpose area on the screen. The second permission signal SSENBL is at the H level within the superimpose area, and is at the L level outside the superimpose area. The superimpose area is designated on the screen of the color monitor 701 by the operator.
NENBL: a third permission signal indicating whether multiple superimposition is possible. The third permission signal NENBL indicates whether or not the video signal LSPC is further superimposed on a part of the video signal LSDA superimposed on the video signal LSPC.

COMP: a signal indicating a region of multiple superimpose. The level of the comparison signal COMP is determined by comparing the video signal LSPC with a predetermined reference voltage Vr, and becomes H level in a region where the video signal LSPC is superimposed on a part of the video signal LSDA. The comparison signal COMP is validated when the permission signal CENBL described below is at the H level, and becomes the third permission signal NENBL.
CENBL: A permission signal for designating whether or not multiple superimposition is possible. The level of the enable signal CENBL is switched by the operator.

  The DA converter 410 in the video reproduction unit IRU converts the video signal LSMEM read from the VRAM 310 into an analog signal and supplies the analog signal to the video switch 510. The video switch 510 selects one of the video signal LSPC output from the video controller 660 and the video signal LSDA output from the DA converter 410 and supplies it to the color CRT 701 as a composite video signal LSMON. A selection signal CNT of the video switch 510 is an output signal of the AND circuit 451.

  The superimpose control circuit 420 has a function of reading the video signal stored in the VRAM 310 in the video processing circuit 800 and scaling the video represented by the video signal.

B. Detailed configuration and operation of the superimpose control circuit 420:
FIG. 3 is a block circuit diagram of the superimpose control circuit 420 and its peripheral circuits. The three-port VRAM 310 shown here uses a read port among the three input / output ports. On pages 27 to 31 of data sheet number 71215-ST of Sony CXK1206, a timing chart relating to the above-described read port is described. The port to be used is the read port 1 on the second page of the data sheet.

  In the three-port VRAM 310, the memory drive clock signal HDCK is perpendicular to the port 1 shift signal terminal CKR1, the memory vertical / horizontal reset signal MRST is perpendicular to the port 1 vertical clear terminal VCLR1, and the horizontal reset signal HRST is perpendicular to the port 1 horizontal clear terminal HCLR1. The offset signal VROFT or the vertical read line clock signal VRLCK is supplied to the port 1 line increment terminal INC1, and the port 1 output enable RE1 (negative logic) is supplied to the port 1 output enable terminal RE1 (negative logic). Further, the analog RGB signal LSMEM (one data in each of R, G and B) is read from the port 1 data outputs DO10 to DO13.

  Analog RGB signals that are read-controlled by the port 1 shift signal CKR1, port 1 vertical clear VCLR1, port 1 horizontal clear signal HCLR1, port 1 line increment signal INC1, and port 1 output enable RE1 (negative logic) corresponding to the above terminals. The LSMEM is output from the port 1 data outputs DO10 to DO13, for example, in 4 bits for each of R, G, and B.

  The video switch 510 outputs the input of the A terminal or the B terminal from the common terminal C by the switching signal VSEL input to the switching signal input terminal CNT. Specifically, the input of the B terminal is output from the C terminal when the switching signal VSEL is at the high level “H”, and the input of the A terminal is output from the C terminal when the switching signal VSEL is at the low level “L”. The CPU 620 controls each unit via a bus 610 in the personal computer.

  421 in FIG. 3 indicates a horizontal reference read dot clock generator that outputs a horizontal reference read dot clock signal HBDCK, and 422 indicates a horizontal read start counter that outputs a horizontal read start signal HRSA and a horizontal read direction reset signal HRST. Indicates a horizontal 64 clock counter that outputs a horizontal reference start signal HRSB, 424 indicates a horizontal read number counter that outputs a horizontal read number signal HRT, and 425 indicates a horizontal read dot clock generator that outputs a horizontal read dot clock signal HDDA. Indicates. The vertical read offset counter 426 outputs a vertical read offset signal VROFT that determines the offset line of the vertical read line of the 3-port VRAM 310 with a count number synchronized with the horizontal reference read dot clock generator 421. The vertical blanking number counter 427 outputs a vertical blanking end signal VBE, the vertical read start counter 428 outputs a vertical read start signal VRS, the vertical read number counter 429 outputs a vertical read number signal VRT, and a vertical read line The clock generator 430 outputs a vertical read line clock signal VRLCK. The AND circuit 431 outputs a switching signal VSEL for superimposing the two video signals LSPC and LSDA, and the OR circuit 432 outputs the vertical read offset signal VROFT and the vertical read line clock signal VRLCK as the port 1 line increment signal INC1. The NOR circuit 433 outputs a read enable RE1 signal. Reference numerals 434 and 435 denote tristate circuits, and 436 denotes an inverter circuit.

  The color signal of the video signal LSPC coming from the color signal input terminal 506 is given to the A terminal of the video switch 510. The horizontal synchronization signal HSPC that arrives from the synchronization terminal 507 forming the horizontal synchronization signal of the input terminal 506 includes a horizontal reference readout dot clock generator 421, a horizontal readout start counter 422, a horizontal 64 clock counter 423, a horizontal readout number counter 424, The ranking number counter 427, the vertical reading start counter 428, the vertical reading number counter 429, the vertical reading line clock generator 430, and the vertical synchronization signal VSPC are supplied to the three-port VRAM 310, the vertical reading offset counter 426, and the vertical blanking number counter. 427, the vertical read start counter 428, the vertical read number counter 429, and the vertical read line clock generator 430. The synchronization signals HSPC and VSPC are also sent to the synchronization signal terminals 490 and 491, respectively.

  Here, input / output of the horizontal synchronizing signal HSPC and the vertical synchronizing signal VSPC will be described with reference to FIG. The horizontal synchronizing signal HSPC and the vertical synchronizing signal VSPC are applied to the required circuits shown in FIG. 3 in the synchronizing signal terminals 490 and 491 and the superimpose control circuit 420 via the buffers 62 and 61. The buffers 61 and 62 have functions such as impedance conversion and waveform shaping, and contribute to accurate transmission of the synchronization signal even when the image processing apparatuses are connected in cascade. The horizontal synchronization signal HSPC is supplied to the PLL circuit 63 in the horizontal reference read dot clock generator 421, and a horizontal reference read dot clock HBDCK is generated as a signal defining the horizontal resolution of the entire horizontal screen specified by the CPU 620. .

  The PLL circuit 63 is configured as shown in FIG. That is, the horizontal synchronizing signal HSPC is supplied from the signal line 70 to the phase comparator 71, and the output of the N divider 74 is supplied to the phase comparator 71. The phase comparator 71 compares the phases of these signals. To output a pulse width signal corresponding to the phase difference. The output of the phase comparator 71 is supplied to a low-pass filter 72 and smoothed, and then supplied to a voltage controlled oscillator (VCO) 73. The VCO 73 oscillates at a frequency corresponding to the applied voltage, and is sent to each part as a horizontal reference read dot clock HBDCK, and is also supplied to the N divider 74 and divided to the frequency of the horizontal synchronizing signal HSPC. And returned to the phase comparator 71. As a result, a horizontal reference read dot clock HBDCK synchronized with the horizontal synchronization signal HSPC is created.

  The count values of the horizontal readout start counter 422, the horizontal 64 clock counter 423, and the horizontal readout number counter 424 in the superimpose control circuit 420 of FIG. 3 are reset by the horizontal synchronization signal HSPC. Further, the vertical synchronization signal VSPC arriving from the synchronization terminal 508 is the port 1 vertical clear VCLR1 of the 3-port VRAM 310, the NOR circuit 433, the vertical readout offset counter 426, the vertical blanking number counter 427, the vertical readout start counter 428, the number of vertical readouts The signals are sent to the counter 429, the vertical readout line clock generator 430, and the synchronization signal terminal 491, respectively. The count values of the vertical read offset counter 426, the vertical blanking number counter 427, the vertical read start counter 428, and the vertical read count counter 429 are reset by the vertical synchronization signal VSPC.

  The horizontal reference readout dot clock signal HBDCK generated by the horizontal reference readout dot clock generator 421 is supplied to the horizontal readout start counter 422, the horizontal 64 clock counter 423, the horizontal readout number counter 424, and the vertical readout offset counter 426, and the trie. The clock signal HDCK of the 3-port VRAM 310 is sent to the port 1 shift signal terminal CKR1 of the 3-port VRAM 310 via the state circuit 435.

  The horizontal readout dot clock generator 425 is composed of a PLL circuit that outputs a signal having a frequency N1 times the frequency of the horizontal synchronization signal HSPC with the horizontal readout reference signal HRSB from the horizontal 64 clock counter 423 as a reference. The horizontal read dot clock signal HDDA is output. The horizontal read dot clock signal HDDA generated by the horizontal read dot clock generator 425 is converted into the clock signal HDCK of the 3-port VRAM 310 via the tristate circuit 434 and the port 1 shift signal terminal CKR1 of the 3-port VRAM 310 and DA conversion. The digital RGB signal LSMEM is used as a read clock signal and a D / A converter 410 conversion clock signal.

  FIG. 6 is an explanatory diagram showing the function of the set value of each circuit in the superimpose control circuit 420. As shown in FIG. 6, the ratio of the frequency fHBDCK of the horizontal reference read dot clock signal HBDCK and the frequency fHDDA of the horizontal read dot clock signal HRDCK (fHBDCK / fHDDA) is the video read from the VRAM 310 (FIG. 6A). Is equal to the horizontal magnification KH of the video (FIG. 6B) displayed on the color CRT 701. Therefore, by adjusting the frequency fHDDA of the horizontal read dot clock signal HDDA, the image displayed on the color CRT 701 can be enlarged or reduced in the horizontal direction. In other words, the image can be scaled in the horizontal direction by adjusting the frequency division value N425 of the PLL circuit in the horizontal readout dot clock generator 425.

  The vertical readout line clock generator 430 is constituted by a PLL circuit that outputs a signal having a frequency N2 times the frequency of the vertical synchronization signal VSPC in synchronization with the vertical synchronization signal VSPC, and outputs a vertical readout line clock signal VRLCK. . The vertical read line clock signal VRLCK generated by the vertical read line clock generator 430 is supplied to a port 1 line increment terminal INC1 that advances a line address that is a vertical address of the 3-port VRAM 310 via an OR circuit 432. , The OR circuit 432, and the NOR circuit 433, are supplied to the port 1 output enable RE1 terminal (negative logic).

  As shown in FIG. 6, the ratio (fHSYNC / fVRLCK) of the frequency fHSYNC of the horizontal synchronizing signal HSPC and the frequency fVRLCK of the vertical readout line clock signal VRLCK is the same as that of the video read from the 3-port VRAM 310 (FIG. 6A). , Equal to the vertical magnification KV of the image (FIG. 6B) displayed on the color CRT 701. Therefore, by adjusting the frequency fVRLCK of the vertical readout line clock signal VRLCK, the video displayed on the color CRT 701 can be enlarged / reduced in the vertical direction. In other words, the video can be scaled in the vertical direction by adjusting the frequency division value N430 of the PLL circuit in the vertical readout line clock generator 430.

  The superimpose control circuit 420 obtains basic read timing from these horizontal reference read dot clock signal HBDCK, horizontal read dot clock signal HDDA, and vertical read line clock signal VRLCK.

  The vertical read offset counter 426 determines the start offset line position of the read line of the 3-port VRAM 310, and the horizontal reference read output from the horizontal reference read dot clock generator 421 after the count value is reset by the vertical synchronization signal VSPC. A vertical offset signal VROFT that advances the line address in the vertical direction of the 3-port VRAM 310 is sent to the OR circuit 432 in synchronization with the dot clock signal HBDCK.

  As shown in FIG. 6A, the set value N426 of the vertical read offset counter 426 indicates the start position in the vertical direction of the video portion read from the 3-port VRAM 310 (area surrounded by a broken line in the figure).

  The vertical blanking number counter 427 includes a counter (not shown) for deleting the vertical back porch area of the video signal LSPC. This counter counts the number of clocks of the horizontal synchronization signal HSPC, and outputs a vertical blanking end signal VBE to the vertical read start counter 428 when the vertical back porch region is passed.

  The vertical read start counter 428 receives the permission signal (vertical blanking end signal VBE) sent from the vertical blanking number counter 427, counts the number of clocks of the horizontal synchronization signal HSPC, and performs the vertical direction from the 3-port VRAM 310. Read start permission signal (vertical read start signal) VRS is output to vertical read number counter 429.

  As shown in FIG. 6C, the set value N428 of the vertical read start counter 428 defines the display start position in the vertical direction when the video read from the 3-port VRAM 310 is displayed on the screen of the color CRT 701. .

  The vertical readout number counter 429 receives the permission signal (control signal VRS) sent from the vertical readout start counter 428, counts the number of clocks of the horizontal synchronization signal HSPC, and indicates the readout period in the vertical direction from the 3-port VRAM 310. The signal, that is, the vertical read count signal VRT is output to the AND circuit 431.

  As shown in FIGS. 6B and 6C, the set value N429 of the vertical readout number counter 429 defines the number of lines in the vertical direction of the video displayed on the color CRT 701.

  The vertical read offset counter 426, the vertical blanking number counter 427, the vertical read start counter 428, the vertical read number counter 429, and the vertical read line clock generator 430 described above perform vertical read control on the 3-port VRAM 310. .

  Note that the horizontal reference readout dot clock signal HBDCK count N426 counted by the vertical readout offset counter 426, the horizontal synchronization signal HSPC count N427 counted by the vertical blanking count counter 427, and the horizontal synchronization counted by the vertical readout start counter 428 are counted. The number of clocks N428 of the signal HSPC, the number of clocks N429 of the horizontal synchronization signal HSPC counted by the vertical readout number counter 429, and the value of the N divider in the PLL circuit in the vertical readout line clock generator 430 are the CPU 620 in the personal computer. To set the required values.

  The horizontal read start counter 422 counts the number of clocks of the horizontal reference read dot clock signal HBDCK sent from the horizontal reference read dot clock generator 421, and reads the read start permission signal (horizontal read start signal HRSA) for the horizontal direction of the 3-port VRAM 310. ) To the horizontal 64 clock counter 423.

  As shown in FIG. 6C, the set value N422 of the horizontal readout start counter 422 defines the horizontal display start position when the video read from the 3-port VRAM 310 is displayed on the screen of the color CRT 701. .

  The horizontal 64 clock counter 423 receives the permission signal (horizontal read start signal HRSA) sent from the horizontal read start counter 422 and receives the number of clocks of the horizontal reference read dot clock signal HBDCK output from the horizontal reference read dot clock generator 421. Count. When the count value reaches 64 clocks, which is the characteristic at the time of reading from the 3-port VRAM 310, the horizontal reading reference signal HRSB is output to the horizontal reading dot clock generator 425, the horizontal reading number counter 424, and the AND circuit 431.

  The horizontal readout number counter 424 counts the number of clocks of the horizontal reference readout dot clock signal HBDCK sent from the horizontal reference readout dot clock generator 421 and reads out a permission signal (horizontal readout number signal HRT for the horizontal direction of the 3-port VRAM 310 in the horizontal direction. ) To the AND circuit 431.

  As shown in FIGS. 6B and 6C, the set value N424 of the horizontal readout number counter 424 defines the number of dots in the horizontal direction of the video displayed on the color CRT 701.

  Thus, horizontal readout control for the 3-port VRAM 310 is performed by the horizontal readout start counter 422, the horizontal 64 clock counter 423, and the horizontal readout number counter 424. Note that the set value of the frequency divider in the PLL circuit of the horizontal reference read dot clock generator 421, the set value of the frequency divider in the PLL circuit of the horizontal read dot clock generator 425, and the horizontal read start counter 422 count. The number of clocks N422 of the horizontal reference readout dot clock signal HBDCK and the number of clocks N424 of the reference dot clock signal HBDCK counted by the horizontal readout number counter 424 are respectively set to required values by the CPU 620 in the personal computer.

C. Contents of video processing in the first embodiment:
FIG. 7 is an explanatory diagram showing the processing contents of the first embodiment of the present invention, and FIG. 8 is a flowchart showing the processing procedure. 8 is performed by the CPU 620 executing an application program stored in the main memory 630.

  In the process of the first embodiment, as shown in FIG. 7A, nine different professional golfers' photographs are displayed as still images on the left half in one window of the color CRT 701. Then, the user selects one of the professional golfers using the mouse 644, and a moving image showing the golf swing of the professional golfer is displayed on the right half of the window.

In step S <b> 1 of FIG. 8, the CPU 620 or the video transfer controller 680 reads the video data of the still image from the CD-ROM device 682 that is an external storage medium and writes it in the still image area SIA in the second VRAM 310. The video data stored in the second VRAM 310 is read by the superimpose control circuit 420 and the video signal is supplied to the color CRT 701. Accordingly, the still image written in the first VRAM 310 in step S1 is displayed on the color CRT 701.

  In step S2, the user selects one of nine professional golfers displayed as a still image. In step S <b> 3, the moving image data indicating the swing of the selected golfer is read from the CD-ROM device 682 by the image transfer controller 680 and transferred to the moving image area MIA in the second VRAM 310. Then, as shown in FIG. 7B, the golfer's swing moving image is written into the moving image area MIA in the second VRAM 310.

  As shown in FIG. 7C, the window memory area 632 of the main memory 630 superimposes the characters “Golf Classroom” and “A Professional Form” displayed in the window and the video in the second VRAM 310. Color key data KY indicating the area to be imposed is written. The video data in the window memory area 632 is transferred to the first VRAM 670 by the CPU 620. When a plurality of windows are opened on the screen, a plurality of window memory areas are secured in the main memory 630. Then, the video data in each window memory area is transferred to the first VRAM 670 by the CPU 620. The video data stored in the first VRAM 670 is read as a video signal LSPC by the video controller 660 and supplied to the video processing circuit 800. Accordingly, the video signal LSPC including the color key data KY is supplied to the video processing circuit 800.

  The signal level of the video signal LSPC corresponding to the color key data KY is higher than the reference voltage Vr shown in FIG. As a result, in the area where the color key data KY is set (superimpose area), the comparison signal COMP compared from the voltage comparison circuit 540 becomes L level, and the video signal LSDA read from the second VRAM 310 is video. It is selected by the switch 510 and supplied to the color CRT 701. On the other hand, in the area where the color key data KY is not set, the video signal LSPC read from the first VRAM 670 by the video controller 660 is selected and displayed on the color CRT 701. In summary, the video read from the second VRAM 310 is displayed in the superimpose area where the color key data KY is set, and is read from the first VRAM 670 in the area where the color key data KY is not set. Displayed video is displayed.

  FIG. 9 is an explanatory diagram showing the position and size of an image in the first embodiment. FIG. 9A shows moving image sizes SX [dots] and SY [lines]. FIG. 9B shows a still image area SIA and a moving image area MIA in the second VRAM 310. The size of the area including the still image area SIA and the moving image area MIA is SXL [pixel] and SLY [line]. FIG. 9C shows a color key data area (superimpose area) in the window memory area 632. If the start address (offset address) of the window memory area 632 is (X0, Y0) and the start address (upper left point address) of the color key data area of the still image is (SX0, SY0), the difference address (SX0− X0, SY0-Y0) is (DH, DY). FIG. 9D shows a screen display in the color CRT 701. The size of the moving image area MIA in the window W is MH [pixel] and MV [line], and the size of the area including the still image area SIA and the moving image area MIA is MHL [pixel] and MVL [line].

The horizontal display magnification KH and the vertical display magnification KV of the moving image of FIG. 9D based on the moving image of FIG. 9A are given by the following equations.
KH = MH / SX (1a)
KV = MV / SY (1b)

The address (SX0, SY0) of the display start position in the window W is given by the following equation.
SX0 = X0 + DH (2a)
SY0 = Y0 + DV (2b)

Display sizes MHL and MVL of an area including a still image area SIA and a moving image area MIA on the screen of the color CRT 701 are given by the following equations.
MHL = SXL × KH (3a)
MVL = SYL × KV (3b)

As described in FIG. 6, the horizontal display magnification KH of the video can be adjusted by adjusting the frequency division value N425 of the PLL circuit in the horizontal readout dot clock generator 425 (FIG. 3). The vertical magnification KV of the video can be adjusted by adjusting the value of the frequency division value N430 of the PLL circuit in the vertical readout line clock generator 430. Specifically, these frequency division values N425 and N430 are given by the following equations.
N425 = NH0 / KH (4a)
N430 = NV0 / KV (4b)
Here, NH0 is a frequency division value when the horizontal display magnification KH is 1, and NV0 is a frequency division value when the vertical display magnification KV is 1.

  As described above, in this embodiment, the still image and the moving image in the window W can be simultaneously scaled at the same magnification by adjusting the frequency division values N425 and N430 of the PLL circuit. The horizontal display magnification KH and the vertical display magnification KV can be set to different values.

  When the display magnifications KH and KV are changed, the CPU 620 scales the color key data area in the window memory area 632 according to the display magnifications KH and KV. Since the amount of data in the window memory area 632 is considerably smaller than the amount of data in the VRAM, the CPU 620 can scale the color key data area at high speed.

D. Contents of video processing in the second embodiment:
FIG. 10 is an explanatory diagram showing the processing contents of the second embodiment of the present invention, and FIG. 11 is a flowchart showing the processing procedure. 11 is also performed by the CPU 620 executing the application program stored in the main memory 630.

  In the second embodiment, a videophone system between computer systems connected to a network is realized. The computer system shown in FIG. 1 can be used.

  In step S <b> 11 of FIG. 11, the CPU 620 reads a still image for selecting a communication partner from the hard disk device 654 and writes it in the still image area in the second VRAM 310. As a result, as shown in FIG. 10A, nine still images for selecting the other party are arranged and displayed on the left half of the window.

  In step S12 of FIG. 11, the user's own video is displayed in the video area on the right half of the window. In the second embodiment, a video camera (not shown) for displaying the user's own video is connected to the video input terminal 103 (FIG. 2).

  When the user selects one other party from the still image in step S13, CPU 620 calls the selected party through the network interface 656 in step S14. When the connection with the other party is completed (step S15), as shown in FIG. 10B, the video of the other party transmitted from the other party's computer system is displayed in the still image area in the window ( Step S16). Note that the video of the other party is supplied to the CPU 620 via the network interface 656 and transferred to the still image area in the second VRAM 310 by the CPU 620. Since the image of the other party is intermittently supplied via the network interface 656, it is displayed on the color CRT 701 as a semi-continuous still image (semi-moving image). The user's own video is also intermittently transferred to the other party's computer system via the network interface 656.

  Thus, during a call (step S17), a semi-continuous still image of the other party is displayed in the still image area in the window, and the user's own moving image is also displayed in the moving image area. When the call ends, the line is disconnected in step S18 (step S18), and the state returns to the state of FIG.

  As described above, in the second embodiment, a videophone using a computer system can be easily realized. At this time, not only the semi-continuous still image of the calling party but also the moving image of the user can be displayed simultaneously in the window. Similarly to the first embodiment, as shown in FIG. 9, it is possible to simultaneously scale a still image and a moving image in the window at the same magnification.

  The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

(1) In the above embodiment, the video signal LSMEM read from the second VRAM 310 is converted into the video signal LSPC read from the first VRAM 670 according to the color key data KY stored in the first VRAM 670. I was trying to synthesize. However, the video signal LSPC read from the second VRAM 310 can be supplied to the color CRT 701 without being combined with other video signals. In this case, the first VRAM 670 can be omitted. In addition, the VRAM 310 has a memory space corresponding to the display area in the color CRT 701 on a one-to-one basis, and the VRAM is used as a frame memory.

1 is a block diagram showing a configuration of a computer system as an embodiment of the present invention. 2 is a block diagram showing an internal configuration of a video processing circuit 800. FIG. The detailed block circuit diagram of the superimpose control circuit 420 and its peripheral circuit. 4 is an explanatory diagram showing an input / output circuit of a horizontal synchronization signal HSPC and a vertical synchronization signal VSPC in a superimpose control circuit 420. FIG. 4 is a block diagram showing a configuration of a PLL circuit 63. FIG. FIG. 3 is an explanatory diagram showing functions of set values of respective circuits in a superimpose control circuit 420. Explanatory drawing which shows the processing content in 1st Example of this invention. The flowchart which shows the process sequence in 1st Example of this invention. Explanatory drawing which shows the position and size of the image | video in 1st Example. Explanatory drawing which shows the processing content in 2nd Example. The flowchart which shows the process sequence in 2nd Example of this invention. Explanatory drawing which shows the state in which the still image and the moving image were simultaneously displayed in one window of a display device.

Explanation of symbols

61, 62 ... buffer 62, 61 ... buffer 63 ... PLL circuit 71 ... phase comparator 72 ... low pass filter 73 ... voltage controlled oscillator (VCO)
74 ... N frequency divider 101 ... Audio input terminal 102 ... Audio output terminal 103 ... Video input terminal 110 ... Audio signal selection circuit 120 ... Volume control circuit 130 ... Video signal selection circuit 140 ... Video signal decoder 210 ... AD converter 220 ... Digitize control circuit 310 ... Video RAM (first video memory)
320 ... Video data selection circuit 330 ... Video memory control signal selection circuit 340 ... Write control circuit 350 ... Read control circuit 360 ... FIFO memory 370 ... FIFO read control circuit 410 ... DA converter 420 ... Superimpose control circuit 421 ... Horizontal Reference readout dot clock generator 422 ... Horizontal readout start counter 424 ... Horizontal readout count counter 425 ... Horizontal readout dot clock generator 426 ... Vertical readout offset counter 427 ... Vertical blanking count counter 428 ... Vertical readout start counter 429 ... Vertical readout count Counter 430 ... Vertical readout line clock generator 431 ... AND circuit 432 ... OR circuit 433 ... NOR circuit 434 ... Tristate circuit 435 ... Tristate circuit 451 ... AND circuits 490, 491 ... Synchronization signal terminal 506 Chrominance signal input terminal 507, 508 ... synchronous terminal 510 ... Video Switch 540 ... voltage comparator circuit 610 ... Bus 620 ... CPU (processor)
630 ... Main memory 632 ... Window memory area 640 ... Peripheral controller 642 ... Keyboard 644 ... Mouse 650 ... Composite I / O port 652 ... Floppy disk device 654 ... Hard disk device 656 ... Network interface 660 ... Video controller 670 ... Video RAM (first) 1 video memory)
680 ... Video transfer controller 682 ... CD-ROM device 701 ... Color CRT
710 ... TV tuner 711 ... TV antenna 800 ... Video processing circuit (video processing unit)

Claims (1)

A method of displaying video on a display device,
(A) preparing in advance a plurality of still images and a moving image corresponding to each still image;
(B) displaying the plurality of still images on the display device;
(C) receiving a selection of one still image from the plurality of still images by a user;
(D) displaying a moving image corresponding to the selected still image on the display device simultaneously with the plurality of still images;
With
The step (a)
A step of writing key data indicating a superimpose area in a first video memory having a memory space corresponding to a display screen of the display device;
The step (b)
Writing still image video signals of the plurality of still images in a still image area in a second video memory;
The step (d)
(D1) The video image signal is continuously written in the moving image area in the second video memory, and is written in the area including the still image area and the moving image area in the second video memory. Reading out the video signal of 1;
(D2) obtaining a second video signal by scaling the video represented by the first video signal;
(D3) A fourth video signal is obtained by synthesizing the second video signal in the superimpose area of the video represented by the third video signal read from the first video memory. Process,
(D4) displaying the scaled moving image and still image on the display device by supplying the fourth video signal to the display device;
(D5) changing the key data stored in the first video memory so as to scale the superimpose area with the changed magnification when the scaling magnification is changed;
A video display method comprising:

Images