JPH02210989A - Television receiver - Google Patents

Abstract

PURPOSE:To reduce flicker on the screen when a reproduced signal from a VTR is watched by shifting a vertical synchronizing pulse in the time base direction so as to appear earlier than a vertical synchronizing signal by a prescribed horizontal period. CONSTITUTION:The television receiver consists of a counter 19, latch circuits 21, 23, comparators 24, 27, a sub counter 26, an AND circuit 25 as a vertical synchronizing pulse forming means and of a sub counter 20 as a control means. A vertical synchronizing pulse forming means uses a vertical synchronizing signal VS of the standard TV signal from a terminal 18 and a clock signal from a terminal 22 to form a vertical synchronizing pulse 28a having frequency twice the frequency of the signal VS whose field frequency is doubled. In this case, the control means shifts the pulse 28a in the time base direction so that the pulse appears earlier than the signal VS by a prescribed horizontal period. Since distortion due to a skew signal is included in an over scan region and does not appears on the effective picture screen, the video signal due to the skew signal is not distorted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a television receiver suitable for use as a monitor of a video tape recorder that reproduces PAL or SBCAM color video signals.

[Summary of the invention]

The present invention relates to a television receiver suitable for use as a monitor for a video tape recorder that reproduces PAL or SECAM color video signals, in which manually inputted video signals are written in a memory and read out from the memory at double speed. In a television receiver configured to display a video signal, a vertical synchronizing pulse forming means for creating a vertical synchronizing pulse having twice the frequency from a vertical synchronizing signal of the input video signal, and By providing a control means for shifting the vertical synchronizing pulse in the time axis direction so that it appears a predetermined horizontal period earlier than the vertical synchronizing signal, it is possible to improve surface flicker even when the reproduced video signal of a video tape recorder is monitored. This prevents skinny from appearing on the screen when switching heads.

[Conventional technology]

Generally, the PAL or SBCAM color video signal is a 50-field format with a vertical frequency of 5 () Hz, and when this PAL or SEC'A M color video signal is played back on a large screen, This has the disadvantage of causing flicker and making it relatively difficult to see. Therefore, a method has been proposed in which the field frequency of this color video signal is doubled to reduce flicker. Figure 3 shows a television receiver that reduces flicker as previously proposed by the present applicant. In Figure 3, (1) is P
Vertical frequency is 50 like AL method or SBCAM method)
This video signal input terminal (1
) is supplied to an analog Y/C separation circuit (2) that separates the color video signal into a luminance signal and a chromaticity signal, and a synchronization separation circuit (3) that separates a synchronization signal. This analog Y/C separation circuit (in which luminance signal Y and color difference signal R
-Y, B-Y (here, R is a red signal and B is a blue signal), and the luminance signal Y is converted into a digital signal by an analog-to-digital conversion circuit (4), and then sent to a noise reduction circuit. (5 Y and field memo U (6 Y
) (6Y') and is supplied to the digital-to-analog conversion circuit (7). In this case, field notes! J
(6Y) (6Y read control signals Ml with twice the frequency of the write control signal My,
The luminance signal output to this digital-to-analog conversion circuit (7) is converted into a luminance signal with twice the field frequency and converted to RGB.
An analog luminance signal 2Y with twice the field frequency is supplied to the conversion circuit (8). Also, analog Y/C separation circuit (
The color difference signals R-Y and B-Y separated in step 2) are sent to R-Y, B-Y, R-Y, B-Y via the analog switch (9).
. . . Serial color difference data is generated, digitized by an analog-to-digital conversion circuit (10), and sent to a memo IJ via a color difference noise reduction circuit (11).
(6C) Supply to (6C'). This memory (6
C') (6C is a 4-bit IT that stores 8-bit serial data in parallel in 4-bit units.The output signal of this memo 'J (6C) (6C') is sent to the flicker reduction circuit (12) in 8 bits. color difference signals 2 (R-Y), 2 (B
-Y), this flicker reduction circuit (1
2) is output to the digital-to-analog conversion circuit (7). Therefore, the read control signal M of memory (6C) (6C') is 2 of the write control signal Mw.
Double the frequency. This digital-to-analog conversion circuit (
The analog field frequency obtained on the output side of 7) is supplied to the RGB conversion circuit (8). Red signal 2R, green signal 2G with twice the field frequency
and a green signal 2B is output. A red signal 2R, a green signal 2G, and a blue signal 2B with twice the field frequency obtained on the output side of this RGB conversion circuit (8) are supplied to the color cathode ray tube to obtain an image with reduced surface flicker. . In addition, in the synchronization separation circuit (3), the vertical synchronization signal V,
and the horizontal synchronizing signal Hs, and this horizontal synchronizing signal H
3 is an AFC that generates a 28MHz clock signal, for example.
Supplied as a reference signal to the circuit (Engine 3). The clock signal from this AFC circuit (13) is supplied to the flicker reduction circuit (12), and this clock signal is sent to the memory (6Y) (6Y (6C) (6C, digital).
They are respectively supplied to the analog conversion circuit (7).

The vertical synchronization signal V from the synchronization separation circuit (3) is also supplied to the flicker reduction circuit (12). Analog-digital conversion circuit (4) (10), noise reduction circuit (
5) (11) It is designed to control a deflection circuit (14) that controls the horizontal and vertical deflection of the color cathode ray tube.

This flicker reduction operation is shown in Figure 4A.

B1 To explain using the three-dimensional model of the image and scanning line in Figure 5 A and B, in the PAL or SBCAM system, the vertical frequency is i field (15) and i+l as shown in Figure 4 A and B.
Fields (16) are interlaced scanned, and the interval between i field (15), i+1 field (16), j+2 field (17), etc. is 20 μs at 50 Hz, but in this 50 field system. However, when a large screen is used, there is a problem of noticeable flickering, so the field frequency is doubled to 100 Hz, as shown in Figure 5 A and B.
The screen flicker is reduced when the screen is set to 10 μs on a large screen.

[Problem to be solved by the invention]

By the way, the playback signal from the video tape recorder is
As shown in Figure A, a skinny signal S exists when switching heads of a video tape recorder, and this skinny signal S is several horizontal periods, for example, 6 horizontal periods (6xH) before the vertical synchronizing signal, and is reproduced by a standard television receiver. When an image is obtained, this skinny signal S exists in the overscan area and does not affect the effective video screen in any way, but the video signal of a television receiver with twice the field frequency as shown in Figure 3 When a playback signal as shown in FIG. 6A from a video tape recorder is supplied to the input terminal (1), the skew signal S of the video signal supplied to the color cathode ray tube is as shown in FIG. 6A as shown in FIG. If the field frequency is doubled, 12H' of the 12 vertical synchronization signals in the horizontal period of twice the field frequency is at the same position in time as the reproduced signal, that is, for example, 6H before the vertical synchronization signal, and the field frequency is doubled. In the John receiver, this is outside the overscan area, and this skinny signal S is displayed on the effective video screen.
This causes distortion and makes the reproduced image difficult to view.

In view of this, it is an object of the present invention to provide a device that can effectively reduce screen flicker even when viewing a reproduced signal from a video tape recorder.

[Means to solve the problem]

The television receiver of the present invention stores manually input video signals in a memory (6Y) as shown in FIGS. 1 and 3, for example.
') (6C) (Write to 6C, this memory (6C)
Y) (6Y') (6C) (6C) In a television receiver configured to read and display data at twice the speed, a vertical synchronization pulse having a frequency twice that of the vertical synchronization signal Vs of this input video signal is generated. The vertical synchronizing pulses from the vertical synchronizing pulse forming means (18) to (28) are applied to the vertical synchronizing signal V for a predetermined horizontal period (for example, 5H).
) control means (20) (20a) for shifting in the direction of the time axis so as to appear earlier.

[Effect]

According to the present invention, when forming a vertical synchronizing pulse having a frequency twice that of the vertical synchronizing signal V, which doubles the field frequency, this vertical synchronizing pulse is the vertical synchronizing signal V, which doubles the field frequency.
s is shifted in the time axis direction so that it appears earlier by a predetermined horizontal period (for example, 5H, 5H is equivalent to 10 horizontal scanning lines when the field frequency is doubled), so the distortion caused by the skew signal S 1-) is included in the overscan area and does not appear on the effective screen, so the video screen is not distorted by this signal S.

〔Example〕

An embodiment of the television receiver of the present invention will be described below with reference to FIGS. 1 and 2.

In this example, the free gamma reduction circuit (12
) vertical sync pulse 2 with twice the field frequency
The V is formed as shown in FIG. That is, in FIG. 1, (18) indicates a vertical synchronizing signal input terminal to which the vertical synchronizing signal V as shown in FIG. 2A from the synchronizing signal separation circuit (3) is supplied. The vertical synchronizing signal V supplied to the terminal (18) is supplied to the clear terminal of the 11-bit counter (19) and also to the clear terminal of the sub-counter (20), and this vertical synchronizing signal Vs is supplied to the latch circuit ( 21
) to the load terminal. Further, (22) indicates a clock signal input terminal to which a clock signal of 4fH, which is four times the horizontal frequency, is supplied. The clock signal is supplied to each trigger terminal of the latch circuits (21) and (23).

The counter (19) is configured to count the 4fa clock signal between the vertical synchronization signals Vs and to supply 10 bits excluding the minimum bit to the latch circuit (21) in order to output the number of counts. . Therefore, the latch circuit (21) receives the vertical synchronization signal V.

Count number (7) of counter (19) every time is supplied
-Latch the number. The sub-counter (20) also counts the 4fi clock signal between the vertical synchronization signals Vs.
This count signal A is supplied to one input terminal of a comparison circuit (24).

In this example, 2Of, (20f M
supplies 5H, equivalent to 10H'. Therefore, this sub-counter (20) is initialized to 20fn and counts every time the vertical synchronizing signal V is supplied.

Also, since the vertical synchronizing signal V is supplied to the load terminal of the latch circuit (23), the vertical synchronizing signal V
, latches the latched number of the latch circuit (21) every time the latch circuit (21) is supplied. In other words, this latch circuit (23) uses a counter (19) that is one field behind the latch circuit (23).
) to latch the number of counting companies.

The output signal B of this latch circuit (23) is transferred to the comparison circuit (24).
) to the other input terminal. This comparison circuit (24)
is designed to output an output signal when the count signal A of the sub-counter (20) matches the output signal of this latch circuit (23), and the output signal of this comparison circuit (24) is passed through an AND circuit ( 25).

In this case, the vertical synchronizing signal V of the standard television signal at constant intervals of 312.5 H as shown in FIG. 2A is supplied to the vertical synchronizing signal input terminal (18), and the latch circuit (21
) is the vertical synchronizing signal V as shown in FIG. 2 B4.

The count number of the counter (19) between the vertical synchronization signals of the previous field when is input 1250 f II
The number 625fH of 0- is latched, and the number 625fi of latches in the previous field of this latch circuit (21) is
The latch circuit (23) latches as shown in FIG.

In this case, when the latch circuit (23) latches, for example, 625fH, the sub-counter (20) is supplied with this vertical synchronizing signal VS to the load terminal, and at this time, the sub-counter (20) is initially set to 20fM, and from this point on, the sub-counter (20) is initially set to 20fM. be done. After that, a clock signal of 605fH is supplied, and the count number of this sub-counter (20) increases to 625.
When f++ is reached, an output signal is obtained from the comparator circuit (24), and this is sequentially repeated to obtain an intermediate vertical synchronization pulse VM at a count position of 605f, l from the vertical synchronization signal Vs as shown in the second diagram.

In this case, the number of latches latched in the latch circuit (23) is determined by the counter (
19), and this intermediate vertical synchronization pulse V
is the number of horizontal periods between vertical synchronization signals two fields ago.
12.5H.

In addition, in this example, the intermediate vertical synchronizing pulses V and I as shown in the second diagram are supplied to the clear terminal of the sub-counter (26), and the clock signal input terminal of the sub-counter (26) is supplied to the clock signal input terminal of the sub-counter (26). 4f from (22)
i's clock signal. Therefore, this sub-counter (26) has an intermediate vertical synchronizing pulse Vt as shown in the second figure.
+ is supplied to the clear terminal, 4f clock signals are counted, and this count signal C is sent to the comparison circuit (2
7). In addition, the latch circuit (2
3) is supplied to the other input terminal of this comparison circuit (27). This comparison circuit (27) is designed to output an output signal when the count signal C of the sub-counter (26) matches the output signal B of this latch circuit (23). The output signal of is supplied to the other input terminal of the AND circuit (25).

In this case, as shown in FIG. 2E, the comparator circuit (24) sends the intermediate vertical synchronizing pulse V
A vertical synchronizing pulse Vs' is obtained when this sub-counter (26) counts the number of latches in the latch circuit (23), for example, 625 fi, from when m is supplied. This vertical synchronizing pulse V, is 2Of□ (5H or IOH') minutes 1 in the time axis direction from the vertical synchronizing signal V as shown in
I'll show up soon.

Therefore, this intermediate vertical pulse V and the vertical synchronizing pulse Vs
' is in the negative direction in this example, so the vertical synchronizing pulse output terminal (28) on the output side of this AND circuit (25) has a vertical synchronizing signal V as shown in FIG. 2F.

A vertical synchronizing pulse (28a) is obtained which is twice as large as 20flI (5H, that is, IOH) and shifted in the time axis direction.

This vertical synchronizing pulse (28&) is supplied to the deflection circuit (14). The rest of the structure is the same as in FIG. 3.

Therefore, according to this example, when forming a vertical synchronizing pulse (28a) with a frequency twice that of the vertical synchronizing signal V of the original video signal, which doubles the field frequency, this vertical synchronizing pulse (28a) Vertical synchronization signal V.

Since it is shifted in the time axis direction so that it appears 5 horizontal periods earlier (5H is equivalent to 10 horizontal scanning lines when the field frequency is doubled), the distortion caused by the skinny signal (
Since the skew (skew) is included in the overscan area and does not appear on the effective video screen, according to this example, it is possible to obtain a good video screen with reduced flicker even when monitoring the playback video signal from a video tape recorder. There is profit.

In the above-mentioned embodiment, explanation was given for normal playback of the video tape recorder, but the operation is similar to that described above during special playback of the video tape recorder, and a good video image with reduced flicker can be obtained.

Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

〔Effect of the invention〕

According to the present invention, screen flicker can be reduced even when the reproduced video signal of a video tape recorder is monitored, and a good video screen can be obtained in which skinny when switching heads does not appear on the effective video screen. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of essential parts of a television receiver of the present invention, FIG. 2 is a line diagram for explaining FIG. 1, and FIG. 3 is a block diagram showing an example of a television receiver. FIG. 4, FIG. 5, and FIG. 6 are diagrams for explaining the present invention, respectively. (1) is a video signal input terminal, (3) is a synchronous separation circuit, (
6Y) (6Y') (6C) (6C is memory, (
12) is a flicker reduction circuit, (14) is a deflection circuit, (18) is a vertical synchronizing signal input terminal, (19) is a counter, (20) and (26) I and each sub-counter,
(21> and (23) are latch circuits, respectively, (24) and (27) are comparison circuits, and (25) is an AND circuit. Agents: Ito, Sadamatsu, Hidetoshi Kuma, Figure 6, ? Amended proceedings of the fIPn example on the Sugi side 1. Display of the case 1988 Patent H No. H265784 2 Name of the invention Case of a person who corrects a television receiver 3.7iR Relationship with Patent Applicant Address Tokyo Parts Co., Ltd. 2 Kitahina Co., Ltd. 6-7-35 Name (2
18) Norio Ohga, Representative Director of Sony Corporation (1) In the specification, page 6, line 13, "20 us"
Correct to 20*s J. (2) Same, page 6, line 17, “10 μs” r 10
m5”. (3) Same, page 11, line 7 '20f, J (2 places) correct the text to "20". (4) Same, page 11, line 10, page 12, line 11, line 812,
13 lines. Delete "r, IJ" in lines 15 and 18, lines 1, 2 and 4 on page 13, lines 12 and 15 on page 14, and line 1 on page 15. (5) In the drawings , Figure 2 is amended as per the attached sheet. 4. Agent 5. Date of amendment order: June 1939. Number of inventions increased by amendment.

Claims (1)

[Claims] In a television receiver in which an input video signal is written into a memory, read out from the memory at double speed, and displayed, a vertical synchronization pulse having twice the frequency is generated from a vertical synchronization signal of the input video signal. The present invention is characterized in that it is provided with a vertical synchronizing pulse forming means for creating a vertical synchronizing pulse, and a control means for shifting the vertical synchronizing pulse from the vertical synchronizing pulse forming means in the time axis direction so that it appears a predetermined horizontal period earlier than the vertical synchronizing signal. television receiver.