JPH02204861A - Vector data processor - Google Patents

Abstract

PURPOSE:To process a vector operation containing a vector mask in a simple constitution and at a high speed by performing the writing/reading operations of vector data to the lowest or highest rank address of a vector register based on the value of the corresponding vector mask. CONSTITUTION:When the vector data is written, the vector data on a memory is given to a vector register 1 via an input crossbar. Then the vector elements having the value of the corresponding vector mask equal to '1' are written ascendingly via the lowest rank address of the register 1. At the same time, the vector elements having the value of the corresponding vector mask equal to '0' are written descendingly via the highest rank address of the register 1. Then the vector data is read out with a reading vector mask signal set at '1'. Thus the vector data can be read out in their original arrangement. On the contrary, only the vector data having its vector mask equal to '1' can be read out when the reading vector mask signal is set at '0'. As a result, the vector data can be calculated in a simple constitution and at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) The present invention relates to a vector data processing device, and particularly relates to control of writing and reading of masked vector data to and from a vector register.

In conventional vector data processing devices, when performing vector operations on masked vector data with the mask enabled, all vector data must be operated on to determine whether the mask of each vector element is valid or invalid. There is a method of reading and performing vector operations regardless of the operation result, and then writing only the vector elements for which the mask is valid for operation among the vector data of the operation result, and for the number of elements between vector elements for which the mask of the vector mask register is valid for operation. A method is used in which each calculation is performed and the number of elements is sequentially added when reading and writing vector data, and vector elements that are valid for calculation of vector data are read and written.

Such conventional methods have the following drawbacks. First, in the first method described above, the control configuration is simple, but
This method has the disadvantage that calculation time is required because calculations are performed even on vector elements that do not actually require calculations. Also, the second
This method does not take as much calculation time as the first method, but it requires a large amount of hardware to calculate the number of elements between vector elements for which the mask is valid for calculation, read it, and add it to the write address. This has the disadvantage that both the control structure and the control structure are complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a vector processing device that has a simple configuration and can perform operations on vector data at high speed.

1m North A vector data processing device according to the present invention includes a vector register that stores a plurality of vector elements, a vector mask register that holds vector mask data corresponding to each of the vector elements, and a vector data processing device that stores vector data from the lowest address to the highest address. a first write address generating means for generating write addresses in ascending order; and a second write address generating means for generating write addresses in descending order from the highest address to the lowest address.
and the write address of the first and second write address generation means is selected according to the value of the vector mask data corresponding to the vector element to be written, and the write address is set as the write address of the vector register. a selection means, a first read address generating means for generating read addresses in ascending order from the lowest address to the highest address, and a second read address generating means for generating read addresses in descending order from the highest address to the lowest address. The method is characterized in that it includes a generating means and a selecting means for selecting read addresses of the first and second read address generating means according to the value of the vector mask data corresponding to the vector element to be read.

sad cliff week Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

1 is a vector register, 2 is a vector mask register,
Reference numeral 3 denotes mask selection means for extracting a vector mask from the vector mask register.

4 is a counter for the first write address generation means, and 5 is a counter for the second write address generation means. 6 is a selector for selecting a write address, 7
8 is a counter for the first read address generating means, 8 is a counter for the second read address generating means, and 9 is a selector for selecting a read address. 10 to 2
Up to 1 are AND gates, OR gates, or inverters for control.

FIG. 2 is a block diagram of a vector data processing device including one embodiment of the present invention shown in FIG. 1, and the vector register 1 in FIG. be done. Portions such as the counter, gate group, and selector in FIG. 1 are represented by address systems #4a, 4b, and 4c.

In addition, 6 is an input loss bar that selects the calculation result or vector data from the memory and inputs it alternatively to vector registers la, lb, and lc; 6 is a vector register la;
An output crossbar 7.8 inputs vector data output from lb and lc to a vector calculator 7.8.

3 and 4 are diagrams for explaining the operation of the embodiment of the present invention, and the operation of the present invention will be explained with reference to these drawings. First, if the vector mask is not valid, the write mask valid signal and read mask valid signal are “
0'', the write address count signal is applied only to the address counter 4 by the gates 10.12, and the read address count signal is applied only to the address counter 7 by the gates 14.16.

Further, the selector 6 selects only the output of the address counter 4 as a write address by the gate 20, and the gate 20
1, the selector 9 selects only the output of the address carantuff and uses it as the read address. Therefore, writing and reading of the vector register 1 is performed sequentially from the lowest address to the highest address. This is the same as the conventional normal vector register write and read operations.

Next, the operation when the vector mask, which is a feature of the present invention, is effective will be described. When the write mask valid signal becomes "1", the write address count signal is applied to the counter 4 by the gates 11 and 12, and the counter is activated only when the vector mask read from the vector mask register 2 by the mask selection means 3 is "1". Count up 4. Further, the write address count signal is also given to the counter 5 by the gate 13.18, and in this case, conversely, from the vector mask register 2 to the mask selection means 3
Counter 5 is counted down only when the vector mask read by is "0".

Further, the selector 6 is controlled by the gate 2o, and when the vector mask is 1ltH, selects the counter 4 and sets it to "0".
In this case, counter 5 is selected and given to vector register 1 as a write address.

The read operation is similar to the write operation, and when the read mask valid signal becomes "1", the read address count signal is applied to the counter 7 by the gates 15 and 16, and is read out from the vector mask register 2 by the mask selection means 3. The counter 7 is counted up only when the vector mask obtained is "1". Further, the read address signal is also given to the counter 8 by the gates 17 and 18, and in this case, conversely, the counter 8 is counted down only when the vector mask read by the mask selection means 3 from the vector mask register 2 is "0". . The selector 9 is controlled by the gate 21, and selects the counter 7 when the vector mask is "1", and selects the counter 8 when the vector mask is "0", and provides the selected signal to the vector register 1 as a read address.

Therefore, assuming that this vector register 1 is now 16 words, using the vector mask shown in FIG.
Considering the case of writing the vector data of a16, the vector data a1 to a16 in the memory are given from the memory to the vector register from the input crossbar, and the value of the corresponding vector mask is "IN" as shown in Figure 3. Certain vector elements a1, a3, a4, a5,
a8, -=-1- are written in ascending order by the lowest address of vector register 1.

Conversely, vector elements a2, a6, a7, alo, al whose corresponding vector mask value is "opa"
3° . . . are written in descending order according to the most significant address of vector register 1. At this time, the value of the vector mask read by the mask selection means 3 and the counter 4,
The value of the counter 5 and the value of the write address output from the selector 6 are as shown in FIG.

Here, when the vector data written in this vector register 1 and the read vector mask signal are read as "1", the same operation as in the case of writing is performed, and al,
a2, a3, a4, a5,...
The vector data can be read in the original vector data arrangement. Conversely, read vector mask signal “0”
When read as al , a3 , a4 , a5
, a8, . . . only vector data whose vector mask is 1'' can be read.

Therefore, by supplying the vector data read out in this manner to the vector computing unit through the output Klobus, it is possible to compute only the vector elements for which the vector mask is valid. At this time, it is obvious that the vector data of the operation result must be written with the write mask signal set to 0 for the vector register to which the operation is written. It is also clear that by reading out the vector register with the read vector mask signal set to "1", the vector data can be read out in the order of the original vector elements.

As described above, according to the vector data processing device of the present invention, vector data can be written and read from either the lowest address or the highest address of the vector register depending on the value of the corresponding vector mask. This has the effect that vector operations with vector masks can be processed at high speed with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an overall block diagram of a vector data processing device including the embodiment of FIG. 1, and FIGS. 3 and 4 illustrate the operation of the embodiment of the present invention. It is a figure for explaining. Explanation of symbols of main parts 1...Vector register 2...Vector mask register 4.5.7.8
...Counter 6.9 ...Selector

Claims (1)

[Claims] (1) A vector register that stores a plurality of vector elements, a vector mask register that holds vector mask data corresponding to each of the vector elements, and a first register that generates write addresses in ascending order from the lowest address to the highest address. a second write address generating means for generating write addresses in descending order from the highest address to the lowest address; selection means for selecting the write addresses of the first and second write address generation means to be the write addresses of the vector register; and a first read address for generating read addresses in ascending order from the lowest address to the highest address. generating means; second read address generating means for generating read addresses in descending order from the highest address to the lowest address; and selection means for selecting a read address of the second read address generation means.