JPH0213731U - - Google Patents
Info
- Publication number
- JPH0213731U JPH0213731U JP1988091565U JP9156588U JPH0213731U JP H0213731 U JPH0213731 U JP H0213731U JP 1988091565 U JP1988091565 U JP 1988091565U JP 9156588 U JP9156588 U JP 9156588U JP H0213731 U JPH0213731 U JP H0213731U
- Authority
- JP
- Japan
- Prior art keywords
- conductive pattern
- integrated circuit
- thin metal
- electronic components
- metal wires
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例の一部を模式的に示
す平面図、第２図は従来例の一部を模式的に示す
平面図である。
１…基板、２…導体パターン、３…搭載部品、
４…金属細線、５…切欠き（目安）。
FIG. 1 is a plan view schematically showing a part of an embodiment of the present invention, and FIG. 2 is a plan view schematically showing a part of a conventional example. 1... Board, 2... Conductor pattern, 3... Mounted components,
4...Thin metal wire, 5...Notch (approximate).
Claims (1)
子部品を搭載し、この電子部品と導体パターンと
を金属細線で電気接続するように構成した混成集
積回路用基板において、前記導体パターンの金属
細線のボンデイング位置に、導体パターンの一部
形状を変形させた目安を形成したことを特徴とす
る混成集積回路用基板。 In a hybrid integrated circuit board configured to have a conductive pattern formed on its surface, various electronic components mounted thereon, and electrically connected to the electronic components and the conductive pattern using thin metal wires, a bonding position of the thin metal wires of the conductive pattern is provided. A board for a hybrid integrated circuit, characterized in that a guideline is formed by partially deforming the shape of a conductor pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988091565U JPH0213731U (en) | 1988-07-11 | 1988-07-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988091565U JPH0213731U (en) | 1988-07-11 | 1988-07-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0213731U true JPH0213731U (en) | 1990-01-29 |
Family
ID=31316037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988091565U Pending JPH0213731U (en) | 1988-07-11 | 1988-07-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0213731U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013070260A (en) * | 2011-09-22 | 2013-04-18 | Nippon Dempa Kogyo Co Ltd | Elastic surface wave element and manufacturing method therefor |
-
1988
- 1988-07-11 JP JP1988091565U patent/JPH0213731U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013070260A (en) * | 2011-09-22 | 2013-04-18 | Nippon Dempa Kogyo Co Ltd | Elastic surface wave element and manufacturing method therefor |