JPH0138244B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field) The present invention implements a circuit using a digital circuit that sequentially calculates the average value of values over a certain period of time and detects whether the average value exceeds a preset value. It is for the purpose of

(Prior Art) FIG. 1 shows an example of a conventional delay detection circuit partially digitized. 1 is the input terminal, MSK
A digital phase modulated signal such as (Minimum Shift Keying) is added. A delay circuit 2 provides a delay corresponding to, for example, the time of one bit of the digital signal. 3 is an exclusive OR circuit, and 4 is a low-frequency amplifier, which is used to give the output of the exclusive OR circuit 3 an average value for approximately 1 bit of the digital signal, and its approximate value. The simplest example is shown in Figure 2. 5 is an analog comparator, which judges whether the output of the low frequency converter 4 exceeds, for example, 1/2 of the voltage of digital "1"; if it exceeds 1/2, the output is "1", for example is output, and if it does not exceed it, outputs "0". An example of the analog comparator 5 is an operational amplifier as shown in FIG.

FIG. 4 shows an example of the output waveform of each part in FIG. 1, and the horizontal axis is the time axis. EXOR in Figure 4
is the output of the exclusive OR circuit 3, and the width of "1" and "0" changes depending on the digital signal input from the input terminal 1. In the LPF shown in FIG. 4, the output of the low frequency filter 4 is time-averaged for approximately one bit of the digital signal. Dotted lines parallel to the horizontal axis indicate "1" and "0"
It shows 1/2 of the output, and after this level, the output of the analog comparator 5 changes as shown by COMP in FIG. 4.

By the way, the low frequency converter 4 and the analog comparator 5 in Fig. 1 are analog circuits, so they are LSI
The drawback was that it was extremely difficult to convert.

(Objective of the Invention) An object of the present invention is to provide a moving average value detection device suitable for LSI implementation.

(Configuration of the Invention) In the configuration of the present invention, data is written in synchronization with a sampling clock oscillator and the clock oscillator.
Equipped with a ^2N (N is a positive integer) stage shift register, an N-bit up-down counter, and a digital comparator, when the data in the first stage of the shift register and the ^2Nth stage where data is written last have the same value. does not count, and when the data in the first stage and the ^2Nth stage of the shift register are different, up-counting or down-counting in synchronization with the clock oscillator according to the different states;
In addition, when all the bits of the up-down counter are "1", no up-count is performed even if the up-counting conditions are met, and when all the bits of the up-down counter are "0", the up-count is down. This moving average value detection device is characterized in that it does not count down even if a counting condition is met. Examples will be described in detail below.

(Embodiment) FIG. 5 is a circuit for explaining the first embodiment of the present invention, in which 1, 2, 3 and 6 are the same as those in FIG. 1, and 7 is a 2 ^N stage circuit. Shift register (N
is a positive integer. ), 8 is a sampling clock oscillator, and 9 is a logic circuit, which inputs the first stage of the shift register 7 into which data is written first, and the second ^Nth stage into which data is written last.
10 is an N-bit up-down counter, and 11 is a digital comparator.

The output data of the exclusive OR circuit 3 is sampled according to the clock of the sampling clock oscillator 8, and read into the first stage A of the ^2N stage shift register 7. This read data is shifted to the right every time the clock of the sampling clock oscillator 8 advances one cycle, and the data is shifted to the right side.
The sampling data read in is shifted to the ^2N stage B of the ^2N stage shift register 7 by ^2N -1 sampling clocks.

The logic circuit 9 performs ^a logical operation as shown in ^FIG . Determine up count and down count.

The frequency c of the sampling oscillator 8 is a high frequency that samples the output from the exclusive OR circuit 3 as faithfully as possible, and is generally more than twice the highest frequency that needs to be reproduced according to Shannon's theorem. , there is one condition. Furthermore, a frequency determined by the following calculation formula is selected.

c=2 ^N -1/T where T is the time length over which the average value is to be obtained.

Next, the operation of the circuit configured as described above will be explained.

First, it is assumed that the contents of each stage of the shift register 7 and the contents of each bit of the up-down counter are all "0". When the sampling clock 8 advances by one cycle, the sampling data is first taken into the first stage A of the shift register 7. If this value is "1", the value of A is transferred to the second stage of the shift register 7 at the next sampling clock, and the up-down counter 10 counts up by 1 bit according to the logic operation shown in FIG. Thereafter, the sampling data is sequentially moved within the shift register 7 in accordance with the sampling clock, and the contents of the up-down counter 10 are increased by the number of "1"s in the sampling data. When the number of sampling clocks reaches ^2N , the first sampling data appears in the ^2Nth stage B of the shift register 7,
Rows 2 to 2 The numbers where the content of each row of ^{the Nth} row is "1" are:
It matches the contents of the up-down counter 10. Next, when the values in the 1st stage A and the ^2Nth stage B of the shift register 7 match, the number of "1"s in the 2nd to ^2Nth stages is
Even if the contents of the shift register are shifted one step at a time at the next sampling clock, they do not change. At this time,
The contents of the up-down counter 10 also remain unchanged.
Also, when the content of the 1st stage A of the shift register 7 is "1" and the content of the ^2Nth stage B is "0", the next sampling clock will change the "1" of the 2nd to ^2Nth stages. The number increases by one, and the contents of the up-down counter 10 also increases by one. Conversely, when the content of the 1st stage A of the shift register 7 is "0" and the content of the ^2Nth stage B is "1", the number of "1"s in the 2nd to ^2N stages of the shift register 7 is decreased by one, and the contents of the up-down counter 10 are also decreased by one.

As can be understood from the above explanation, the number of "1"s in the second to ^2N stages of the shift register 7 always matches the contents of the up-down counter 10. Therefore, by comparing the value with a preset value using the digital comparator 11, an output indicating whether or not the value has been exceeded can be obtained at the output terminal 6. Also, the number of "1"s in the contents of the 2nd to ^2Nth stages of the shift register 7 is determined at what rate from that time to the time T back.
If we compare this number with 2 ^N -1, we are finding the time average within the above time period. Since the contents of the shift register 7 change sequentially in accordance with the cycle of the sampling oscillator 8, a moving average value within time T is obtained.

Next, if the sampling data is "1" for all time T, then the shift register 7's 2
All the bits in the 2nd to ^2nd rows are "1", and similarly, all N bits of the up-down counter 10 are "1". In other words, the number of "1"s is 2 ^N -1.

Also, when the average value is 1/2, the number of "1" is between 2 ^N-1 + 1 and 2 ^N-1 -1, and "1"
When the number of up-down counters is 2 ^N-1 + 1, that is, only the MSB of up-down counter 10 is "1" and the remaining N
- When one bit is “0”, the average value is 1/2
bigger. Also, when the number of “1” is 2 ^N-1 −1, that is, the up-down counter 10
Only the MSB is “0” and the remaining N-1 bits are “1”
, the average value is less than 1/2. Therefore, in cases where it is only necessary to determine whether the average value is larger or smaller than 1/2 (this is the case in most cases)
The digital comparator 11 may be a simple one that detects whether the MSB of the up-down counter 10 is "1" or "0".

When detecting whether the average value exceeds an arbitrary value between 0 and 1, a number obtained by multiplying an arbitrary value between 0 and 1 by 2 ^N-1 may be set in the digital comparator 11.

By the way, in the first embodiment shown in FIG. 5, the number of "1"s in the 2nd to ^2N stages of the shift register 7 and the contents of the up-down counter 10 may be affected by some reason (such as noise, etc.). When they no longer match due to
This causes the inconvenience that the correct average value is no longer detected.

The second embodiment is improved to prevent this, and is shown in FIG. In FIG. 7, 12,
13 is a logic circuit, and other symbols are the same as in FIG. The logic circuit 12 closes the gate of the logic circuit 13 to which the output of the logic circuit 9 is input when the values of the N bits of the up-down counter 10 are all "1", and even if an up-count instruction is issued from the logic circuit 9, , does not count, and conversely, when the values of the N bits of the up-down counter 10 are all "0", the gate of the logic circuit 13 is closed to prevent counting even if a down-count instruction is issued from the logic circuit 9. .

Next, to explain the operation of FIG. 7, if for some reason the value of the up-down counter 10 becomes larger than the contents of the shift register 7, when the sampling data becomes a series of "1",
All N bits of the up-down counter 10 become "1" before the contents of the shift register 7 become "1". However, because the logic circuits 12 and 13 do not count up any more, if the number of "1"s starts to decrease after all the values in the shift register 7 become "1", the second stage of the shift register 7 The number of "1"s in the 2nd to 2nd ^Nth rows and the value of the up-down counter 10 come to match.

Similarly, when the value of the up-down counter 10 becomes smaller than the contents of the shift register 7, it is corrected when the values of the 2nd to ^2N stages of the shift register 7 all become "0". , hereafter, the contents of the shift register 7 and the up-down counter 10
The contents of will match.

There is an extremely high probability that the sampling data will be all "1" or all "0" for T time, so in rare cases the contents of the shift register 7 and the contents of the up-down counter 10 will not match. Even when the average value is correct, it is corrected immediately and the correct average value can always be detected.

Note that, as illustrated as the third embodiment in FIG.
By adding hysteresis characteristics to the detection operation of the digital comparator 11, the operation can be made more stable. That is, for example, when the output of the digital comparator 11 is "0", the detection point level when it becomes "1" next time is raised by a certain value (for example, raised by 2), and conversely, the output of the digital comparator 11 is "0". 0”, the next time it becomes 1, digital comparator 1
If the detection point level of 1 is lowered by a certain value (for example, lowered by 2), the output will not rise or fall in a short time due to small fluctuations in the input signal, so stable operation can be achieved. This can be applied to both the first embodiment shown in FIG. 5 and the second embodiment shown in FIG. This is effective when handling signals with a lot of noise.

As described above, in the first, second, and third embodiments, when the data in the first stage of the shift register 7 is "1" and the data in the ^2N stage is "0", up-counting is performed. It was hot. By connecting the inverter 15 after the comparator 11 as shown in Fig. 9, it is possible to easily down-count when the data in the first stage of the shift register 7 is "1" and the data in the ^2Nth stage is "0". However, when the data in the first stage of the shift register 7 is "0" and the data in the ^2Nth stage is "1", a moving average value detection device can be implemented by up-counting.

(Effect of the invention) As explained above, the moving average value can be detected by configuring a simple digital circuit.
Can be converted into LSI.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional configuration, Figure 2 is an example of a circuit diagram of a conventional low frequency converter, Figure 3 is an example of a circuit diagram of a conventional analog comparator, and Figure 4 is an example of the circuit diagram of a conventional analog comparator. Waveform diagrams of various parts, FIG. 5 is a circuit diagram showing one embodiment of the present invention, FIG. 6 is a diagram showing the operation of the logic circuit 9, FIG. 7 is a circuit diagram showing a second embodiment of the present invention, FIGS. 8 and 9 are circuit diagrams for explaining third and fourth embodiments of the present invention. 1... Input terminal, 2... Delay circuit, 3... Exclusive OR circuit, 6... Output terminal, 7... Shift register, 8... Sampling clock oscillator,
9...Logic circuit, 10...Up-down counter, 11...Comparator, 12, 13, 14...
...Logic circuit, 15...Inverter.

Claims (1)

[Claims] 1. A moving average value detection device that sequentially calculates the average value of values over a certain period of time and detects whether the average value exceeds a preset value, comprising: a sampling clock oscillator; When the shift register is written in synchronization with the oscillator, and the data in the first stage and the data in the last stage of the shift register have different values, an up-count signal or a down-count signal is output, and each data is a logic circuit that outputs neither signal when the values are the same; an up-down counter that performs a counting operation based on the up-count signal or the down-count signal; and a predetermined value that is counted in the counter. 1. A moving average value detection device comprising: a comparator for comparing the moving average value. 2 If the data in the first stage of the shift register is "1" and the data in the last stage is "0", it counts up or down, and when the data in the first stage of the shift register is "0", it counts up or down. 2. The moving average value detection device according to claim 1, wherein the moving average value detection device performs down-counting or up-counting in a different state where the data in the final stage is "1". 3. In a moving average value detection device that sequentially calculates the average value of values over a certain period of time and detects whether the average value exceeds a preset value, a sampling clock oscillator and a When the data in the first stage and the data in the last stage of the shift register have different values, an up-count signal or a down-count signal is output, and when the respective data have the same value, an up-count signal or a down-count signal is output. a first logic circuit that does not output any of the signals; an up-down counter that performs counting operations based on the up-count signal or the down-count signal; and when each bit of the up-down counter is all "1"; a second logic circuit that does not perform an up-count even if an up-counting condition is satisfied, and does not perform a down-counting even if a down-counting condition is satisfied when all bits of the up-down count become "0"; A moving average value detection device comprising a comparator that compares the value counted in the counter with a predetermined value.