JP2000077990A - Digital phase comparator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase comparator which consists of a full digital circuit of high performance at a low cost. SOLUTION: An exclusive OR is secured via an exclusive OR gate 22 and accordingly the phase difference value is detected for the signals which are latched by the D flip-flops 10 and 12. At the same time, an exclusive OR is secured for the preceding and next signals of the D flip-flops 16 and 18 to extract two waveform edges. These waveform edges are supplied to an RS flip-flop 26 for detection of a phase difference code (leading or lagging phase). The phase difference value and the phase difference code are supplied to a counter 30 where a phase difference is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase comparator suitable for comparing the phase difference between two logical value signals and outputting the result of the comparison as a digital signal.

[0002]

2. Description of the Related Art Various types of phase comparators for comparing the phase difference between two logic value signals are known. For example, a typical circuit is shown in FIG. In the figure, a comparison circuit 100 for comparing the phases of logical value signals A and B is composed of a large number of NAND gates and inverters as shown, and the phases of input signals A and B are digitally compared. . The comparison result is supplied to the charge pump circuit 102. This charge pump circuit 1
Numeral 02 is constituted by a plurality of MOS transistors, whereby a phase error signal as a comparison result is output in the form of an analog signal.

[0003]

However, in the prior art described above, the analog charge pump circuit 102 is used in the output stage of the digital comparison circuit 100. For this reason, it is difficult to integrate the whole into an LSI, and an A / D converter or the like is required to handle the output signal as a digital signal.
Also, dynamically changing the characteristics of the phase comparator is difficult because of the analog circuit. Further, in order to detect the phase difference between both the rising edge and the falling edge of the digital signal, two sets of circuits as shown in FIG. 4 are required, which complicates the circuit and increases the cost.

The present invention has been made in view of the above points, and has as its object to provide a low-cost, high-performance digital phase comparator.

[0005]

In order to achieve the above object, the present invention provides a digital phase comparator for detecting a phase difference between two logic value signals, wherein the phase difference between the two logic value signals is detected. Phase difference amount detection means (10, 12, 22, 2
8); phase difference code detecting means (16, 18, 20, 24, 26) for detecting the sign of the phase difference between the two logical value signals; Bit string conversion means (30) for converting into a digital signal using the code of the phase difference detected by the phase difference code detection means; a filter for performing a predetermined band filtering on the phase difference signal thus converted Means (38);

According to the main mode, the phase difference amount detecting means and the phase difference sign detecting means each include a plurality of latch means for sequentially latching the two logical value signals, respectively, and the logical value latched by these latch means. A plurality of operation means for performing an exclusive OR operation on the signal, wherein the bit string conversion means counts the phase difference signal in a counting direction determined based on the phase difference code. Constituted by means.

According to still another aspect, there is provided control means for changing a clock serving as a reference for the operation of the latch means, a latch clock of the filter means and the counter means, and characteristics of the filter means.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. FIG.
FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is a timing chart corresponding to FIG.

In FIG. 1, the Q output side (non-inverted output side) of the D flip-flop 10 is connected to the D flip-flop 1
6, exclusive OR gate 20 and exclusive OR gate 2
2 respectively. D flip-flop 16
Are connected to an exclusive OR gate 20. The output side of the exclusive OR gate 20 is connected to the S terminal of the RS flip-flop 26.

On the other hand, the Q output side of the D flip-flop 12 is connected to a D flip-flop 18, an exclusive OR gate 24.
And the exclusive OR gate 22. The Q output side of the D flip-flop 18 is connected to the exclusive OR gate 24. Exclusive OR gate 2
4 is connected to the R terminal of the RS flip-flop 26. The output of the exclusive OR gate 22 is D
It is connected to the D terminal of the flip-flop 28. The Q output side of the D flip-flop 28 is connected to the EN
Connected to ABLE terminal.

The Q output side of the RS flip-flop 26 is
It is connected to the UP / DOWN terminal of the counter 30.
The output side of the counter 30 is connected to a digital filter 38.

The output of the controller 36 is a clock 1
It is connected to a 4, 1 / N frequency divider 32 and a digital filter 38, respectively. The output side of the clock 14 is connected to the D flip-flops 10, 12, 16, 18, 28, the RS flip-flop 26, the respective CLK terminals of the counter 30,
/ N frequency divider 32 are connected to the respective IN terminals.
The output side of the 1 / N divider 32 is connected to the latch clock generator 3
4 is connected. The output side of the latch clock generator 34 is connected to the RESET terminal of the counter 30 and the digital filter 38.

Next, the operation of each unit described above will be described. The logical value signals A and B shown in FIG. 2 are input to the D flip-flops 10 and 12, respectively.
And 12 are latched at the rising timing of the clock signal CLOCK shown in FIG. The latched signal waveforms are shown in FIG. 2 as LACHA and LACHB.
The exclusive OR gate 22 performs a logical operation that becomes 1 when the corresponding bits of the two latched bit strings are different. Therefore, the exclusive OR gate 22 detects the amount of phase difference by taking the exclusive OR of the latched signals.

In the D flip-flop 16 and the exclusive OR gate 20, the edge of the signal waveform A is extracted by taking the exclusive OR of the latch signals before and after the D flip-flop 10 (FIG. 2). XOR1). The extracted edge signal is input to the S terminal of the RS flip-flop 26. In the D flip-flop 18 and the exclusive OR gate 24, the edges of the signal waveform B are extracted by taking the exclusive OR of the latch signals before and after the D flip-flop 12 (XOR2 in FIG. 2). The extracted edge signal is input to the R terminal of the RS flip-flop 26.

In the RS flip-flop 26, S and R
The sign of the phase difference, that is, whether it is a leading phase or a lagging phase, is detected based on the signal input to each terminal of FIG.
UP / DOWN). The sign signal of the detected phase difference is
The signal is input to the UP / DOWN terminal of the counter 30. To match the phase difference amount and the timing of the phase difference code signal,
The phase difference signal detected from the exclusive OR gate 22 is sent to the E flip-flop 28 of the counter 30 via the D flip-flop 28.
Input to the NABLE terminal.

In the counter 30, the detected phase difference amount signal is counted by an appropriate clock and output as a digital signal. That is, in the counter 30, one of the count up and the count down is determined based on the sign signal of the phase difference detected by the RS flip-flop 26. For example, the sign signal of the phase difference has a logical value of “1”.
In the state of the leading phase of the up counter, the logical value "0"
In the state of the lag phase, the state is a down counter. When the ENABLE terminal has a logical value of "1", that is, when the phase difference amount signal has a logical value of "1" indicating that there is a phase difference, the count operation is performed.
An output signal which is a count value of the counter 30 is sent to the digital filter 38 by the touch clock generated by the 1 / N divider 32,
Is reset. In the digital filter 38, appropriate band filtering is performed. by this,
A phase digital signal is obtained.

FIG. 3 shows an embodiment in which the digital phase comparator of the above embodiment is applied to the detection of a tracking error of an optical disk. In FIG. 3, each divided output of the four-divided photodetector 50 is a signal including a phase difference corresponding to a tracking error. These divided signals are supplied to delay circuits 60 to 66 for phase difference correction via IV amplifiers 52 to 58, respectively. Then, the signals of the photodetectors 50 located at diagonal positions are added. That is, the outputs of the delay circuits 60 and 64 are added by the adder 68, and the outputs of the delay circuits 62 and 66 are added by the adder 70. The addition signal is output from the comparator 7
The data is binarized (digitized) at 2 and 74, respectively. Then, the two digitized digital signals A and B are supplied to the digital phase comparator 80 described above. The digital phase comparator 80 compares the phases of the signals A and B as described above, and obtains a phase difference signal between them, that is, a digital tracking error signal.

Further, in the above operation, the controller 36 determines the frequency of the clock 14 (for example, 100 MHz).
z), the division number N of the 1 / N divider 32 (for example, N = 51)
2) and the band of the digital filter 38 is controlled. The clock 14 has the D flip-flops 10, 12, 16, 1
8, 28, RS flip-flop 26 and counter 30
(CLOCK in FIG. 2). 1 /
A reset signal is generated by the N frequency divider 32 and the latch clock generator 34 and provided to the counter 30 and the digital filter 38. The counter 30 is reset simultaneously with the latch based on the reset signal. Thus, the characteristics of the clock, digital conversion, and digital filtering are changed as needed.

[0019]

As described above, according to the present invention,
The following effects can be obtained. (1) All circuits of the phase comparator are composed of digital circuits synchronized with a clock, and the whole can be implemented as an LSI. (2) The phase difference between the rising edge and the falling edge of the logical value signal can be compared by one circuit, and the circuit can be simplified and the cost can be reduced. (3) Since all the circuits can be constituted by digital circuits, the characteristics of the phase comparator can be easily and appropriately changed. (4) By using an operation clock having a frequency sufficiently higher than that of the input signal, sufficient accuracy can be ensured. (5) The performance of the phase comparator can be set to an optimum state according to each characteristic, such as during normal tracking and during special processing such as search.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart corresponding to FIG.

FIG. 3 is a block diagram showing an embodiment in which the above embodiment is applied to tracking error detection of an optical disc.

FIG. 4 is a diagram showing a configuration of a conventional phase comparator.

[Explanation of symbols]

 10, 12, 16, 18, 28: D flip-flop 14: clock 20, 22, 24: exclusive OR gate 26: RS flip-flop 30: counter 32: 1 / N divider 34: latch clock generator 36 ... Controller 38 ... Digital filter 50 ... Photodetector 52-58 ... Amplifier 60-66 ... Delay circuit 68,70 ... Adder 72,74 ... Comparator 80 ... Digital phase comparator 100 ... Comparison circuit 102 ... Charge pump circuit

Claims (3)

[Claims] 1. A digital phase comparator for detecting a phase difference between two logical value signals, wherein: a phase difference amount detecting means for detecting a phase difference amount between the two logical value signals; a phase difference between the two logical value signals Phase difference code detecting means for detecting the sign of the phase difference signal; converting the phase difference signal detected by the phase difference amount detecting means into a digital signal using the sign of the phase difference detected by the phase difference code detecting means A digital phase comparator, comprising: bit string conversion means; and filter means for performing filtering of a predetermined band on the phase difference signal converted thereby. 2. A phase difference amount detecting means and a phase difference sign detecting means, wherein a plurality of latch means for sequentially latching the two logical value signals, respectively, are exclusive with respect to the logical value signals latched by the latch means. And a plurality of arithmetic means for performing a logical OR operation, and the bit string converting means is configured by a counter means for counting the phase difference signal in a counting direction determined based on the phase difference code. The digital phase comparator according to claim 1, wherein: 3. The digital device according to claim 2, further comprising a control unit for changing a clock serving as a reference of the operation of the latch unit, a latch clock of the filter unit and the counter unit, and a characteristic of the filter unit. Phase comparator.