JPH01112600A - Service life decision device for storage element - Google Patents

Abstract

PURPOSE:To prevent data from being written in a storage element in excess of a control value for each address by updating the number of times of writing of each address corresponding to every write of the data in the storage element and writing the result in the storage element together with the content. CONSTITUTION:A CPU 1 designates the address to a read/write controller 3 to send a readout request signal. Then the storage element 2 receives a request signal from the circuit 3 to give the stored data and the number of times of writing to the controller 3. The CPU 1 receives them and replaces the data with a content desired to be written newly to increment the count data of the number of writes. The CPU 1 constituting the new data and the content of the number of writes sends the write request signal to the controller 3 and the controller 3 writes the data formed newly in the address of the element 2 and the number of write. In this case, when the CPU 1 reads out the data and the number of times of writing read by the CPU 1 reaches a limit value, a fault is annunciated by the alarming device 5. Thus, the write in excess of the control value is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a device for determining the lifespan of a semiconductor non-volatile memory element such as an E2FROM so that it is not used more than a controlled number of times.

2. Description of the Related Art As a conventional device for determining the life span of a memory element, a configuration as shown in FIG. 5, for example, has been proposed in Japanese Patent Application Laid-Open No. 62-200800. 1 in Figure 5 is the central processing unit (
(hereinafter abbreviated as CPU).

Now, when it is necessary to write data to a storage element 2 such as an E 2 F ROM, the CPU 1 sends a write signal WR to the read/write control device 3, and at the same time refers to the random number generator 5 to detect events that occur with a certain probability. Only when this is encountered, the contents of one write count area in the memory element 2 are updated, and the memory element 2 is updated based on this updated value.
This is to determine whether the number of writes to has reached the limit value.

Further, when the number of writes reaches a limit value, if there is no unused data area in the memory element 2, the life of the memory element 2 is terminated and an alarm is issued from the alarm device 4 to the outside. Note that the memory element 2 is an E2PROM (7) or an EAROM-? It is a semiconductor nonvolatile memory such as NVRAM, and the limit value of the number of writes is, for example, up to 10,000 times per register (that is, for each address).

Problems to be Solved by the Invention However, in the above configuration, the count area for storing the contents updated when data is written is provided corresponding to each address, as shown in the memory map of FIG. Not there.

Therefore, it is recorded! Although it is possible to know the total number of write operations performed on element 2, it is not possible to identify the difference between addresses to which write operations occur from time to time and addresses that do not, and to count the number of write operations for each address. In other words, there was a problem in that the true limit value guaranteed by the memory element could not be grasped.

The present invention solves this conventional problem, and each time data is written to the memory element, the number of writes for each corresponding address is updated, and the contents are written together to the memory element. The purpose of this is to prevent data from exceeding a control value from being written into a storage element.

Means for Solving the Problems In order to solve the above-mentioned problems, the lifespan determination device for a memory element of the present invention provides a method for determining the lifespan of a memory element in which arbitrary data to be written/read is stored in a predetermined number of data areas of a memory element. By providing a data area and a write count area that corresponds one-to-one to the data area, the number of writes for each address can be ascertained.

Function: With the above-described configuration, the present invention is able to grasp not only the total number of writes to the memory element but also the number of writes independently for each address, making it possible to make the most of the lifespan specified for the memory element. Become. For example, if only the number of writes to a certain address exceeds the limit, only the corresponding data area and count area can be switched to an unused area in the storage element, or an alarm can be issued.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. , FIG. 1 is a block diagram showing an apparatus for determining the lifespan of a memory element, and FIG. 2 is a memory map diagram of the memory element. For example, assume that among n data areas, a part of each data area is allocated to a count area. That is, each address Ai (i21.n) stores data Di and the number of writes Ci in a combined configuration.

First, the CPU 1 stores the data D at the address At of the storage element 2.
The process in which it becomes necessary to write i' will be explained with reference to the flowchart of FIG.

The CPU 1 sends a read request signal DR to the read/write control device 3, specifying the address At. Next, the storage element 2 receives this request signal from the read/write control device 3 and passes the contents of the data input count Ci previously stored at the address At to the read/write control device 3. Therefore, the CPU 1 reads this data and replaces the data Di with the new content Di' to be written, and increments the count data of the number of writes Ci to become ci'(Ci' = Ci + 1). The CPU 1 sends the write request signal WR to the read/write control device 3 after configuring the data D to be written (and the contents of the number of writes Ci'). The newly configured content (Di'
and Ci'). By the way, if the number of writes Ci has reached the limit value at the time the CPU 1 reads out the data Dt and the contents of the number of writes Ci, then
The At data area is used for abnormal processing such as notification to the outside by the erasure alarm device 6. Here, the number of writes Ci is incremented not every write operation, but may be done, for example, once every 10 or 100 times.

Also, as shown in the memory map in Figure 2, one address At
Instead of dividing the structure in the data area into a data Di part and a write count Ci part', for example, as shown in the memory map of FIG.
．． It is also conceivable to make the data areas A21 (i=1 to n/2) correspond to the data Di portion and the write count Ci portion, respectively.

In the above configuration, the area for data arbitrarily written to each address and the area for counting the number of writes are 1:1.
Since it corresponds to the above, it is possible to determine the lifespan of each address in the memory element, thereby making it possible to make the most of the lifespan specified for the memory element.

Effects of the Invention As described above, according to the memory element life determination device of the present invention, by having a structure that automatically determines #4J that the number of writes has reached the memory element life for each address, Since a system can be constructed without worrying about the limit value of the number of times of writing to a memory element, there is an effect that the operational stability and reliability of the entire system using such a memory element can be improved.

[Brief explanation of the drawing]

FIG. 1 shows the life 'l of a memory element in one embodiment of the present invention.
! Figure 2 is a block diagram of the I-no-determination device, Figure 2 is a memory map diagram of the memory element of the same device, and Figure 3 is the same lifespan! l! To the flowchart of the IJ determination process 1. Figure 4 is a memory map diagram inside the memory element in the embodiment of the current cycle, Figure 5 is a block diagram of a conventional memory element life judgment device, and Figure 6 is a diagram showing the memory map inside the conventional memory element. FIG. 1...CPU, 2...Storage element, 3.
... Read/write control device, 4 ... Alarm device.

Claims (1)

[Claims] A memory element with a limited number of write operations, a read/write control device for writing data to the memory element and reading the written data, and a read/write control device for writing data to the memory element. A central controller that instructs the read/write control device to write in a data structure in which a number of writes is assigned to each stored address, and determines whether the number of writes for each data in the storage element has reached a limit value. A device for determining the lifespan of a memory element, comprising: an arithmetic processing unit; and an alarm device connected to the central processing unit to notify an external party when the number of writes reaches a limit value.