JPH01106580A - Decoding device - Google Patents

Abstract

PURPOSE:To efficiency cope with an error by recognizing the occurrence of the decoding error when picture data of one scanning line quantity are not decoded within a prescribed time. CONSTITUTION:A programmable timer device 29, in which the time required for producing pictures of one scanning line quantity in an ordinary modified- modified read(MMR) decoding process is set as a timer value, becomes time-out when the time elapses. Namely, when the decoding process of one scanning line quantity in an MMR decoding section 38 does not complete until the time up of the programmable timer device 29, time-out pulses are sent to an interrupt signal generator 30. Upon receiving the pulses, the generator 30 generates an interrupt signal I/R3 against a CPU32 and informs the CPU32 of the time-out. The CPU32 discriminates that an error occurs in the MMR decoding process being executed so far and the MMR decoding section 38 is put in a deadlock state, and interrupts the MMR decoding process. At the same time, the CPU32 executes a process against the error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a decoding device for encoded data, and particularly to a decoding device for decoding binary image data into MMR encoded data, which is a type of two-dimensional compression code.

[Prior art]

2. Description of the Related Art In facsimile machines, image file devices, and the like, encoding processing for redundancy compression is performed on image data in order to improve memory usage efficiency and transmission efficiency.

In such a device, if there is an error in the encoded data, normal decoding processing will not be executed, making it impossible to reproduce the original image data. Furthermore, even if there is an error in such coded data, if the decoding device does not have a function to detect errors in the coded data, wasteful decoding processing will continue.

In particular, modified modified read (MM
R) The data encoded by the method does not include the line synchronization code in the Modified Huffman method or Modified Read method, so there is an error in the encoded data and the decoding process is normal. If this is not done, there is an inconvenience that the subsequent data (all data) from the erroneous data will not be decoded correctly.

〔the purpose〕

The present invention has been made in view of the above points, and it is an object of the present invention to provide a decoding device that can reliably recognize decoding errors when decoding encoded data and can efficiently deal with the errors.

〔Example〕

The present invention will be explained below using preferred examples.

FIG. 2 is a block diagram showing the overall configuration of a facsimile machine to which the present invention is applied.

In the figure, 1 is a CPU which is the central control unit, and 2 is a floppy disk.
Disk controller section, 3 is a serial interface section that interfaces with the keyboard, 5 is a CPU I
6 is a floppy disk driver section used for backup etc., 7 is a keyboard section used for inputting commands, 9 is a mouse used for image manipulation, etc.; 10 is a display device, 11 is a mouse interface controller, 13 is an image display processor, 14 is a frame memory for storing image data, etc., 15 is a window memory for storing MMR encoded data, etc., 16 is an MMR encoding/decoding device, 17 is an I10 control section, 18 is a line interface section A119 is a line interface section B, 20 is a hard disk controller section, and 21 is a part of a hard disk driver.

An explanation will be given regarding FIG. 2.

The line interface unit B19, which performs data transmission and reception processing with the line side, sequentially receives MMR encoded data sent from the line side.
notifies the line interface unit A18 of reception of the MMR encoded data and transfers the received data.

The line interface unit A18 notifies the inter-CPU interconnect CPUUI of the reception via the system bus SB, and also takes in the transfer data from the line interface unit B19. When the reception is finished and all the transfer data from the line interface unit B19 has been taken in, the line interface unit A18 notifies the CPUI of this fact, and the CPUI transfers the data from the line interface unit A18 to the hard disk controller 20 via the system bus SB. The received data is transferred to the hard disk driver 21 and stored in the hard disk.

The procedure for decoding the MMR encoded data received from the line side, stored in the hard disk driver 21, and outputting it to the printer in this manner is as follows.

The CPUI transfers the MMR encoded data stored in the hard disk driver 21 to the hard disk controller 20.
and the system bus SB to the window memory 15.

After that, the CPUI sends the MMR code/decoder 16
A decoding request command is sent between the CPUs.

Upon receiving the request command, the MMR code/decoder 16 sequentially receives MMR encoded data from the area on the window memory 15 specified by the CPUI via the system bus SB by DMA transfer. The MMR encoding/decoding device 16 sequentially executes decoding processing, and the decoded image data is DMA-transferred to an area on the frame memory 14 designated by the CPUI via the image bus IB.

The MMR encoding/decoding device 16 executes the decoding process on all areas of the window memory 15 designated by the CPUI, and then returns a response indicating the end of the decoding process to the CPU 1. The CPUI receives the response and
An output request command to the printer is sent to the I10 control unit 17, and the I10 control unit 17 transfers image data from the area of the frame memory 14 designated by the CPUI and outputs the image information to the printer.

Similarly, when outputting to the display device 10, the image data stored in the window memory 15 is transferred to the frame memory 14, and the image display processor 13 accesses the frame memory 14, thereby displaying the image data on the display.

The above is the procedure up to outputting an image based on MMR encoded data received from the line side to the printer and display device 10. Next, the procedure up to sending the image data read from the scanner to the line side is described below. Describe.

When the scanner notifies the I10 control unit 17 of a start signal to start reading, the I10 control unit 17 receives the signal and notifies the CPUI of the information. CPU
I instructs the I10 control unit 17 to read the original image using the scanner. In accordance with the instruction, the I10 control unit 17 starts reading from the scanner and sequentially stores the read image data into the window memory 15 specified by the CPUI via the image bus IB.

When reading from the scanner is finished, the I10 control unit 17 notifies the CPUI of the completion. Upon receiving the notification, the CPUI sequentially stores the image data stored in the window memory 15 in the hard disk driver 21 via the hard disk controller 20 via the system bus SB.

In this way, MMR encoding of the image data stored in the hard disk driver 21 is performed as follows.

The CPUI transfers the image data stored in the hard disk driver 21 to the frame memory 14. When the transfer is completed, the CPUI sends an encoding request command to the MMR encoder/decoder 16. Upon receiving the encoding request command, the MMR encoding/decoding device 16 sends the CPU
Image data is received from the frame memory 14 specified by I by DMA transfer via the image bus IB.

The MMR encoding/decoding device 16 sequentially converts the image data into M
MR encoding is performed, and the MMR encoded data is stored in an area designated by the CPUI on the window memory 15 via the system bus SB.

When MMR encoding is completed for all the image data on the frame memory 14 specified by the CPUI, the MM
The R encoding device 16 returns a response indicating the end of encoding to the CPUI.

In response to the response, the CPUI stores the MMR encoded data on the window memory 15 in the hard disk driver 21 via the system bus SB and the hard disk controller 20.

The CPUI is M stored in the hard disk driver 21.
MR encoded data to hard disk controller I roller 20
and the system bus SB to the line interface section A18.

The CPUI notifies the line interface unit A18 of the transmission. Line interface unit A18 receives the transmission notification and requests line interface unit B19 to execute the transmission process. In response to the request, the line interface section B19 receives the transmission MMR encoded data from the line interface section A18, and executes transmission processing on the line side.

FIG. 3 shows the MM stored in the window memory 15 during the decoding operation in the facsimile machine shown in FIG.
A state in which R encoded data is decoded by the encoder/decoder 16 and image data obtained for each scanning line is stored in the frame memory 14 is shown. In this way, MMR encoded data does not have a line synchronization signal or the like, and encoded data for one screen is continuous without boundaries, and this is decoded into image data for each scanning line.

FIG. 1 is a block diagram showing an embodiment of an MMR decoding device within the encoding/decoding device 16 shown in FIG.

22 is an address comparator section, 23 is a FIFO section,
24 and 44 are tri-state buffer sections, 25 and 4
5 is a bidirectional transceiver, 26 and 46 are bus controllers, 27 and 47 are bus arbiters, 28 is an I10 address decoding unit, 29 is a programmable timer device, 30 is an interrupt signal generator, and 31 is a 2-channel DM
A controller, 32 is CPU, 33 is address latch, 34 is ROM, 35 is RAM, 36 is I10 boat register, 371;! A FIFO section, 38 an MMR decoding section, 39 an S/P conversion section, 40 an output I10 boat register, and 41 a timing signal generator.

FIG. 4 shows the M M Rf! shown in FIG. 1. 3 is a flowchart showing the overall processing procedure of the encoding device.

The operation of the MMR decoding device shown in FIG. 1 will be explained.

First, a channel attention indicating the presence or absence of a command is sent from the CPUI shown in the second diagram via the system node SB. A channel attention is an I10 message consisting of a code indicating a channel command and a CPU number.
The address notifies the other CPU of the arrival of the command.

Assume that a channel attention indicating a decoding request command is generated from the CPU 32 shown in the first diagram from the CPU 32 shown in the second diagram.

The CPU number included in the channel attention input from the system bus SB is compared with the own CPU number by the comparator 22, and if it is determined that the channel attention is addressed to the own CPU, the FIF
Partner C included in channel attention in O element 23
Import the PU number. As a result, the FIFO element 23 generates an interrupt I/R1 to the CPU 32, and this interrupt causes the CPU 32 to read the partner CPU number from the FIFO section 23.

After checking the other party's CPU number, the CPU 32
After setting various parameters in the channel DMA controller 31, it is activated.

As a result, 2-channel DMA controller 31 sends an address signal to address bus AB.

At the same time, system node SB is sent to bus arbiter 27.
When the bus arbiter 27 acquires the node, it notifies the bus controller 26 of the acquisition. As a result, the bus controller 26 controls the system bus SB.
A memory read signal is sent between the

The bus arbiter 27 also includes a bidirectional transceiver 25,
It also notifies the tri-state buffer section 24 of the bus acquisition. Thereby, the tri-state buffer unit 24 sends an address signal to the system bus SB. Furthermore, the command contents are read from the inter-CPU communication area placed in the frame memory 14 shown in the second figure via the system bus SB.

Thereafter, all command contents are read using the same procedure. The command contents read from the inter-CPU communication area of the frame memory 14 via the system bus SB are as follows:
The data is stored in the RAM 35 via the bidirectional transceiver 25 and the data bus DB.

The CPU 32 analyzes the command stored in the RAM 35 in this way, and when determining that it is a decoding request command, the CPU 32 sets the storage address of the MMR encoded data on the window memory 15 shown in the second figure added to the command to 2 channels. D
Set the address of the image data area on the frame memory 14 to the MA controller 31, and set the address of the image data area on the frame memory 14 to channel 2 D.
Set it in the MA controller 31.

Furthermore, the CPU 32 causes the address decoding unit 28 to
MM is activated and the output address code signal is activated.
The number of image bits of one scanning line added to the analyzed decoding request command is set for the R decoder 38. Also,
Prior to decoding, the CPU 32 sets a timer value in the programmable timer device 31 for the time required to generate one scanning line worth of image data by the decoding operation.

Next, the CPU 32 instructs the start of a DMA transfer operation of the MMR encoded data from the window memory 15 in FIG. 2 to the decoding device in FIG. register 36
MMR until the FIFO section 37 becomes full via
DMA transfer the encoded data. At this time, the bus controller 26, bus arbiter 27, bidirectional transceiver 2
5 and the I10 boat register 36 are the same as those for command DMA transfer, except that the DMA transfer destination is changed from the RAM 35 to the I10 boat register 36.

Next, the CPU 32 requests the MMR decoding unit 38 to start decoding via the data bus DB and address bus AB, and instructs the 2-channel DMA controller 31 to start executing the 2-channel DMA operation.

In the MMR decoding section 38, the MMR decoding section 38 receives the MMR data from the FIFO section 37.
Decoding of the encoded data is started in accordance with the timing clock CLK from the timing signal generator 41. When decoding is started, the MMR decoding unit 38
requests MMR encoded data from the FIFO section 37, and
Serial image data generated by decoding operation is S/P
The image is sent to a converter 39 and converted into a parallel word image.

When the word conversion for one word is completed, the S/P converter 39
The enable signal for clock transmission to the timing signal generator 41 is turned off, and the 2-channel DMA
A DMA request DMA 1 is sent to the controller 31 to DMA transfer the decoded image data to the frame memory 14 via the image bus IB.

On the other hand, in the FIFO section 37, the M
When the MR encoded data does not satisfy the full condition, a DMA request DMA 2 is issued to the 2-channel DMA controller 31 requesting DMA transfer of the MMR encoded data from the system bus SB. Here, the DMA request DMA2 on the MMR encoded data side has a higher priority than the DMA request DMA1 on the image data side. Therefore, the CPU 32 receives the DMA request D.
If MA2 exists, DMA transfer on the MMR encoding side is executed first even if there is a DMA request DMA1.

The procedure for DMA transfer of MMR encoded data from window memory 15 via system bus SB is as described above.

When the DMA transfer on the MMR encoded data side is completed, the DM
DM on the image data side in response to A request DMA 1
A transfer is started. In the DMA read cycle, I1
The parallel word image data is read from the 0 port register 40, and in the next DMA cycle, the image bus I
A request is made to the bus arbiter 47 on the B side to acquire the image bus IB, and when the bus is acquired, the bus arbiter 47 sends the bus controller 46, both transceivers 45, and tri-state buffer section 44. shall be notified of this.

As a result, the bus controller 46 controls the image bus I
A memory write signal is sent to B.

The tri-state buffer section 44 sends an address signal to the image bus IB, and the parallel word image data read from the I10 port register 40 is sent to the frame memory 1 shown in the second figure via a bidirectional transceiver 45.
It is stored in 5.

Furthermore, when the parallel word image data is read from the I10 boat register 40, the next encoding is executed.

By the above procedure, the MMR corresponding to one scanning line is
After decoding the encoded data, one scanning line of parallel word image data converted by the S/P converter 39 is I1
0 vote register 40, frame memory 1
After completing the DMA operation to 5, the 2 channel DM
The A controller 31 generates an interrupt to the CPU 32. As a result, the CPU 32 performs the 2-channel DM
2 for the DMA on the image data side of the A controller 31.
After setting the parameters for the scanning line and the timer value in the programmable timer device 29, the 2-channel DMA controller 31 is restarted.

The same procedure as above is repeated for each scanning line.

When the final scanning line is entered and the MMR decoding unit 38 detects an RTC indicating the end of one screen of images in the MMR encoded data from the FIFO unit 37, the MMR decoding unit 38 sends an interrupt signal 1/R2 to the CPU 32. to notify. CPU
32 receives the interrupt signal I/R2, determines that the MMR decoding is final, waits for the end of the DMA transfer of the final parallel image data, completes the MMR decoding process, and sends a response to the CPUI shown in the second figure. Send it back.

During the above MMR decoding, the MM in the FIFO section 37
If there is an error in the R encoded data and a decoding error occurs in the MMR decoding section 38, the MMR decoding section 38 may fall into a deadlock state in which normal decoding operations cannot be performed.

Here, the state is constantly monitored by the programmable timer device 29. That is, the programmable timer device 29, which is set as a timer value, takes the time required to generate an image for one scanning line in normal MMR decoding processing.
If it exceeds that time, it will time out. In other words, MMR
If the decoding process for one scanning line in the decoding section 38 is not completed by the time up of the programmable timer device 29, the programmable timer device 29 sends a timeout pulse to the interrupt signal generator 30.

In response to the pulse, the interrupt signal generator 30 interrupts the CPU 3.
2 and notifies the CPU 32 of the interrupt signal I/R3.

Upon receiving the interrupt signal, the CPU 32 determines that an error has occurred in the MMR decoding process that was being executed up to that point, and that the MMR decoding unit 38 is in a deadlock state.
The MMR decoding process is interrupted and error handling is executed. Furthermore, a response is returned to the CPUI, the series of MMR decoding processes is completed, and preparation is made for the next MMR decoding process request.

The timer value set in the programmable timer device 29 is set to be slightly longer than the maximum required time for normal decoding processing, and is variable depending on the image length per scanning line of the image to be decoded. It is set.

Note that although this embodiment has described decoding of MMR encoded data, the present invention is similarly applicable to decoding of encoded data using other encoding methods.

It goes without saying that the present invention can also be applied to other devices other than facsimile devices, such as image file devices.

〔effect〕

As described above, according to the present invention, it is possible to provide a decoding device that can reliably recognize the occurrence of a decoding error in the decoding process, thereby improving the reliability of the system. be.

[Brief Description of the Drawings] Figure 1 is a block diagram showing an example of the configuration of an MMR decoding device to which the present invention is applied, Figure 2 is a block diagram showing the overall configuration of a facsimile machine, and Figure 3 is MMR encoded data. FIG. 4 is a flowchart showing the procedure of MMR decoding processing, and 1 is a CPU
. 14 is frame memory, 15 is window memory, 16
29 is a programmable timer, and 38 is an MMR decoding unit.

Claims (1)

[Claims] In a decoding device that decodes encoded data, when decoding encoded data, a decoding error occurs if the decoding of one scanning line of image data is not completed within a predetermined time. A decoding device characterized by recognition.