JPS6359064A - Coder for picture data - Google Patents

Abstract

PURPOSE:To code a picture data at a high speed and to code even a picture data intermittently supplied with a high efficiency by DMA transferring the picture data from a picture memory to a coder and supplying a reference signal to operate the coder to the coder synchronously with the DMA transfer of the picture data. CONSTITUTION:An I/O control section 17 stores a picture data obtained through the read of an original picture by means of a scanner to an area of a window memory 15 designated by a CPU 1 via an image bus 8 sequentially. The CPU 1, upon the receipt of the notice of end of read, stores the picture data stored in the window memory 15 into a hard disk driver 21 sequentially. The CPU 1 transfers the stored picture data to a frame memory 14. An MMR coder/ decoder 16 receives a coding request command from the CPU 1 and receives the picture data in parallel by one word each through the DMA transfer from the frame memory 14 designated by the CPU 1. Then the MMR coder/decoder 16 applies MMR coding the picture data sequentially.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an encoding device, and particularly to an image data encoding device for encoding binary image data.

[Prior art]

2. Description of the Related Art Conventionally, in transmitting image data such as by facsimile or storing image data such as image files, encoding processing is performed to compress the redundancy of image data in order to improve transmission efficiency and storage efficiency.

This type of encoding processing includes modified Huffman (MH) encoding and modified read (MR) encoding.
Encoding, modified modified read (M
MR) encoding etc. are often used.

For example, in two-dimensional encoding such as MMR encoding, encoding is performed based on the correlation between the image line to be encoded and the previous image line, but this correlation is determined by a microcomputer, etc. In many cases, this is done by software processing, and the timing 9 for taking in data to the encoding section is also controlled by a microcomputer.

Therefore, the encoding operation is limited by the processing speed of the microcomputer, making it difficult to perform a high-speed encoding operation.

Therefore, it is conceivable to configure the encoding section with a hardware circuit that does not rely on a microphone or a computer to perform high-speed processing, but it has been difficult to apply this to encoding.

〔the purpose〕

The present invention has been made in view of the above points, and it is an object of the present invention to provide an image data encoding device that can encode image data at high speed and efficiently even when image data is supplied intermittently. purpose.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings. In this embodiment, a case will be described in which the present invention is applied to MMR encoding for two-dimensionally encoding image data.

FIG. 1 is a block diagram showing the overall configuration of a facsimile machine according to an embodiment of the present invention. In FIG. 1, l is a CPU consisting of a well-known microprocessor, 2 is a floppy disk controller section, 3 is a serial interface section, 4 is a system bus, 5 is a main storage device that stores CPU programs, and 6 is a user program. 7 is a keyboard section for the user to input commands, 8 is an image bus, 9 is a pointing device, IO is a display device, ll is an interface controller, 1
3 is an image display processor, 14 is a frame memory, 15
is a window memory, 16 is an MMR code/decoder, and 17 is a window memory.
is I10 control section, 18 is line interface section A, 19
A line interface section B120 is a hard disk controller, and 21 is a hard disk driver.

First, FIG. 1 will be explained.

The line interface section B19, which performs data transmission/reception processing with the line side, sequentially receives MMR encoded data sent from the line side. Further, the line interface unit B19 that has received the MMR encoded data notifies the line interface unit A18 that it has received the MMR encoded data, and transfers the received data to the line interface unit A18. Thereby, the line interface section 1118 notifies CI' U ] of the reception of the MMR encoded data via the system bus 4 through inter-CPU communication, and also takes in the transfer data from the line interface section B19. After the reception of the MMR encoded data sent from the line side is completed, the line interface section B1
When all of the transfer data from 9 has been taken in, the line interface section B19 notifies the CPUI of this fact. Thereby, the CPUI transfers the received data from the line interface unit A18 via the system bus 4 to the hard disk driver 21 via the hard disk controller 20, and stores the received data.

The procedure for decoding the MMR encoded data received from the line side, stored in the hard disk driver 21, and outputting it to the printer is as follows.

The CPU 1 transfers the MMR encoded data stored in the hard disk driver 21 to the hard disk controller 2.
0 to the window memory 15. After that, CPtJl instructs the MMR code/decoder 16 to
A decryption request command is sent through inter-communication. MMR
Upon receiving the request command, the code/decoder 16
M from the area on window memory 15 specified by t
MR encoded data is sequentially received in parallel for each l word by DMA transfer.

The MMR encoding/decoding device 16 sequentially executes decoding processing, and the decoded image data is transferred to an area on the frame memory 14 specified by the CPU via the image bus 8.
DMA transfer is performed in parallel word by word.

The MMR encoding/decoding device 16 performs decoding processing on data in all areas of the window memory 15 designated by the CPUI, stores all the decoded data on the frame memory 14, and then instructs the CPUI to perform the decoding processing. Return a completion response. Upon receiving the response, the CPUI sends an output request command to the printer to the I10 control unit 17, and the I10 control unit 17 reads the decoded image data from the area of the frame memory 14 specified by the CPUI. , transferred via the image bus 8,
Output the image information to the printer. Then, a printer records an image on a recording material such as paper based on the received image data.Also, when outputting to the display device 10, the image data stored in the window memory 15 is decoded and processed. The received image data is then transferred to the frame memory 14, and the image display processor 13 accesses the frame memory 14 to display an image based on the received image data on the display device 10.

The above is the procedure for outputting the MMR encoded data received from the line side to the printer and display device 10. Next, the procedure for encoding and transmitting the image data read from the scanner to the line side is as follows. Describe.

Start signal indicating a request to start reading from the scanner Month 1
0 control unit 17 is notified. The I10 control unit 17 receives the signal and notifies the CPU 1 of the information. C
The PUI instructs the I10 control unit 17 to start reading with the scanner. In accordance with the instructions, the I10 control unit 17 causes the scanner to start reading, and the image data obtained by reading the original image with the scanner is stored in the window memory 15 specified by the CPU 1 via the image bus 8.
are stored sequentially in the area. When reading from the scanner is finished, the I10 control unit 17 notifies the CPUI of the completion. Upon receiving the notification, the CPU 1 sequentially stores the image data stored in the window memory 15 in the hard disk driver 21 via the hard disk controller 20 via the system bus 4.

In this way, MMR encoding of the image data stored in the hard disk driver 21 is performed as follows.

The CPUI transfers the image data stored in the hard disk driver 21 to the frame memory 14. When this transfer is completed, the CPUI
6, sends an encoding request command. Upon receiving the encoding request command, the MMR encoding/decoding device 16
Image data is received word by word in parallel from the frame memory 14 designated by the CPUI via the image bus 8 by DMA transfer. And MMR code/decoding 1
6 device sequentially MMR encodes the image data, and the MMR encoded data is stored in C on the window memory 15.
It is stored in the area specified by the PUI via the system bus.

When MMR encoding is completed for all the image data on the frame memory 14 specified by the CPUI, the MM
The R code/decoder 16 returns a response indicating completion of encoding to the CPUI. In response to the response, the CPUI stores the MMR encoded data on the window memory 15 in the hard disk driver 21 via the hard disk controller 20 via the system bus 4.

In this way, the CPUI installs the hard disk driver 2.
The MMR encoded data stored in 1 is transferred via the hard disk controller 20 and further via the system bus 4 to the line interface section A18.

Also, at this time, the CPU 1 uses the line interface section A.
18 is notified of the transmission. Line interface part A
18 receives the transmission notification and requests the line interface section B19 to execute the transmission process. In response to the request, the line interface section B19 receives the MMR encoded data to be transmitted from the line interface section A18, and executes transmission processing on the line side.

FIG. 2 shows how the image data stored in the frame memory 14 is subjected to MMR encoding for each -scanning line in the MMR encoding/decoding device 16 shown in FIG.

Further, FIG. 3-1 shows the MMR code/decoder 1 shown in FIG.
FIG. 6 is a block diagram showing the configuration of an embodiment of the encoding unit No. 6; FIG.

In Figure 3-1, 22 is a CPU, 23 is a RAM device, 24 is a ROM device,
25 is an address latch, 26 and 56 are bus arbiters, 27 and 57 are bus controllers, 28 and 58 are bidirectional transceivers, 29 and 59 are tristate buffer elements, 30 and 50 are buffer elements, and 31 is an address decoding section. , 32 and 52 are FIFO units, 33 is an address bus, 34 is a data bus, 36 is an I10 boat register, 37 is a P/S conversion unit, 38 is an MMR encoder, 3
9 is a NAND element, 40 is an A N D element, 42 is an OR element
43 is a horizontal synchronous signal generator, 44 is a vertical synchronous signal generator, 45 is a comparator, 46 is a 2-channel DMA
The controller 48 is a timing generator.

An explanation will be given regarding FIG. 3-1. Further, FIG. 5 shows the operating procedure.

A channel attention indicating the presence or absence of a command is applied from the CP [, + 1 shown in the first diagram] via the system bus 4. I10
The destination CF'U is notified of the arrival of the command using the address. This channel attention is taken into the comparator 45 via the buffer element 30, and compared with the own CP 11 number, and if it is determined that it is addressed to the own CP U, the FI
The partner CPU number that generated the channel attention is loaded into the F0 section 32.6 At this time, the FIFO section 32
generates an interrupt to the CPU 22, which causes CI)
The IJ 22 reads the other party's CI) U number from the FIFO unit 32.

After checking the partner CP tJ number, CPU2
2 activates the DMA controller 46, and the DMA controller 46 sends an address signal to the address bus 33. At the same time, for the bus arbiter 26,
It requests acquisition of the system lotus 4, and when the bus is acquired, it notifies the lotus controller 27 of the acquisition. The HAS controller 27 exchanges C-memory control information with the system bus 4.

The bus arbiter 26 also includes a bidirectional transceiver 28
Also for the trice date buffer element 29,
Notify you of lotus acquisition. Tri-state buffer element 2
9 crosses over to the system hub 4 and sends out an address signal. Furthermore, the command contents are read from the CPU-to-CPU communication area located in the frame memories 1, 1 shown in FIG. 1 through the bidirectional transceiver 28.

FIG. 3-2 shows the area for communication between CPUs placed in the frame memory 14 shown in FIG. 1.

C)) The command content read from the U-to-U communication area is transmitted via the system hash 4 and the two-way transceiver 28.
It is stored in the RAM device 23. CPU 22 is R
When the command stored in the AM device 23 is analyzed and determined to be an encoding request command, the address of the image data area on the frame memory 14 shown in the first diagram added to the command is sent to the 2-channel DMA controller 46. Also, the storage address of the MMR encoded data on the window memory 15 shown in the first figure given to the command is set in the two-channel DMA controller 46. Furthermore, CP
U22 activates the address decode section 31, and uses the address decode signal to activate the horizontal synchronization signal generator 43.
Also, the number of image hits of one scanning line added to the command is set for the MMR encoder 38.

Now, we will start the actual operation of encoding the image data, and FIG. 4 shows an operation timing chart related to the encoding operation. First, the M M Ri encoder 38 is supplied with a timing clock from the timing generator 48 via the A N 1) element 110 and the OR element 42 . The MMR decoupler 38 performs a signal operation when the timing clock is supplied, and interrupts the encoding operation by stopping the supply of the timing clock.

The CPU 22 activates the address decoding section 31, and uses the address decode signal generated at this time to request the vertical synchronization signal generator 44 to generate a vertical synchronization signal.

As a result, the vertical synchronization signal generator 44 generates a vertical synchronization signal indicating the input period of image data for one screen, and
The MR encoder 38 and NAND element 39 are notified of the occurrence. Similarly, the CI) U 22 activates the address decoding section 31, and the horizontal synchronizing signal generating section 4
3 to generate horizontal synchronization signal 1. As a result, the horizontal synchronization signal generator 43 generates a horizontal synchronization signal indicating the input period of image data for one scanning line, and notifies the MMR archer 38 and the NAN I') element 39 of its generation. . At this time, the supply of the timing clock from the timing generator 48 to the MMR encoder 38 via the NAN I) element 39, AND element 40, and OR element 42 is stopped. Therefore, the MMR encoder 38 has stopped the encoding operation.

In the above-L state, the CP IJ 22 instructs the I) MA controller 46 to start the DMA-It cycle.

]) MA request from the P/S converter 37, 1
) MΔ controller 46 sends out an address signal via r) MA cleat cycle, and at the same time requests the bus arbiter 56 to acquire the image bus 8. When acquiring the lotus, it requests the bus controller 57 to acquire the image bus 8. Notice. The bus controller 57 exchanges memory control signals with the image bus 8.

Further, the lotus arbiter 56 has a bidirectional transor/<58,
Also, the tri-state buffer element 59 is notified of the acquisition of the lotus.

After this, the l.Rice date buffer element 59 sends the previously set address transmission to the image hash 8. Then, the frame memory 14F shown in the first diagram
DM image data from the image data area in 1 word units from the bidirectional transceiver 58 via the image lot 8.
The data is read into the A controller 46. One word of image data read into the DMA controller 46 is transferred to the next D
M A write cycle, I10 boat register 3
It is latched to 6. At the same time as it is latched into the I10 port register 36, the image data in the I10 port register 36 is transferred to the P/S converter 37. At this timing, the P/S converter 37 sends a clock enable signal to the ANr) element 40, and sends a timing clock signal to the MMR encoder 38 via the ANr) element 40 and the OR element 42. is supplied (as shown in the fourth figure), and
As shown in FIG. 4, a serial conversion timing pulse is applied from the I10 boat register 36 to the P/S converter 37.

This changes the data in /'0 port register 36))
/S converter 37 and into the river as shown in the fourth figure (]
, /'0 From the port register 36 to the P/8 conversion unit: (P/8 conversion enable input is applied to 7. Therefore, l
)/8 converter 37 performs parallel/serial conversion of the image data, and the serially converted image data is converted into 16 bits (MMR encoder;
input as serial image data (pixels). After one word of parallel/norial conversion is performed, I)
/S converter 37 sends a clock enable signal to AN I-) element 40! , thereby turning off the MMR encoder 38 via the AND element and the OR element 42.
Timing clock supply to the system stops. Furthermore, a DMA request is sent to the DMA controller 46, requesting DMA transfer of the image data to be encoded to the I10 boat register 30.

By the above operation, D for -scanning line worth of image data is
MA is performed in units of l words and is input to the MMR encoder 38 as serial data.

- When the input of the image data for the scanning line to the MMR encoder 38 is completed, the generation of the horizontal synchronization signal stops, and thereby the timing clock is is supplied to the MMR encoder 38, and the MMR encoder 38 encodes the thus inputted image data according to a well-known MMR encoding procedure. Incidentally, MMR encoding is explained in detail in Japanese Patent Application No. 170803/1983.

Also, the MMR initialized data outputted from the MMR encoder 33 at this time is outputted to the F I F 0 section 52 in accordance with the timing pulse outputted from the MMR encoder 38 . When the MMR encoded data is input to the FIF0 unit 52, a DMA request is sent to the DMA controller 46. Here, in comparison with the DMA request requesting the capture of image data to be encoded output from the P/S converter 37, the F I F 0 section 52
DMA requests output from the DMA request have a higher priority. Therefore, when the FI F 0 section 52 issues an MA request (1) as shown in the fourth diagram, the DMA controller 46 sends the M
Read the M R encoded data I) Start the M A read cycle, I) In the M A write cycle, use the control signals of the bus arbiter 26 and the controller 27 to perform the same procedure as on the image bus 8 side. MM is connected to the system bus 4 side via the bidirectional transceiver 28.
R code data is sent. The data sent to the system hub 4 side is stored in a preset address area of the window memory 15 shown in the first diagram.

Window memory 15 for image data for one scanning line
When I) MA to CI) is performed, an interrupt is generated to CI) U 22. The CPU 22 thereby sets the DMA parameters (memory address, etc.) for the second scanning line to the DMA controller 46,
Restart the DMA controller 46. Similarly, the MMR encoded data generated by the encoding operation is also
The data are sequentially stored in the window memory 15 shown in the figure.

When the image data of each scanning line is encoded repeatedly as described above and the image data of all the scanning lines has been MMR encoded, the CPU 22 writes a response to the RAM device 23 and stores the contents of the response. The DMA controller 46 performs DMA transfer in a similar manner to the inter-CPU communication area located in the frame memory 14 in FIG. 3-1.

Furthermore, the MMR decoding process is completed by applying channel attention to the CPUI shown in FIG. 1 via the system bus 4 and notifying the CPUI.

In this embodiment, the present invention was applied to MMR encoding, but the present invention can also be applied to other encoding operations such as modified read (MR) encoding and modified Huffman (MH) encoding. It is.

〔effect〕

As described above, according to the present invention, the image data to be encoded is transferred to the encoder at high speed by DMA transfer, and the encoding operation is performed in accordance with the DMA, so that the system design is flexible. Not only is this possible, but also high-speed encoding is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a facsimile device to which the present invention is applied, FIG. 2 is a diagram showing an image data encoding operation, and FIG. 3-1 is a block diagram showing an example configuration of an MMR encoding device. 3-2 is a diagram showing the area for communication between CP0, FIG. 4 is a timing chart diagram showing the serial conversion operation of image data, and FIG. 5 is a flowchart diagram showing the procedure of the encoding operation. 1 is CPtJ, 4 is system bus, 8 is image bus,
14 is frame memory, 15 is window memory, 16
is an MMR encoder/decoder, 37 is a P/S converter, and 38 is an MMR encoder/decoder.
MR encoder, 48 is a timing generator, and 46 is a DMA controller.

Claims (1)

[Claims] In an image data encoding device that transfers image data stored in an image memory to an encoder and encodes it, the image data is transferred from the image memory to the encoder by DMA, and it is synchronized with the DMA transfer of image data. 1. An image data encoding device characterized in that image data that is intermittently transferred by DMA is encoded by supplying a reference signal for operating the encoder to the encoder.