JP7313840B2 - Information processing device, control method for information processing device, and program - Google Patents

Description

The present invention relates to an information processing device, a control method for the information processing device, and a program.

2. Description of the Related Art In recent years, there are information processing apparatuses equipped with NAND flash memories such as eMMCs (embedded Multi Media Cards) and SSDs (Solid State Drives) as auxiliary storage devices.

In the NAND flash memory, the data size written by the host system and the data size actually written to the NAND flash memory (hereinafter referred to as actual write data size) may differ depending on the state when new data is written. Data writing to the NAND flash memory is performed in page units (4 KBytes, for example). On the other hand, erasure of data in the NAND flash memory is executed in units of blocks (64 KBytes, for example) consisting of a plurality of pages. When writing new data to a page in which data has already been written, the NAND flash memory erases the entire block containing the page and writes the new data to be written together with the erased data. Therefore, the actual write data size to the NAND flash memory is larger than the data size instructed to be written by the host system. A WAF (Write Amplification Factor) is the ratio of the actual write data size of the NAND flash memory to the data size instructed to be written by the host system.

For example, when writing 2 KBytes of data from the host system, 62 KBytes of data may be written to the block to which the data is written. At this time, the already written data of 62 KBytes is deleted, and the data of 64 KBytes obtained by adding the data of 2 KBytes to the data of 62 KBytes is written to the NAND flash memory. In the above case, the WAF will be 31.

The eMMC, which is an embedded memory as a NAND flash memory, does not store the actual write data size to the NAND flash memory. Therefore, the host system cannot obtain the data size actually written to the NAND flash memory, and the host system cannot know how much data has been written to the NAND flash memory of the eMMC.

In order to address the above-described problem, for example, in Patent Document 1, the amount of data written within a certain period of time is estimated by multiplying the data size instructed to be written by the host device within a certain period of time by the WAF.

JP 2015-198377 A

By the way, in a NAND flash memory such as eMMC, there is an upper limit to the total amount of write data size, and if data is written exceeding the upper limit, the data is not guaranteed. In order to guarantee data stored in the NAND flash memory, the total write amount to the NAND flash memory must not exceed a predetermined upper limit.

However, as described above, since the eMMC does not store the actual write data size, the host system cannot calculate the total write data size to the NAND flash memory of the eMMC. Therefore, there is a possibility that the size of data written to the NAND flash memory of the eMMC will exceed the guaranteed upper limit without the user noticing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide notification so that the total write data size does not exceed the data guaranteed upper limit even when the actual write data size to the NAND flash memory is unknown.

The present invention provides a nonvolatile semiconductor memory device for storing data and a memory device for each data size.WAFan information processing device comprising: an instruction means for instructing the semiconductor storage device to write data; a counting means for counting the number of write instructions of the data size of the data instructed to be written for each data size; a calculation means for calculating a write size corresponding to the data size of the data instructed to be written;AccumulationdoAccumulationmeans andAccumulationand notification means for notifying when the written size satisfies a predetermined condition with respect to a threshold value, and the calculation means corresponds to the data size of the data instructed to be written and the data size of the data instructed to be written.WAFand the number of write instructions, the write size is calculated.

According to the present invention, even if the actual write data size to the memory is unknown, it is possible to warn the user so that the total write data size does not exceed the upper limit.

1 is a diagram illustrating an example of a configuration of an image forming apparatus 100 in Examples 1 and 2; FIG. 4 is a diagram showing an example of the configuration of a WAF management table in Examples 1 and 2; FIG. 6 is a flowchart of WAF management table selection processing in the first and second embodiments; FIG. 10 is a diagram showing a flowchart of eMMC write processing in the first embodiment; 4 is a diagram showing an example of a configuration of a descriptor table 500 in Examples 1 and 2; FIG. FIG. 10 is a diagram showing a flowchart of actual write data size addition processing in the first and second embodiments; 7 is a flowchart of life determination processing 700 in the first and second embodiments; 10 is a flowchart of eMMC write processing 800 in Example 2. FIG. 10 is a flowchart of actual write data size subtraction processing 900 according to the second embodiment; FIG. 11 is a diagram illustrating an example of the configuration of an image forming apparatus in Examples 3 and 4; FIG. 11 is a diagram showing a flowchart of eMMC write processing in the third embodiment; 10 is a flowchart of write data size count-up processing in the third and fourth embodiments; 7 is a flowchart of actual write data size addition processing in the first and second embodiments; 14 is a flowchart of timer interrupt processing, power state transition processing, and shutdown processing in Embodiments 3 and 4; 14 is a flowchart of eMMC write processing in Example 4. FIG. FIG. 14 is a flow chart of write data size countdown processing in the fourth embodiment. FIG.

(Example 1)
EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing this invention is demonstrated using drawing. Note that the present embodiment will be described using an image forming apparatus as an example of an information processing apparatus. An information processing apparatus other than the image forming apparatus, such as a computer or a tablet terminal, may execute the following processing.

FIG. 1 shows the configuration of an image forming apparatus 100 according to the first embodiment.

The main SoC 101 (System on a Chip) is an integrated circuit component and includes a CPU 102, image processing hard logic 103, and memory I/F 104, which will be described later. The main SoC 101 also includes control interfaces such as a RAM 106, a ROM 107, and a UI 108, which will be described later, and a system bus connecting them, but they are not shown in FIG. 1 because they are not directly related to the present invention.

A CPU 102 is a central processing unit for controlling the entire image forming apparatus 100 .

The image processing hardware logic 103 performs image processing such as correction, processing, and editing on the input image data read from the scanner 110 . Furthermore, the image processing hardware logic 103 performs processing such as color conversion, filter processing, and resolution conversion on output image data that the main SoC 101 outputs to the printer 109 .

A host memory I/F 104 is a memory interface including a DMAC 105 (Direct Memory Access Controller). Controlling the DMAC 105 by the CPU 102 enables data input/output between the eMMC 112 and the RAM 106 .

A RAM 106 is a system work memory for the operation of the CPU 102, and stores calculation data of the CPU 102 and various programs. The RAM 106 is also used as an image memory that holds image data that has been subjected to various image processing by the image processing hardware logic 103 during scanning and printing.

A ROM 107 is a boot ROM and stores a boot program for the image forming apparatus 100 .

The UI 108 is a user interface, and includes a liquid crystal display that displays a screen, a touch panel that receives input from the user, hard keys, and the like.

A printer 109 is a printer engine that prints image data on paper, and includes a laser scanner unit, a photosensitive drum, a paper transport unit, and the like.

A scanner 110 is a unit that reads images and characters on paper with a CCD sensor or a CIS sensor and converts them into image data.

The external I/F 111 is an interface for a telephone network, wired LAN, wireless LAN, USB, or the like, and data communication is performed between the image forming apparatus 100 and an external device via each interface.

The eMMC 112 includes a memory I/F 113 , a controller 114 and a NAND flash memory 116 .

The memory I/F 113 is an interface that performs data input/output between the main SoC 101 and the controller 114 under the control of the controller 114 .

The controller 114 is a memory control module that interprets commands received from the main SoC 101 via the memory I/F 113 and performs operations according to the commands. Additionally, controller 114 includes a CID register 115 . The CID register 115 is a register specified by the standard defined by JEDEC, and is an abbreviation for Card IDentification number register. The CID register 115 contains information such as a manufacturer ID indicating the device maker and a product name identifying the device.

The NAND flash memory 116 is a non-volatile NAND flash memory that records data. Data is written to the NAND flash memory 116 by injecting electrons into the floating gates of memory cells in the NAND flash memory 116 under the control of the controller 114 . Image data and the like processed by the image processing hardware logic 103 are written into the NAND flash memory 116 . In the NAND flash memory 116, data writing is performed page by page. Furthermore, in the NAND flash memory 116, data deletion is performed in units of blocks consisting of a plurality of pages. When writing data from the middle of a page, the controller 114 once saves the data of the block containing the page to another memory. Then, the controller 114 deletes the data for each block, and then writes new data, which is a combination of the data originally written in the block and the newly written data, to the NAND flash memory 116 . In order to perform the above processing, in the NAND flash memory, the data size instructed to be written by the CPU 102 via the DMAC 105 and the data size actually written to the NAND flash memory 116 by the controller 114 are different.

FIG. 2 is a WAF management table for managing WAFs for estimating the amount of data actually written to the NAND flash memory 116 when the main SoC 101 writes data to the NAND flash memory 116 in the first embodiment.

The WAF management table shown in FIG. 2 is stored in the eMMC 112. FIG. The WAF management table stores estimated WAF values for each write data size that the main SoC 101 can indicate. In this embodiment, the main SoC 101 estimates the actual write data size to the NAND flash memory 116 by using the WAF stored in the WAF management table. The WAF management table stores WAFs for each data size for multiple types of eMMC. This is because the WAF numerical value can be obtained using the WAF management table shown in FIG. 2 without creating a new WAF management table even if a different type of eMMC 112 is used. Note that it is sufficient if the WAF management table is stored for the type of eMMC in which the WAF management table is stored. In that case, only the WAF for the host write data size may be stored without having the manufacturer ID 201 and product name 202 .

The WAF changes depending on the data size instructed to be written by the main SoC 101, the amount of data currently stored in the NAND flash memory 116, and other conditions. Therefore, the WAF stored in the WAF management table is a numerical value for obtaining the data size estimated to be actually written to the NAND flash memory based on the data size instructed to be written by the main SoC 101 . Also, the WAF stored in the WAF management table may be a value defined by the manufacturer that produces the eMMC.

In general, the smaller the write size, the larger the WAF. Therefore, in the WAF management table shown in FIG. 2, the WAF is set larger as the size of the data designated to be written by the main SoC 101 is smaller.

The WAF also depends on the block size, which is the unit in which the NAND flash memory 116 erases data. The block size differs between device makers, and even between devices of the same maker. Therefore, the WAF management table shown in FIG. 2 stores WAFs for each manufacturer ID indicating device maker and product name indicating device.

"No" 200 is a row serial number in the WAF management table and is used for element management.

A “manufacturer ID” 201 is an ID for specifying the device manufacturer that manufactured the eMMC 112, and is the manufacturer ID of the CID register of the eMMC defined by the standard.

A “product name” 202 is an ID for specifying a device, which is the product name of the eMMC CID register defined by the standard.

“Host write data size” 203 is the data size that the main SoC 101 instructs the eMMC 112 to write. The WAF management table describes all write data sizes that the main SoC 101 may instruct to write. In this embodiment, it is assumed that the main SoC 101, which is the host system, writes data of five different sizes: 4 KBytes, 8 KBytes, 16 KBytes, 32 KBytes, and 64 KBytes.

“WAF” 204 is a WAF value estimated for each data size written by the main SoC 101 to the NAND flash memory. Numerical values described in “WAF” 204 are values calculated from operation simulations and spec sheet values.

FIG. 3 is a flowchart showing processing related to development of the WAF management table executed when the image forming apparatus 100 is started in the first embodiment. The processing illustrated in FIG. 3 is performed by the CPU 102 during the system startup sequence after the power of the image forming apparatus 100 is turned on. A program for executing the process shown in FIG. 3 is stored in the ROM 107, and the CPU 102 develops the program in the RAM 106 and executes the process, thereby realizing the process.

The CPU 102 executes initialization processing of the eMMC 112 (S301). The contents of the processing executed by the CPU 102 in S301 are those specified by the standard. For example, in S<b>301 , the CPU 102 performs register initialization of the eMMC 112 and processing for setting the access speed between the main SoC 101 and the eMMC 112 .

After completing the processing of the eMMC 112, the CPU 102 reads the value of the CID register (S302). As described above, the CID register 115 is a register defined by the standard and contains information such as the manufacturer ID indicating the device maker and the product name identifying the device. At S302, the CPU 102 reads the manufacturer ID and product name from the CID register 115. FIG. The manufacturer ID and product name read here are used to calculate the WAF estimated when the CPU 102 writes data to the eMMC 112 . By using the manufacturer ID and product name read in S302, a WAF corresponding to the type of eMMC 112 built in the image forming apparatus can be used.

Based on the manufacturer ID and product name read out in S302, the CPU 102 expands only the relevant portion of the WAF management table stored in the eMMC 112 into the RAM 106 (S303). For example, if the manufacturer ID read in S302 is 0xEE and the product name is 0x567891234DEF, the CPU 102 expands the rows of Nos. 006 to 010 in the WAF management table of FIG. After developing the WAF management table, the CPU 102 terminates the processing shown in FIG.

FIG. 4 is a flowchart of eMMC write processing in the first embodiment. The eMMC write process is a process for the main SoC 101 to write data to the eMMC 112, and is performed in cooperation with the CPU 102, DMAC 105, and controller 114. FIG. A flowchart showing processing by the CPU 102 is stored in the ROM 107, and the CPU 102 develops the program in the RAM 106 and executes it.

The CPU 102 creates a descriptor table 500 for controlling the DMAC 105 on the RAM 106 (S401). Details of the descriptor table 500 will be described later. In S401, the CPU 102 secures a data area on the RAM 106 for generating a descriptor table.

FIG. 5 shows the structure of the descriptor table 500 in the first embodiment.

As described above, descriptor table 500 is generated by CPU 102 and stored in RAM 106 . The start address of the area storing the descriptor table 500 is set in the register of the DMAC 105 by the CPU 102 . The DMAC 105 accesses the descriptor table 500 based on the set top address and operates according to the contents of the descriptor table 500 .

A Command Number 501 is a command number to be issued by the DMAC 105 to the controller 114 . This command number is synonymous with the command number defined in the standard defined by JEDEC. The DMAC 105 refers to the number stored in the Command Number 501 and determines processing.

A Command Argument 502 is a command argument that the DMAC 105 should issue to the controller 114 . The command argument has contents defined by the standard, and includes, for example, a write destination address when the command issued by the DMAC 105 is a write command.

Block Length 503 is the unit block length of data to be transferred between the DMAC 105 and controller 114 .

A Block Count 504 is the number of blocks transferred between the DMAC 105 and the controller 114 .

A Host Address 505 is an address on the RAM 106 and indicates the top address of data to be transferred between the DMAC 105 and the controller 114 . That is, when performing Write processing for writing data stored in the RAM 106 to the eMMC 112, the Host Address 505 is the address of the RAM 106 where the data to be transferred is stored. On the other hand, when performing Read processing for reading data stored in the eMMC 112 , the Host Address 505 is the transfer destination address of the data read from the eMMC 112 .

Among the contents of the descriptor table, the value obtained by multiplying the value of Block Length 503 by the value of Block Count 504 is the host write data size for the transfer. For example, if the Block Length 503 is 512 Bytes and the Block Count 504 is 8, the host write data size for this transfer will be 4 KBytes. By the above calculation, the CPU 102 can obtain the data size that the main SoC 101 instructs the eMMC 112 to write. Here, the data size that the main SoC 101 instructs the eMMC 112 to write via the DMAC 105 is different from the data size that the controller 114 of the eMMC 112 actually writes to the NAND flash memory 116 .

The CPU 102 sets the start address of the descriptor table 500 stored on the RAM 106 in S401 to the DMAC 105 (S402). The DMAC 105 can acquire the contents of the descriptor table 500 by accessing the address set in S402, and can operate according to the contents set in the descriptor data table 500. FIG.

The CPU 102 turns on the enable register of the DMAC 105 (S403). When the CPU 102 turns on the enable register of the DMAC 105, the DMAC 105 accesses the address set in S402 and starts DMA transfer.

The DMAC 105 issues a write data size setting command to the controller 114 based on the contents of the descriptor table 500 (S404). In S404, the CPU 102 acquires the unit block length and the number of blocks stored in the descriptor table 500, and issues a command. The CPU 102 issues a command CMD16 setting the block length to the controller 114 of the eMMC 112 and a command CMD23 setting the number of data blocks to be written to the controller 114 .

The controller 114 in the eMMC 112 receives commands from the DMAC 105 to set the block length and the number of write data blocks. Then, the controller 114 executes processing corresponding to each command and issues the processing result to the DMAC 105 (S405). The format of this response is defined by the standard, and the controller 114 notifies the DMAC 105 of a response indicating whether or not the processing for the received command has been completed normally.

The DMAC 105 waits until receiving a notification from the controller 114 indicating that the processing corresponding to the command transmitted in S404 has been completed normally. The DMAC 105, having received the notification indicating that the processing corresponding to the command issued in S404 has been completed normally, issues a write command to the controller 114 based on the contents of the descriptor table 500 (S406). In S404, the DMAC 105 issues CMD24 (WRITE_BLOCK) and CMD25 (WRITE_MULTILE_BLOCK) based on the descriptor table 500. FIG. Here, a case has been described in which a response is issued in S405 indicating that the process has been completed normally in response to the command issued in S404. After S404, if the controller 114 issues a response indicating that the process corresponding to the command issued in S404 has not been completed normally, the process described in S404 is executed again.

The controller 114 executes processing corresponding to the command issued by the DMAC 105 in S406. After executing the processing, the controller 114 notifies the DMAC 105 of information indicating whether or not the processing was completed normally as a response (S407). The format of this response is a standard format. The DMAC 105 is notified of the status of the controller 114 in response to the received command in S407.

The DMAC 105 waits without proceeding with the process until it receives a response corresponding to the command issued in S406 from the controller 114 . The DMAC 105 receives from the controller 114 a response indicating that the processing corresponding to the command issued in S406 has been completed normally, and transfers the data to be written to the eMMC 112 to the controller 114 (S408).

In S408, the DMAC 105 reads data from the RAM 106 based on the contents of the descriptor table 500, and transfers the data to the eMMC 112 (S408). In S<b>408 , the DMAC 105 accesses data on the RAM 106 based on the Host Address 505 in the descriptor table 500 . The DMAC 105 then transfers the data read from the RAM 106 to the controller 114 . In this embodiment, a case has been described where the processing corresponding to the command issued in S406 is normally completed and the DMAC 105 receives a response indicating that the processing has been completed normally. In S407, if a response is issued indicating that the process corresponding to the command issued in S406 was not completed normally, the DMAC 105 may return to S406 without performing the process described in S408.

The controller 114 acquires data to be written to the NAND flash memory 116 of the eMMC 112 from the DMAC 105 and writes the data to the NAND flash memory 116 . When the writing to the NAND flash memory 116 is normally completed, the controller 114 issues a response indicating that the writing is normally completed to the DMAC 105 (S409). The format of this response is defined by standards, and the DMAC 105 is notified of the status of the received data. The status notified to the SMAC 105 in S409 includes the result of error detection for the data transferred in S408.

The DMAC 105 receives the response from the controller 114 and issues an interrupt to the CPU 102 (S410). In S409, the SMAC 105 determines whether or not the writing of the data whose transfer was started in S408 was completed normally, based on the error detection result output from the controller 114 . When data writing to the NAND flash memory is normally completed, the DMAC 105 outputs an interrupt signal to the CPU 102 indicating that the data transfer has been completed normally. On the other hand, if the writing of data to the NAND flash memory has not been completed normally, the DMAC 105 outputs an interrupt signal to the CPU 102 indicating that the data transfer has not been completed normally.

CPU 102 receives an interrupt signal from DMAC 105 . Then, it is determined whether or not the interrupt signal received from the DMAC 105 is an interrupt signal indicating that the data transfer has been normally completed (S411). If it is determined in S411 that the interrupt signal received by the CPU 102 is an interrupt indicating that the data transfer to the eMMC 112 has been completed normally, the CPU 102 executes the processing described in S412. On the other hand, if the interrupt signal received in S411 is determined to be an abnormal interrupt signal indicating that the data transfer has not been completed normally, the CPU 102 executes processing described later in S413.

In S412, the CPU 102 executes processing for estimating the data size of the data actually written to the NAND flash memory 116 by the controller 114 and calculating the sum of the data sizes written to the NAND flash memory 116 so far. Details of S412 will be described later.

Executed when the CPU 102 receives an abnormal interrupt in S410, it performs a recovery operation such as retransfer, or displays an abnormal state on the UI 108 (S413). Since S413 is not directly related to the present invention, its details are omitted. Note that when writing data to the NAND flash memory 116 fails, the process of obtaining the actual write data size is not performed.

FIG. 6 is a flowchart of the actual write data size addition process executed by the CPU 102 in S412 of FIG. The actual write data size addition process is a process of calculating the data size actually written to the eMMC 112 and obtaining the total write data size to the eMMC 112 . A program for executing the processing shown in FIG. 6 is stored in the ROM 107, and the CPU 102 develops the program in the RAM 106 and executes it, thereby realizing the processing.

The CPU 102 estimates the WAF based on the data size (Dsize1) for which writing is instructed based on the descriptor table 500 (S601). In S<b>601 , Dsiza1 is the product of Block Length 503 and Block Count 504 of descriptor table 500 . The CPU 102 selects the WAF corresponding to Dsize1 based on the WAF management table developed in the RAM 106 . For example, in S303, assuming that the WAF management tables No. 001 to No. 005 in FIG. 2 have been developed, if Dsize1 is 8 KBytes, WAF 2.0 is selected.

The CPU 102 multiplies Dsize1 by the WAF selected in S601 to calculate Dsize2, which is the data size that the eMMC 112 actually writes to the NAND flash memory 116 (S602). For example, if Dsize1 is 8 KBytes and WAF is 2.0, Dsize2 will be 16 KBytes.

The CPU 102 adds Dsize2 obtained in S602 to the cumulative write data size (Dtotal) (S603). For example, if Dsize2 obtained in S602 is 16 KBytes and Dtotal up to that point is 100 KBytes, Dtotal newly obtained in S603 will be 116 KBytes. Dtotal is written in the eMMC 112 and is written to the RAM 106 at startup. During operation of the image forming apparatus 100, the value of Dtotal stored in the RAM 106 is updated each time the eMMC 112 is written. Dtotal stored in RAM 106 is updated with the value stored in RAM 106 when the image forming apparatus 100 is powered off.

FIG. 7 is a processing flow for prompting replacement of the main controller to which the eMMC 112 is attached using the accumulated write data Dtotal when the accumulated write data size of the eMMC 112 approaches the upper limit. A program for executing the processing described in the flowchart of FIG. 7 is stored in the ROM 107, and the processing is realized by developing the program in the RAM 106 and executing it by the CPU 102. FIG. The flowchart shown in FIG. 7 is assumed to be performed during the system startup sequence after the power of the image forming apparatus 100 is turned on. However, after the power of the image forming apparatus 100 is turned on, the process illustrated in FIG. 7 may be executed periodically, for example, at a timing set by the user.

The CPU 102 reads Dtotal from the RAM 106 and determines whether or not Dtotal is equal to or less than a second reference value (Dth2) (S701). Dth2 is, for example, 90% of the data size described in the data sheet or the like as the write life of the eMMC 112 . For example, when the actual write data size that reaches the write life is 100 GBytes, Dth2 is 90 GBytes.

If Dtotal is less than or equal to Dth2, the CPU 102 advances the process to S703. On the other hand, if Dtotal is greater than or equal to Dth2, the CPU 102 advances the process to S702.

The CPU 102 notifies the user that the eMMC 112 needs to be replaced (S702). When the total write data size to the eMMC 112 is close to the upper limit of the write data of the eMMC 112, the eMMC 112 cannot guarantee data if more data is written. Therefore, when the data size estimated as the total write data size to the eMMC 112 exceeds Dth2, in S702, a notification is sent to prompt a serviceman to replace the controller board having the eMMC 112. FIG. In addition to the screen prompting to contact the serviceman, the external I/F 111 may be used to automatically transmit a parts replacement dispatch notification to the service center. In this way, the user is warned to use new memory when the data size estimated as the total write data size to the eMMC 112 is nearing the end of the write life. By doing so, it is suppressed that the total write data size to the eMMC 112 exceeds the total write data size, which is the write life, without realizing it, and the data written to the eMMC 112 cannot be guaranteed.

When the total write data size Dtotal to the eMMC 112 is less than or equal to Dth2, the CPU 102 determines whether or not Dtotal is less than or equal to the first reference value (Dth1) (S703). Dth1 in this embodiment is a value smaller than Dth2. For example, Dth1 is set to 70% of the write data size, which is the eMMC 112 write life.

If Dtotal is not equal to or less than Dth1, the CPU 102 executes the processing described in S704.

The CPU 102 displays a screen on the UI 108 to notify the user that the eMMC 112 is nearing the end of its writing life (S704). Here, the message displayed on the UI 108 is different from the message displayed in S702, and may be any message indicating that the time for replacement of the eMMC 112 is approaching. By providing Dth1 which is smaller than Dth2, the user can be notified that the eMMC 112 is approaching the end of its write life and the time to replace the memory is approaching. In this embodiment, two thresholds are used to notify the user in stages that the eMMC 112 is approaching the end of its write life. However, the user may be notified only when replacement is required without performing the processes of S703 and S704.

According to this embodiment, it is possible to select an appropriate WAF according to the data size to be written from the main SoC 101 to the eMMC 112, and to calculate the data size of the data actually written to the NAND flash memory. By accumulating the calculated data size and comparing it with the data size that becomes the write life of the eMMC 112, even if the memory cannot accurately know the actual write data size, it can be known that the life of the memory is near.

(Example 2)
In Example 1, the actual write data size addition processing S412 was performed after the write processing to the eMMC 112 was normally completed. In the second embodiment, before data writing to the eMMC 112 is completed, the actual write data size to be written to the NAND flash memory of the eMMC 112 is estimated, and the total write data size addition process is calculated. In the second embodiment, the actual write data size to the eMMC 112 is predicted and the total write data size is calculated before data writing to the eMMC 112 is completed. By doing so, it is possible to reduce the processing required after the write processing to the eMMC 112 is completed, and shorten the time required to complete the write.

1, FIG. 2, FIG. 3, FIG. 5, FIG. 6, and FIG. 7 are the same as those in the first embodiment, and therefore description thereof is omitted here.

FIG. 8 is a flow chart showing a write process 800 to eMMC in the second embodiment. The eMMC write processing 800 is processing for the main SoC 101 to write data to the eMMC 112, and is performed in cooperation with the CPU 102, DMAC 105, and controller 114. FIG. A program indicating the processing executed by the CPU 102 is stored in the ROM 107, and the processing shown in FIG. 8 is realized by developing the program in the RAM 106 and executing it. The same numbers are given to the same processes as in FIG. 4, and only the parts different from the first embodiment will be explained.

In S801, the CPU 102 calculates the actual write data size to the eMMC 112 based on the contents of the descriptor table 500 generated in S401, and calculates the total write size. In S801, the CPU 102 executes processing similar to the actual write data size addition processing shown in FIG.

In S411, if the interrupt signal received by the CPU 102 from the DMAC 105 is not an interrupt signal indicating that data writing has been completed normally, the CPU 102 executes processing for subtracting the actual write data size calculated in S801 (S802). Details of the processing executed by the CPU 102 in S802 will be described later with reference to FIG.

In the second embodiment, as described above, the actual write data size to the eMMC 112 is estimated in S801 to predict the total write data size, regardless of whether or not the data was normally written to the eMMC 112 . By doing so, the data write process can be completed without performing the process of estimating the actual write data size after the data is written to the eMMC 112 .

FIG. 9 is a flowchart of actual write data size subtraction processing 900 executed by the CPU 102 in S802 of FIG. The program described in the flowchart shown in FIG. 9 is stored in the ROM 107, and the processing is realized by the CPU 102 executing the program developed in the RAM 106. FIG.

Based on the descriptor table 500, the CPU 102 calculates the data size that the CPU 102 instructed the eMMC 112 to write (S901). The CPU 102 reads out the Block Length 503 and the Block Count 504 from the descriptor table 500 and multiplies them to calculate the data size that the CPU 102 has instructed to write to the eMMC 112 .

Next, the CPU 102 selects the data size calculated in S901 and the WAF corresponding to the data size calculated in S901 from the WAF management table developed in the RAM 106 (S902).

The CPU 102 estimates the data size calculated in S901 and the data size scheduled to be actually written to the eMMC 112 from the WAF selected in S902 (S903). In S903, the CPU 102 multiplies the data size calculated in S901 by the WAF selected in S902.

Finally, the CPU 102 subtracts the estimated write data size obtained in S903 from the total write data size stored in the RAM 106 (S904).

By performing the above processing, when writing to the eMMC 112 is not completed normally, the total write data size of the eMMC 112 can be corrected according to the actual writing situation.

In FIG. 9, the descriptor table 500 is used to recalculate the data size added to the actual write data size in S801. In S801, the data size added by the CPU 102 may be stored in the RAM 106, and in S813, the CPU 102 may acquire the data size added in S801 from the RAM 106 and subtract it from the total write data size.

Also in the second embodiment, the process shown in FIG. 7 is executed at an arbitrary timing after the process shown in FIG. 8 is completed. By executing the processing shown in FIG. 7, even the eMMC 112 that cannot know the actual write data size can predict the total write data size and notify that the write data size to the eMMC 112 is approaching the upper limit.

According to the second embodiment, it is possible to select an appropriate WAF according to the data size when writing from the main SoC 101 to the eMMC 112 and calculate the actual write data size. Also, the CPU 102 can calculate the actual write data size without waiting for the completion of the DMA transfer. Therefore, the CPU 102 does not need to estimate the actual write data size after completing the data write to the eMMC 112 and add it to the total write data size, and the time required after data write to the eMMC 112 is shortened.

(Example 3)
In the first and second embodiments, the actual write data size addition process is performed each time the write process is performed. However, in the third embodiment, the actual write data size addition process is performed at a timing different from that of the write process. Specific timings will be described in the examples.

2, 3, 5, and 7 are the same as those of the first embodiment, and therefore description thereof is omitted here.

FIG. 10 shows the configuration of an image forming apparatus 1000 according to the third embodiment. Components similar to those in FIG. 1 are denoted by similar reference numerals, and descriptions thereof are omitted.

The timer 117 is a module that transmits an interrupt signal to the CPU 102 when the count value reaches a threshold. The count cycle and threshold can be arbitrarily set by the CPU 102 .

The main switch 118 is operated by the user, and is used by the user to arbitrarily turn on or off the image system apparatus 100 . The CPU 102 is connected to the main switch 118 and can receive an interrupt signal indicating that the main switch 118 is turned on or off.

FIG. 11 is a flowchart of eMMC write processing in the third embodiment. The eMMC write process is a process for the main SoC 101 to write data to the eMMC 112, and is performed in cooperation with the CPU 102, DMAC 105, and controller 114. FIG. Configurations similar to those in FIG. 3 are denoted by similar reference numerals, and descriptions thereof are omitted. 11 differs from FIG. 3 in the processing after S411.

At step S411, the CPU 102 receives an interrupt signal from the DMAC 105. FIG. Then, it is determined whether or not the interrupt signal received from the DMAC 105 is an interrupt signal indicating that the data transfer has been completed normally. If it is determined in S411 that the interrupt signal received by the CPU 102 is an interrupt indicating that the data transfer to the eMMC 112 has been completed normally, the CPU 102 executes the processing described in S1112. On the other hand, if the interrupt signal received in S411 is determined to be an abnormal interrupt signal indicating that the data transfer has not been completed normally, the CPU 102 executes processing described later in S413.

In S1112, the CPU 102 executes count-up processing based on the write data size (that is, host write data size) transferred from the DMAC 105 to the controller 114 in the DMA transfer of S403 to S410. Assuming that the WAF differs for each host write data size, a counter is prepared for each data size and counted up. Details of step S1112 will be described with reference to FIG.

S<b>413 is executed when the CPU 102 receives an abnormal interrupt in S<b>410 , executes recovery operations such as retransfer, or displays an abnormal state on the UI 108 . Since S413 is not directly related to the present invention, its details are omitted.

In S1114, the CPU 102 determines whether or not the value of the counter used in the processing of S1112 exceeds a predetermined threshold. If the threshold is exceeded, S1115 is executed. The threshold here is a value determined with sufficient margin so that the counter does not overflow under any circumstances. If the threshold is not exceeded, write processing 1100 ends.

In S1115, the CPU 102 calculates the cumulative write data size based on the counter value. Details of S1115 will be described with reference to FIG.

As described here, in the eMMC write process 400, write data size count-up processing in S1112 and comparison processing between the count value and the threshold value in S1114 are performed. Compared to the actual write data size addition processing 700 described with reference to FIG. 7, these processings are limited to simple count-up processing and bit operation (comparison) processing, so the CPU load is extremely light.

Next, step S1112 will be described in detail using FIG. FIG. 12 is a flow chart of write data size count-up processing 1200 in the third embodiment. The write data size count-up process 1200 is a process executed by the CPU 102 in S1112 of the eMMC write process 400, and is a process that counts up based on the host write data size (Dsize1).

In S1201, the CPU 102 determines the counter to be incremented based on the host write data size (Dsize1). The host write data size (Dsize1) can be determined from the contents of the descriptor table 500 described with reference to FIG.

S1202 is executed when it is determined in S1201 that the host write data size (Dsize1) is 4 kB. In S1202, the CPU 102 increments 4kB_Counter (counter for 4kBytes).

S1203 is executed when it is determined in S1201 that the host write data size (Dsize1) is 8 kB. In S1203, the CPU 102 increments 8kB_Counter (counter for 8kBytes).

S1204 is executed when it is determined in S1201 that the host write data size (Dsize1) is 16 kB. In S1204, the CPU 102 increments 16 kB_Counter (counter for 16 kBytes).

S1205 is executed when it is determined in S1201 that the host write data size (Dsize1) is 32 kB. In S1205, the CPU 102 increments 32 kB_Counter (counter for 32 kBytes).

S1206 is executed when it is determined in S1201 that the host write data size (Dsize1) is 64 kB. In S1206, the CPU 102 increments 64 kB_Counter (counter for 64 kBytes).

After completing S1202 to S1206, the count-up process ends.

In this embodiment, an example of preparing counters for 4 kBytes to 64 kBytes has been described, but counters for data sizes other than these may be prepared and counted according to the system configuration.

Next, S1115 will be described in detail using FIG. FIG. 13 is a flow chart of actual write data size addition processing 1300 in the third embodiment. The actual write data size addition process 1300 is a process executed by the CPU 102 in S415 of the eMMC write process 400, and is a process of calculating the cumulative write data size (Dtotal).

The execution timing of the actual write data size addition processing 1300 may be timing other than S1115, such as when the system is shut down, when transitioning to sleep (power saving state), or at regular intervals (when a timer interrupt occurs). Details will be described with reference to FIG.

In S1301, the CPU 102 multiplies the "counter value", the "WAF", and the "data size" for each data size to calculate the actual write data size for each data size. For example, consider a case where the value corresponding to the 4 kB WAF of the eMMC is 8.0 in FIG. 2 and the value of 4 kB_Counter is 500. The actual write data size in this case is 16000 kBytes, which is 500 multiplied by 8 and 4. Such calculation is performed for each data size.

In S1302, the CPU 102 adds the calculation result for each data size performed in S1301 to the cumulative write data size (Dtotal). For example, if the calculation result in S1301 is 72,000 kBytes and Dtotal up to that point is 100,000 kBytes, Dtotal newly obtained in S1302 is 172,000 kBytes.

In S1303, the CPU 102 resets all the counters for each data size (initializes the count result to 0). After completing S1303, the actual write data size addition processing 1300 ends.

Next, with reference to FIG. 14, the execution timing when the actual write data size process is executed at timings different from those of S1114 and S1115 in FIG. 11 will be described. Here, three timings will be described as examples. Note that in FIG. 11, after executing S1114 and S115, the actual write data size processing may be executed at each timing in FIG. Alternatively, in FIG. 11, the actual write data size process may be executed at each timing in FIG. 14 without executing S1114 and S1115.

14A to 14C are flowcharts (A) to (C) showing execution timings of the actual write data size addition processing 1300 in this embodiment.

FIG. 14A is a flow chart for executing actual write data size addition processing 1400 in timer interrupt processing. A timer is provided in a general microcomputer or SOC, and is a module that issues an interrupt to the CPU when a set time elapses (count value expires). In this embodiment, the timer 117 included in the SoC 101 is used.

In S<b>1401 , the CPU 102 waits for an interrupt signal from the timer 117 . When the CPU 102 detects an interrupt signal from the timer 117, the CPU 102 executes S1402. Since S1402 is the actual write data size addition processing 1300 described with reference to FIG. 7, description thereof is omitted here. After completing S1402, the time interrupt processing ends.

(B) of FIG. 14 is a flowchart for performing the actual write data size addition process 1300 in the power state transition process.

In S1411, the CPU 102 determines whether the system as a whole satisfies the power state transition condition. When transitioning from a normal state (also called a standby state or idle state) to a power saving state (sleep state or hibernate state) that consumes less power than the normal state, it is necessary to satisfy transition conditions. For example, if the power saving state is entered while a print job or scan job is in progress, the job will be interrupted. Therefore, the CPU 102 determines that the power saving state is not entered during these jobs (that is, the power state transition condition is not satisfied). Details of the power state transition conditions are not directly related to the present embodiment, so a detailed description thereof will be omitted.

When the CPU 102 determines that the system as a whole satisfies the power state transition condition, S1412 is executed. Since S1412 is the actual write data size addition processing 1300 described with reference to FIG. 13, description thereof is omitted here.

In S1413, the CPU 102 shifts the system to the power saving state. Specifically, for example, control is performed to turn off the power of the printer 109 and the scanner 110 . After completing S1413, the power state transition processing ends.

(C) of FIG. 14 is a flowchart for executing the actual write data size addition process 1300 in the shutdown process.

At S<b>1421 , the CPU 102 waits for an off interrupt signal from the main switch 118 . When the CPU 102 detects the OFF interrupt signal from the main switch 118, the CPU 102 executes S1422.

Since S1422 is the actual write data size addition processing 1300 described with reference to FIG. 7, description thereof is omitted here.

In S1423, the CPU 102 shifts the system to the shutdown state. Specifically, for example, a process of writing necessary system data expanded in the RAM 106 to the ROM 107 is performed. After completing S1423, the shutdown process ends.

According to this embodiment, it is possible to select an appropriate WAF according to the data size to be written from the main SoC 101 to the eMMC 112 and to calculate the actual write data size. As a result, the host system can estimate the actual write data size more accurately than before.

Furthermore, according to this embodiment, only the count-up process of the write size is performed at the timing of occurrence of the write process to the eMMC, and the calculation of the actual write data is performed at a different timing using the count value. As a result, it is possible to reduce the local concentration of the CPU load.

(Example 4)
In the fourth embodiment, in the eMMC write process 1100, the write data size count-up process S1112 is performed after receiving the DMA transfer completion interrupt (S410). In the second embodiment, a flow for performing write data size count-up processing prior to receiving a DMA transfer completion interrupt is shown.

2, 3, 5, and 7 in Example 1 and FIGS. 10, 12, 13, and 14 in Example 3 are the same as in Example 4, so description thereof will be omitted here.

FIG. 15 is a flowchart of eMMC write processing 1000 in the fourth embodiment. The eMMC write processing 1000 is processing for the main SoC 101 to write data to the eMMC 112, and is performed in cooperation with the CPU 102, DMAC 105, and controller 114. FIG. Components similar to those in FIG. 11 are denoted by similar reference numerals, and descriptions thereof are omitted. 15 differs from FIG. 11 in the processing of S1511 and S1513.

In S<b>403 , the CPU 102 turns on the enable register of the DMAC 105 to start DMA transfer by the DMAC 105 . After completing S403, the process proceeds to S1511.

In S1511, the CPU 102 executes count-up processing based on the contents of the descriptor table 500 generated in S401. S1511 corresponds to S1112 in FIG. 11 and is the same as write data size count-up processing 1200 described in FIG.

In S412, the CPU 102 determines the type of interrupt received in S1010. If it is determined that it was an abnormal interrupt, S1513 is executed. If it is not an abnormal interrupt, the process proceeds to S1114.

In S1513, the CPU 102 performs a process of counting down the data size previously counted up in S1511. Details of S1513 will be described later with reference to FIG.

In S414, a recovery operation such as retransfer is executed, or an abnormal state is displayed on the UI 108. FIG. Since S413 is not directly related to the present invention, its details are omitted. The subsequent steps are the same as in FIG. 11, so the description is omitted.

Also in the present embodiment, the execution timing of the actual write data size addition process 1300 may be different as described in FIG. 14 of the third embodiment. Specifically, other than S1115, it may be performed at timing such as when the system is shut down, when transitioning to sleep (power saving state), or at regular intervals (when a timer interrupt occurs).

FIG. 16 is a flowchart of write data size countdown processing 1600 in the fourth embodiment. The write data size countdown process 1600 is a process executed by the CPU 102 in S1513 of the eMMC write process 1500. FIG.

In S1601, the CPU 102 determines the counter to be decremented based on the host write data size (Dsize1). The host write data size (Dsize1) can be determined from the contents of the descriptor table 500 described with reference to FIG.

S1602 is executed when it is determined in S1601 that the host write data size (Dsize1) is 4 kB. In S1602, the CPU 102 decrements 4 kB_Counter (counter for 4 kBytes).

S1603 is executed when it is determined in S1601 that the host write data size (Dsize1) is 8 kB. In S1603, the CPU 102 decrements 8 kB_Counter (counter for 8 kBytes).

S1604 is executed when it is determined in S1601 that the host write data size (Dsize1) is 16 kB. In S1104, the CPU 102 decrements 16 kB_Counter (counter for 16 kBytes).

S1605 is executed when it is determined in S1101 that the host write data size (Dsize1) is 32 kB. In S1605, the CPU 102 decrements 32 kB_Counter (counter for 32 kBytes).

S1606 is executed when it is determined in S1601 that the host write data size (Dsize1) is 64 kB. In S1106, the CPU 102 decrements 64 kB_Counter (counter for 64 kBytes).

In this embodiment, an example of preparing counters for 4 kBytes to 64 kBytes has been described, but counters for data sizes other than these may be prepared and counted according to the system configuration.

According to this embodiment, it is possible to select an appropriate WAF according to the data size to be written from the main SoC 101 to the eMMC 112 and to calculate the actual write data size. Also, the CPU 102 can calculate the actual write data size without waiting for the completion of the DMA transfer. As a result, it becomes possible for the host system to estimate the actual write data size more accurately than before, and the processing time overhead due to the calculation of the actual write data size by the CPU 102 can be reduced.

Furthermore, according to this embodiment, only the write size count-up process or count-down process is performed at the timing of writing to the eMMC, and the calculation of the actual write data is performed at a different timing using the count value. As a result, it is possible to reduce the local concentration of the CPU load.

(Other embodiments)
The present invention is also realized by executing the following processing. That is, the software (program) that realizes the functions of the above-described embodiments is supplied to a system or device via a network or various storage media, and the computer (or CPU, MPU, etc.) of the system or device reads and executes the program code. In this case, the computer program and the storage medium storing the computer program constitute the present invention.

Claims (14)

An information processing device having a nonvolatile semiconductor storage device for storing data and a memory for storing a WAF for each data size,
an instruction means for instructing the semiconductor memory device to write data;
counting means for counting, for each data size, the number of write instructions of the data size of the data instructed to be written;
calculating means for calculating a write size corresponding to the data size of the data instructed to be written;
accumulating means for accumulating the calculated write size;
notification means for notifying when the accumulated write size satisfies a predetermined condition with respect to a threshold;
The calculation means is
An information processing apparatus, wherein the write size is calculated based on the WAF corresponding to the data size of the write-instructed data, the data size of the write-instructed data, and the write instruction count. The calculation means calculates the write size for each data size based on the WAF corresponding to the data size of the data instructed to write and the data size of the data instructed to write, and the number of write instructions,
2. The information processing apparatus according to claim 1, wherein said accumulating means accumulates the write sizes of the plurality of data sizes calculated by said calculating means. 3. The information processing apparatus according to claim 1 , wherein the predetermined condition is that the accumulated write size is larger than the threshold value. a measuring means for counting a timer;
signal output means for outputting an interrupt signal when the count time of the timer by the measurement means exceeds different thresholds;
4. The information processing apparatus according to any one of claims 1 to 3 , wherein the calculating means calculates the write size based on the WAF corresponding to the data size of the data instructed to write and the data size of the data instructed to write, and the number of write instructions, in accordance with the reception of the interrupt signal. 5. The information processing apparatus according to any one of claims 1 to 4 , wherein the calculating means calculates the write size after satisfying a power state transition condition of the information processing apparatus from the first power state to the second power state with lower power consumption than the first power state and before transitioning from the first power state to the second power state. 6. The information processing apparatus according to any one of claims 1 to 5 , wherein the calculation unit calculates the write size based on the operation IF receiving a shutdown processing instruction for turning off the power of the information processing apparatus. 7. The information processing apparatus according to any one of claims 1 to 6 , wherein said calculation means calculates said write size at regular time intervals. 8. The information processing apparatus according to claim 1, wherein said notification indicates that the semiconductor memory device needs to be replaced. the notification means is a display unit;
9. The information processing apparatus according to any one of claims 1 to 8 , wherein the display unit displays a message prompting replacement of the semiconductor memory device as the notification on the display unit. 10. The information processing apparatus according to claim 1, wherein said semiconductor memory device is a non-volatile NAND flash memory. having image processing means for processing image data;
11. The information processing apparatus according to claim 1, wherein said semiconductor memory device stores said image data processed by said image processing means. 12. An information processing apparatus according to claim 11 , further comprising a printer configured to form an image on a sheet based on the image data generated by said image processing means. The information processing apparatus according to any one of claims 1 to 12 , wherein the WAF is one or more. 14. The information processing apparatus according to claim 1, wherein said WAF stored in said memory is said WAF for each said data size set corresponding to a product name of said semiconductor memory device.

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