JP6119117B2 - Electronics - Google Patents

Description

  The present invention relates to an image sensor.

There is known an imaging unit in which a back-illuminated imaging chip and a signal processing chip are connected via a micro bump for each cell unit in which a plurality of pixels are combined.
[Prior art documents]
[Patent Literature]
[Patent Document 1] Japanese Patent Application Laid-Open No. 2006-49361

  In the imaging unit, one output line is input to one CDS / A / D circuit by one bump for one cell. However, if any of the output lines, bumps, and CDS • A / D circuit is abnormal, the pixel signal from the entire cell cannot be obtained, or even if there is no abnormality, the cell and the CDS • A / D circuit are not obtained. There was a problem that the combination with the / D circuit was fixed and the degree of freedom of processing was low.

  In the first aspect of the present invention, a unit group including a plurality of pixels for converting incident light into a pixel signal and a unit group provided corresponding to the unit group are read from each of the plurality of pixels of the unit group. An imaging unit having a plurality of sets of output lines from which the pixel signals are output, a plurality of A / D converters that digitize and output the input pixel signals, and a plurality of the output lines are connected to the plurality of output lines. An imaging device is provided that includes a switching unit that switches which of the A / D conversion units inputs.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 is a cross-sectional view of a backside illuminating type MOS imaging device according to the present embodiment. It is a figure explaining the pixel arrangement | sequence and unit group of an imaging chip. It is a circuit diagram corresponding to the unit group of an imaging chip. It is a block diagram which shows the structure of the imaging device which concerns on this embodiment. A part of functional block of a drive part is shown. It is a block diagram which shows functional structures, such as a signal processing part. The unit group of another image sensor is shown typically. The circuit diagram of the pixel unit in a unit group is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a cross-sectional view of a back-illuminated image sensor 100 according to this embodiment. The imaging device 100 includes an imaging chip 113 that outputs a pixel signal corresponding to incident light, a signal processing chip 111 that processes the pixel signal, and a memory chip 112 that stores the pixel signal. The imaging chip 113, the signal processing chip 111, and the memory chip 112 are stacked, and are electrically connected to each other by a conductive bump 109 such as Cu.

  As shown in the figure, incident light is incident mainly in the positive direction of the Z-axis indicated by a white arrow. In the present embodiment, in the imaging chip 113, the surface on the side where incident light is incident is referred to as a back surface. Further, as shown in the coordinate axes, the left direction of the paper orthogonal to the Z axis is the X axis plus direction, and the front side of the paper orthogonal to the Z axis and the X axis is the Y axis plus direction. In the following several figures, the coordinate axes are displayed so that the orientation of each figure can be understood with reference to the coordinate axes of FIG.

  An example of the imaging chip 113 is a back-illuminated MOS image sensor. The PD layer 106 is disposed on the back side of the wiring layer 108. The PD layer 106 includes a plurality of PDs (photodiodes) 104 that are two-dimensionally arranged and store charges corresponding to incident light, and transistors 105 that are provided corresponding to the PDs 104.

  A color filter 102 is provided on the incident side of incident light in the PD layer 106 via a passivation film 103. The color filter 102 has a plurality of types that transmit different wavelength regions, and has a specific arrangement corresponding to each of the PDs 104. The arrangement of the color filter 102 will be described later. A set of the color filter 102, the PD 104, and the transistor 105 forms one pixel.

  On the incident light incident side of the color filter 102, a microlens 101 is provided corresponding to each pixel. The microlens 101 condenses incident light toward the corresponding PD 104.

  The wiring layer 108 includes a wiring 107 that transmits the pixel signal from the PD layer 106 to the signal processing chip 111. The wiring 107 may be multilayer, and a passive element and an active element may be provided.

  A plurality of bumps 109 are disposed on the surface of the wiring layer 108. The plurality of bumps 109 are aligned with the plurality of bumps 109 provided on the opposing surfaces of the signal processing chip 111, and the imaging chip 113 and the signal processing chip 111 are pressed and aligned. The bumps 109 are joined and electrically connected.

  Similarly, a plurality of bumps 109 are disposed on the mutually facing surfaces of the signal processing chip 111 and the memory chip 112. The bumps 109 are aligned with each other, and the signal processing chip 111 and the memory chip 112 are pressurized, so that the aligned bumps 109 are joined and electrically connected.

  The bonding between the bumps 109 is not limited to Cu bump bonding by solid phase diffusion, and micro bump bonding by solder melting may be employed. Further, for example, one or several bumps 109 may be provided for one unit group described later. Therefore, the size of the bump 109 may be larger than the pitch of the PD 104. Further, a bump larger than the bump 109 corresponding to the pixel region may be provided in a peripheral region other than the pixel region where the pixels are arranged.

  The signal processing chip 111 has a TSV (silicon through electrode) 110 that connects circuits provided on the front and back surfaces to each other. The TSV 110 is preferably provided in the peripheral area. The TSV 110 may also be provided in the peripheral area of the imaging chip 113 and the memory chip 112.

  FIG. 2 is a diagram for explaining the pixel array and the unit group 131 of the imaging chip 113. In particular, a state where the imaging chip 113 is observed from the back side is shown. In the pixel area, 20 million or more pixels are arranged in a matrix. In this embodiment, 16 pixels of 4 pixels × 4 pixels adjacent to each other form one unit group 131. The grid lines in the figure indicate the concept that adjacent pixels are grouped to form a unit group 131. The number of pixels forming the unit group 131 is not limited to this, and may be about 1000, for example, 32 pixels × 64 pixels, or more or less.

  As shown in the partially enlarged view of the pixel region, the unit group 131 includes four so-called Bayer arrays composed of four pixels, ie, green pixels Gb, Gr, blue pixels B, and red pixels R, vertically and horizontally. The green pixel is a pixel having a green filter as the color filter 102, and receives light in the green wavelength band of incident light. Similarly, a blue pixel is a pixel having a blue filter as the color filter 102 and receives light in the blue wavelength band, and a red pixel is a pixel having a red filter as the color filter 102 and receiving light in the red wavelength band. Receive light.

  FIG. 3 is a circuit diagram corresponding to the unit group 131 of the imaging chip 113. In the figure, a rectangle surrounded by a dotted line typically represents a circuit corresponding to one pixel. Note that at least some of the transistors described below correspond to the transistor 105 in FIG.

  As described above, the unit group 131 is formed of 16 pixels. The 16 PDs 104 corresponding to the respective pixels are respectively connected to the transfer transistors 302, and the gates of the transfer transistors 302 are connected to the TX wiring 307 to which transfer pulses are supplied. In the present embodiment, the TX wiring 307 is commonly connected to the 16 transfer transistors 302.

  The drain of each transfer transistor 302 is connected to the source of the corresponding reset transistor 303, and a so-called floating diffusion FD between the drain of the transfer transistor 302 and the source of the reset transistor 303 is connected to the gate of the amplification transistor 304. The drain of the reset transistor 303 is connected to a Vdd wiring 310 to which a power supply voltage is supplied, and the gate thereof is connected to a reset wiring 306 to which a reset pulse is supplied. In the present embodiment, the reset wiring 306 is commonly connected to the 16 reset transistors 303.

  The drain of each amplification transistor 304 is connected to a Vdd wiring 310 to which a power supply voltage is supplied. The source of each amplification transistor 304 is connected to the drain of each corresponding selection transistor 305. Each gate of the selection transistor is connected to a decoder wiring 308 to which a selection pulse is supplied. In the present embodiment, the decoder wiring 308 is provided independently for each of the 16 selection transistors 305. The source of each selection transistor 305 is connected to a common output wiring 309. The load current source 311 supplies current to the output wiring 309. That is, the output wiring 309 for the selection transistor 305 is formed by a source follower. Note that the load current source 311 may be provided on the imaging chip 113 side or on the signal processing chip 111 side.

  Here, the flow from the start of charge accumulation to pixel output after the end of accumulation will be described. When a reset pulse is applied to the reset transistor 303 through the reset wiring 306 and simultaneously a transfer pulse is applied to the transfer transistor 302 through the TX wiring 307, the potentials of the PD 104 and the floating diffusion FD are reset.

  When the application of the transfer pulse is canceled, the PD 104 converts the incident light to be received into charges and accumulates them. Thereafter, when the transfer pulse is applied again without the reset pulse being applied, the accumulated charge is transferred to the floating diffusion FD, and the potential of the floating diffusion FD changes from the reset potential to the signal potential after the charge accumulation. . When a selection pulse is applied to the selection transistor 305 through the decoder wiring 308, a change in the signal potential of the floating diffusion FD is transmitted to the output wiring 309 through the amplification transistor 304 and the selection transistor 305. Thereby, a pixel signal corresponding to the reset potential and the signal potential is output from the unit pixel to the output wiring 309.

  As shown in the figure, in this embodiment, the reset wiring 306 and the TX wiring 307 are common to the 16 pixels forming the unit group 131. That is, the reset pulse and the transfer pulse are simultaneously applied to all 16 pixels. Therefore, all the pixels forming the unit group 131 start charge accumulation at the same timing and end charge accumulation at the same timing. However, the pixel signal corresponding to the accumulated electric charge is sequentially applied to each selection transistor 305 by a selection pulse, and is selectively output to the output wiring 309. In addition, the reset wiring 306, the TX wiring 307, and the output wiring 309 are provided separately for each unit group 131.

  By configuring the circuit with the unit group 131 as a reference in this way, the charge accumulation time can be controlled for each unit group 131. In other words, it is possible to output pixel signals with different charge accumulation times between adjacent unit groups 131. More specifically, while one unit group 131 performs charge accumulation once, the other unit group 131 repeats charge accumulation several times and outputs a pixel signal each time, so that Each frame for a moving image can be output at a different frame rate between unit groups 131.

  FIG. 4 is a block diagram illustrating a configuration of the imaging apparatus according to the present embodiment. The imaging apparatus 500 includes a photographic lens 520 as a photographic optical system, and the photographic lens 520 guides a subject luminous flux incident along the optical axis OA to the imaging element 100. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the imaging apparatus 500. The imaging apparatus 500 mainly includes an imaging device 100, a system control unit 501, a photometry unit 503, a work memory 504, a recording unit 505, and a display unit 506.

  The photographing lens 520 is composed of a plurality of optical lens groups, and forms an image of a subject light flux from the scene in the vicinity of its focal plane. In FIG. 4, the photographic lens 520 is representatively represented by a single virtual lens arranged in the vicinity of the pupil.

  The image sensor 100 includes a driving unit 502 and a signal processing unit 514 in addition to the imaging chip 113. The drive unit 502 is a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 100 in accordance with instructions from the system control unit 501. The signal processing unit 514 performs signal processing such as analogizing pixel signals from the plurality of PDs 104 of the imaging chip 113.

  The signal processing unit 514 delivers the digitized pixel signal to the image processing unit 511 of the system control unit 501. The image processing unit 511 performs various image processing using the work memory 504 as a work space, and generates image data. For example, when generating image data in JPEG file format, a compression process is executed after generating a color video signal from a signal obtained by the Bayer array. The generated image data is recorded in the recording unit 505, converted into a display signal, and displayed on the display unit 506 for a preset time.

  The photometric unit 503 detects the luminance distribution of the scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor having about 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance for each area of the scene. The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. The light metering unit 503 may be shared by the image sensor 100. Note that the arithmetic unit 512 also executes various arithmetic operations for operating the imaging device 500.

  The drive unit 502 and the signal processing unit 514 may be partly or entirely mounted on the imaging chip 113, or part or all may be mounted on the signal processing chip 111. A part of the system control unit 501 may be mounted on the imaging chip 113 or the signal processing chip 111.

  FIG. 5 shows a part of functional blocks of the drive unit 502. The drive unit 502 includes a group control table 150, a pixel drive unit 156, an AD control unit 152, and an address assignment unit 154.

  The group control table 150 has information used to control each of the plurality of unit groups 131. The information is written from the system control unit 501 in accordance with shooting conditions and the like. Examples of the information include information for specifying the unit group 131, timing for applying a reset pulse and a transfer pulse to each pixel of the unit group 131, or a shift amount thereof with respect to a reference timing. Other information will be described later.

  The pixel driving unit 156 refers to the group control table 150 and drives each pixel of the unit group 131, particularly the transfer transistor 302 of each pixel, based on information associated with the unit group 131. Thereby, the pixel driving unit 156 refers to the group control table 150 and controls the reset pulse, the transfer pulse, and the selection pulse for each unit group 131 to execute the charge accumulation control. The pixel driving unit 156, the AD control unit 152, and the address assigning unit 154 will be described later.

  FIG. 4 is a block diagram illustrating a functional configuration of the signal processing unit and the like. The signal processing unit 514 includes switches 411 and 421 that are electrically connected to the output wiring 309 of the unit groups 131 and 132 via bumps, signal processing circuits 412 and 422 provided corresponding to the switches 411 and 421, and signals. Demultiplexers 413 and 423 provided corresponding to the processing circuits 412 and 422, and a pixel memory 414 are provided.

  In the example shown in FIG. 4, a set of a switch 411, a signal processing circuit 412 and a demultiplexer 413 and a set of a switch 421, a signal processing circuit 422 and a demultiplexer 423 are provided. Further, the output wiring 309 from one unit group 131 branches and is connected to the two switches 411 and 421 via the bumps 109 respectively. Similarly, the output wiring 309 from the other unit group 132 branches and is connected to the two switches 411 and 421 via the bump 109, respectively.

  The switch 411 is controlled by the AD control unit 152 and switches which output wiring 309 of the two unit groups 131 and 132 is input to the signal processing circuit 412. Similarly, the switch 421 is also controlled by the AD control unit 152 and switches which output wiring 309 of the two unit groups 131 and 132 is input to the signal processing circuit 412.

  The pixel signal input via the switch 411 is supplied to the signal processing chip 111 by a signal processing circuit 412 that performs correlated double sampling (CDS) / analog / digital (A / D) conversion. D conversion is performed. The A / D converted pixel signal is transferred to the demultiplexer 413 and stored in the pixel memory 414 corresponding to each pixel.

  Similarly, the pixel signal input via the switch 421 is subjected to CDS and A / D conversion by the signal processing circuit 422 formed in the signal processing chip 111. The A / D converted pixel signal is transferred to the demultiplexer 423 and stored in the pixel memory 414 corresponding to each pixel.

  The pixel memory 414 is shared by the two signal processing circuits 412 and 422. By indicating the address, the pixel values from PD1 to 16 of the unit group 131 are stored in the memories 1 to 16 of the corresponding pixel memory 414. Similarly, the pixel values from the PDs 17 to 32 of the unit group 132 are stored in the memories 17 to 32 of the corresponding pixel memory 414.

  In the example shown in FIG. 6 as described above, since the two unit groups 131 and 132 can be connected to the two signal processing circuits 412, 422, there are four combinations of connections. Which combination is selected is determined by the AD control unit 152 switching the switches 411 and 421 with reference to the group control table 150.

  Hereinafter, a specific example of selecting a combination of connections will be described. In the first example, a combination of connections is selected depending on the abnormality of the signal line including the bump 109, the abnormality of the signal processing circuit 412 and the like.

  In this case, the abnormal bump 109, the signal processing circuit 412 and the like are specified in a test at the time of factory shipment or when the system control unit 501 detects an abnormal value on the image in use. Information specifying the abnormal bump 109, the signal processing circuit 412 and the like is written in the group control table 150.

  When the information specifying the abnormal bump 109 and the signal processing circuit 412 is written in the group control table 150, the AD control unit 152 uses the pixel signal without using the abnormal bump 109 and the signal processing circuit 412. Select the combination of connections for which is output. For example, in the example illustrated in FIG. 6, when the fact that the signal processing circuit 412 is abnormal is written in the group control table 150, the AD control unit 152 detects abnormalities for the two unit groups 131 and 132. The switch 411 corresponding to the signal processing circuit 412 is cut off, and the switch 421 corresponding to the signal processing circuit 422 is brought into a connected state. In this case, the switch 421 may be connected to the two unit groups 131 and 132 in a time-sharing manner, or may be simultaneously connected.

  When only one signal processing circuit 422 is used for the two unit groups 131 and 132, the address assigning unit 154 assigns addresses to the output from the unit group 131 and the output from the unit group 132. Thereby, the demultiplexer 423 corresponding to the signal processing circuit 422 stores the pixel values from the PD1 to 16 of the unit group 131 in the memories 1 to 16 of the corresponding pixel memory 414 based on the address, and Pixel values from PDs 17 to 32 of group 132 are stored in memories 17 to 32 of corresponding pixel memory 414.

  The group control table 150 stores information for specifying the signal processing circuits 412 to be connected to the two unit groups 131 and 132 instead of the information for specifying the abnormal bumps 109, the signal processing circuits 412 and the like. May be. Alternatively, the group control table 150 may store information that specifies whether the switch 411 and the switch 411 should be connected in association with the information that specifies the respective switches 411 and 421.

  According to the first example, it is possible to obtain pixel signals from any unit group 131 and the like with redundancy for circuit abnormality. In this case, the two signal processing circuits 412, 422 preferably have the same function and performance. For example, the two signal processing circuits 412, 422 preferably have the same processing speed, the same number of bits for digitization, that is, the same resolution, and the like.

  In the second example, when the two signal processing circuits 412 and 422 have different functions or performances, a more appropriate connection combination is selected. For example, signal processing circuits 412 and 422 having different processing speeds are provided. In this case, there is a positive correlation that the higher the processing speed, the larger the heat generation amount and power consumption (hereinafter, collectively referred to as the heat generation amount). When the amount of generated heat is large, noise on the image signal tends to increase.

  In this case, the group control table 150 is written with information specifying which of the two signal processing circuits 412 and 422 has a high processing speed or a large amount of heat generation. When there is an imaging instruction from the system control unit 501, the AD control unit 152 refers to the group control table 150, and when the conversion speed is prioritized, the signal processing circuit 412 or the like having the higher processing speed As used, one of the switches 411 and 421 is connected and the other is disconnected. Further, the AD control unit 152 places one of the switches 411 and 421 in a connected state so that the signal processing circuit 412 having the smaller amount of generated heat is used when the amount of generated heat is a priority. Turn off. In this case, the switches 411 and 421 may be connected to the two unit groups 131 and 132 in a time-sharing manner, or may be simultaneously connected.

  For example, the system control unit 501 instructs whether or not the processing speed is a priority and whether or not the heat generation amount is a priority. Instead, the AD control unit 152 may make a determination according to a predetermined determination condition, for example, whether or not the temperature of the image sensor 100 exceeds a threshold value.

  The AD control unit 152 further connects the one of the signal processing circuits 412 and 422 with the higher processing speed to one of the unit groups 131 and 132 and connects the one with the lower processing speed to the other. The switches 411 and 421 may be controlled. In any case of the second example, the address assigning unit 154 associates PD1 to 16 of the unit group 131 with the memories 1 to 16 of the pixel memory 414, and associates PD17 to 32 of the unit group 132 with the pixel memory 414. Addresses are assigned so as to be associated with the memories 17 to 32.

  As described above, according to the second example, an appropriate signal processing circuit can be used depending on whether the processing speed has priority or the heat generation amount has priority. Further, when the above-mentioned priorities are different for the two unit groups 131 and 132, a signal processing circuit prioritizing the processing speed can be used on one side, and a signal processing circuit prioritizing the heat generation amount or the like can be used on the other side.

  In the third example, when the two signal processing circuits 412 and 422 have other functions or performances different from each other, a more appropriate connection combination is selected. For example, signal processing circuits 412 and 422 having different digitization bit numbers are provided. Examples of different digitization bit numbers are 12 bits and 16 bits, for example. In this case, the larger the number of bits, the more gradations can be obtained, but there is a positive correlation that the amount of signals handled thereafter increases. In addition, there may be a negative correlation that the processing speed becomes slower as the number of bits increases.

  In this case, in the group control table 150, information specifying which of the two signal processing circuits 412, 422 has more bits or which signal amount is larger is written. When there is an imaging instruction from the system control unit 501, the AD control unit 152 refers to the group control table 150 and uses the signal processing circuit 412 having the larger number of bits when the number of bits has priority. As shown, one of the switches 411 and 421 is connected and the other is disconnected. Further, when priority is given to the signal amount, the AD control unit 152 places one of the switches 411 and 421 in a connected state so that the signal processing circuit 412 having a smaller signal amount is used, and puts the other in a disconnected state.

  The AD control unit 152 further connects one of the unit groups 131 and 132 with the larger number of bits in the signal processing circuits 412 and 422 and connects the other with the smaller number of bits to the other. The switches 411 and 421 may be controlled. In the third example, the system control unit 501 may indicate that the connection state may be set in a time-division manner or at the same time, and which function or the like is given priority. The control unit 152 may determine the same as in the second example. The function of the address assigning unit 154 is the same as that in the second example.

  As described above, according to the third example, an appropriate signal processing circuit can be used depending on whether the number of bits has priority or the signal amount has priority. Furthermore, when the above-mentioned priorities are different for the two unit groups 131 and 132, a signal processing circuit with priority on the number of bits can be used on one side, and a signal processing circuit with priority on signal amount can be used on the other. Note that the priority may be a comparison between the processing speed and the number of bits instead of the comparison between the signal amount and the number of bits.

  FIG. 7 schematically shows a unit group 655 of another image sensor 654. FIG. 8 shows a circuit diagram of the pixel unit 656 in the unit group 655.

  In the unit group 655, pixels are two-dimensionally arranged in a Bayer arrangement as in FIG. One row selection line is provided for every two rows of pixels, and two rows of pixels are commonly connected to each row selection line. Further, one column selection line is provided for every two columns of pixels, and two columns of pixels are commonly connected to each column selection line.

  One unit in the Bayer array forms a pixel unit 656. That is, the pixel unit 656 has four pixels Gb, Gr, B, and R.

  The power supply wiring Vdd and the reset wiring are commonly connected to all the pixels included in the unit group 131. In addition, the Gb transfer wiring is commonly connected to the pixels Gb in the unit group 131. Similarly, the Gr transfer wiring is commonly connected to the pixel Gr in the unit group 131, the B transfer wiring is commonly connected to the pixel B in the unit group 131, and the R transfer wiring is common to the pixel R in the unit group 131. It is connected to the. Further, the reset wiring and each transfer wiring are separately provided between the plurality of unit groups 131.

  The pixels Gb, Gr, B, and R of the pixel unit 603 share the reset transistor 620, the amplification transistor 622, and the selection transistors 624 and 642. The pixel Gb1 includes transfer transistors 626 and 628. Similarly, the pixel Gr includes transfer transistors 630 and 632, the pixel B includes transfer transistors 634 and 636, and the pixel R includes transfer transistors 638 and 640.

  When attention is paid to each pixel, the connection relationship between the pixel, the reset transistor 620, and the amplification transistor 622 is the same as that in FIG. On the other hand, the connection relationship of the transfer transistor 626 and the like is different from that in FIG. The gate, drain, and source of the transfer transistor 626 of the pixel Gb are connected to the Gb transfer wiring, the row selection line 1, and the gate of the transfer transistor 628, respectively. The source and drain of the transfer transistor 628 are connected to one end of the PD of the pixel Gb and the gate of the amplification transistor 622, respectively. The connection relationship between the pixels Gr, B, and R is the same.

  The column selection line is connected to the drains of the transfer transistors 626, 630, 634, and 638 of the pixel unit 656. The output wiring 604 of the pixel unit 656 is provided with a selection transistor 642 whose column selection line and gate are connected.

  One output wiring 604 is provided for every two columns of pixels, but is electrically connected to each other. Further, the output wiring 604 branches into two and is connected to the bumps 606 and 608, respectively. One bump 606 is connected to the input side of one A / D conversion circuit 614 via a switch 610. The other bump 608 is connected to the input side of the other A / D conversion circuit 616 via the switch 612.

  7 and FIG. 8, the image signal of each pixel is read as follows. Note that the description of the reset operation is omitted for the sake of simplicity.

  One of the row selection lines, for example, the row selection line 1 is turned on. In this state, one of the transfer lines, for example, the Gb transfer wiring is turned on. In this state, one of the column selection lines, for example, the column selection line 1 is turned on. Thereby, both transfer transistors 626 and 628 of the pixel Gb of one pixel unit 656 in the unit group 655 are turned on, and the charge of the pixel Gb is transferred to the gate of the amplification transistor 622. Here, since the row selection line 1 is in the on state, the selection transistor 624 is also on, and the pixel signal amplified in accordance with the charge transferred to the gate of the amplification transistor 622 is output corresponding to the pixel unit 653. Output from the wiring 604.

  Furthermore, by keeping the row selection line 1 and the Gb transfer wiring in the on state and sequentially switching the column selection line in the on state, the pixel signals of the pixels Gb for one row are sequentially output from the respective output wirings 604. . Therefore, the pixel signal from the pixel Gb is input to the A / D conversion circuit 614 via the bump 606 one pixel at a time. In this case, since the selection transistor 642 is disposed in each pixel unit 656, the output from the pixel Gb of the pixel unit 656 not selected by the column selection line is blocked. Accordingly, each of the pixel signals of the pixels Gb for one row of the unit group 655 is read without being influenced by other pixel signals and stored in the pixel memory 414.

  Next, in a state where the row selection line 1 and the Gr transfer wiring are turned on, the pixel selection signals of the pixels Gr for one row are sequentially output from the respective output wirings 604 by sequentially switching the on state of the column selection line. The Similarly, by sequentially switching the ON state of the column selection line while the row selection line 1 and the B transfer wiring are turned on, pixel signals of pixels B for one row are sequentially output from the respective output wirings 604, and the row By sequentially switching the ON state of the column selection line in a state where the selection line 1 and the R transfer wiring are turned on, pixel signals of pixels R for one row are sequentially output from the respective output wirings 604.

  As described above, the pixel signals of the two rows of pixels of the unit group 655 are read out. Next, the row selection line 2 is turned on and the above procedure is repeated to read out pixel signals of pixels for the next two rows of the unit group 655. By repeating the above procedure for all row selection lines, the pixel signals of all the pixels in the unit group 655 are read out.

  Further, the pixel unit is composed of four pixels, the row selection wiring is arranged for every two rows of pixels, and the output wiring is arranged for every two columns of pixels, but this is not restrictive. For example, when the pixel unit is composed of m rows and n columns, a unit group is provided with one row selection wiring for each m rows and one output wiring for each n columns, and m × n A separate transfer wiring may be provided. Each transfer wiring may be common in the pixel group.

  The present embodiment can be applied by replacing the unit group 655 shown in FIGS. 7 and 8 with the unit groups 131 and 132 shown in FIGS. The combination of the unit group and the signal processing circuit is not limited to 2 to 2 shown in FIG. 6 and 1 to 2 shown in FIG. 7, and the number is not limited as long as it is one to many or many to many.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  100 imaging device, 101 microlens, 102 color filter, 103 passivation film, 104 PD, 105 transistor, 106 PD layer, 107 wiring, 108 wiring layer, 109 bump, 110 TSV, 111 signal processing chip, 112 memory chip, 113 imaging Chip, 131 unit group, 132 unit group, 150 group control table, 152 AD control unit, 154 address assigning unit, 156 pixel driving unit, 302 transfer transistor, 303 reset transistor, 304 amplification transistor, 305 selection transistor, 306 reset wiring, 307 TX wiring, 308 decoder wiring, 309 output wiring, 310 Vdd wiring, 311 load current source, 411 switch, 412 signal processing circuit, 413 Multiplexer, 414 pixel memory, 421 switch, 422 signal processing circuit, 423 demultiplexer, 500 imaging device, 501 system control unit, 502 drive unit, 503 photometry unit, 504 work memory, 505 recording unit, 506 display unit, 511 image processing , 512 operation unit, 514 signal processing unit, 520 photographing lens, 604 output wiring, 606 bump, 608 bump, 610 switch, 612 switch, 614 A / D conversion circuit, 616 A / D conversion circuit, 620 reset transistor, 622 Amplification transistor, 624 selection transistor, 626 transfer transistor, 628 transfer transistor, 630 transfer transistor, 632 transfer transistor, 634 transfer transistor, 636 transfer transistor, 638 Transfer transistor, 640 Transfer transistor, 642 Select transistor, 654 Image sensor, 655 unit group, 656 pixel unit

Claims (4)

A plurality of regions having a plurality of light receiving units, an imaging region in which imaging conditions of light incident on the plurality of light receiving units can be set for each region, and a plurality of output units for outputting signals from the regions; An imaging unit having
A plurality of signals output from a plurality of output units for each region are input, a plurality of input units that output signals from the region to a plurality of signal conversion units, the plurality of input units, and the plurality of signal conversions And a plurality of selection units that select the signal conversion unit to which signals output from the plurality of output units for each region are input, and are stacked on the imaging unit A processing unit,
The imaging unit
The plurality of regions include a first region and a second region,
As the plurality of output units, a first output unit and a second output unit that output a first signal from the first region, and a third output unit and a fourth output that output a second signal from the second region. And
The signal processing unit
The plurality of input units include a first input unit and a second input unit to which the first signal is input, and a third input unit and a fourth input unit to which the second signal is input,
The first selection unit connected to the first input unit and the third input unit as the plurality of selection units and having a state of outputting the first signal and a state of outputting the second signal; An electronic apparatus having a second selection unit connected to a second input unit and the fourth input unit and having a state of outputting the first signal and a state of outputting the second signal . The first selecting unit, possess a state of outputting both said first signal and said second signal, and a state in which the first signal nor also output the second signal,
The second selection unit, an electronic apparatus of claim 1 further comprising a state of outputting both said first signal and said second signal, and a state in which the first signal nor also outputs the second signal. The first output unit, the second output unit, the third output unit, the fourth output unit, the first input unit, the second input unit, the third input unit, the electronic device according to claim 1 or 2 and the fourth input unit is a bump. The signal processing unit
The plurality of signal conversion units include a first signal conversion unit and a second signal conversion unit that convert a signal output from the first selection unit and a signal output from the second selection unit into a digital signal.
The electronic device as described in any one of Claim 1 to 3 .

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