JP5928184B2 - Power supply device, control circuit, electronic device, and power supply control method - Google Patents

Description

  The present invention relates to a power supply device, a control circuit, an electronic device, and a power supply control method.

  In an electronic device or the like, a switching power supply is used to supply power to a load, and for example, a DC-DC converter that converts a DC voltage into another DC voltage is used. Conventionally, a comparator-type DC-DC converter is known as a DC-DC converter capable of high-speed response to a sudden load change (for example, see Patent Document 1).

  FIG. 15 shows an example of a conventional comparator-type DC-DC converter. The DC-DC converter 4 includes a converter unit 5 and a control circuit 6. The converter unit 5 includes transistors T11 and T12, a coil L11, and a capacitor C11.

  The comparator 80 in the control circuit 6 receives the feedback voltage VFB2 (here, the divided voltage obtained by dividing the output voltage Vo1 by the resistors R11 and R12) and the reference voltage VR11 according to the output voltage Vo1. The The comparator 80 compares the feedback voltage VFB2 with the reference voltage VR11 and outputs an output signal S11 having a level corresponding to the comparison result to the set terminal S of the RS flip-flop (RS-FF circuit) 81. The oscillator 82 outputs a clock signal CLK having a constant frequency to the reset terminal R of the RS-FF circuit 81.

  The RS-FF circuit 81 is in a reset state in response to the H level clock signal CLK and outputs the L level output signal S12. Then, the drive circuit 83 outputs H level control signals DH and DL to turn off the transistor T11 and turn on the transistor T12. At this time, the switch circuit SW11 is turned off in response to the L-level output signal S12 output from the RS-FF circuit 81. Then, since the capacitor C13 is charged according to the current I11 supplied from the current source 84, the reference voltage VR11 increases from the reference voltage VR0 with a fixed slope (= I11 / C13).

  When the reference voltage VR11 becomes higher than the feedback voltage VFB2, the comparator 80 outputs an H level output signal S11. In response to the H level output signal S11, the RS-FF circuit 81 enters a set state and outputs an H level output signal S12. Then, the drive circuit 83 outputs L level control signals DH and DL to turn on the transistor T11 and turn off the transistor T12.

  As described above, in the comparator-type DC-DC converter 4, the feedback voltage VFB2 corresponding to the output voltage Vo1 and the reference voltage VR11 are always compared by the comparator 80, and the main-side transistor is immediately compared according to the comparison result. T11 is switched. Therefore, the comparator-type DC-DC converter 4 can respond to a sudden load change at high speed.

JP 2011-182533 A

  By the way, in recent DC-DC converters, a ceramic capacitor having a low equivalent series resistance (ESR) is often adopted as the capacitor C11 in the converter unit 5 because of its low cost. However, if the equivalent series resistance ESR of the ceramic capacitor becomes too low, a sufficient phase margin cannot be secured, and a problem arises that ringing occurs in the output voltage Vo1 in high-frequency operation such as during sudden load changes.

  According to one aspect of the present invention, a converter unit having a switch circuit to which an input voltage is supplied, and a coil connected between the switch circuit and an output terminal that outputs an output voltage, and the output voltage A control circuit that switches the switch circuit at a timing according to a comparison result between a corresponding feedback voltage and a reference voltage, the control circuit including a first current generated according to a reference voltage, and the input A reference voltage generation circuit configured to generate the reference voltage that changes based on a rate of change of the coil current flowing through the coil in accordance with a difference current from the second current proportional to the voltage;

  According to one aspect of the present invention, there is an effect that a phase margin can be ensured.

The block circuit diagram which shows the DC-DC converter of 1st Embodiment. The wave form diagram which shows the operation | movement of the DC-DC converter of 1st Embodiment. The circuit diagram which shows the internal structural example of a timer circuit. (A) is a circuit diagram showing an example of an internal configuration of the reference voltage generation circuit of the first embodiment, and (b) is a waveform diagram showing an operation of the reference voltage generation circuit of the first embodiment. FIG. 3 is a circuit diagram showing an example of an internal configuration of the gm amplifier according to the first embodiment. FIG. 3 is a circuit diagram illustrating an internal configuration example of a current source according to the first embodiment. Explanatory drawing which shows the simulation result at the time of sudden load change. (A), (b) is a characteristic view for demonstrating the frequency characteristic of the DC-DC converter of 1st Embodiment. Explanatory drawing which shows the simulation result at the time of sudden load change. The block circuit diagram which shows the DC-DC converter of 2nd Embodiment. (A) is a circuit diagram showing an example of an internal configuration of the reference voltage generation circuit of the second embodiment, (b) is a waveform diagram showing the operation of the reference voltage generation circuit of the second embodiment. The circuit diagram which shows the internal structural example of the gm amplifier of 2nd Embodiment. The circuit diagram which shows the internal structural example of the current source of 2nd Embodiment. 1 is a schematic configuration diagram illustrating an electronic device. The block circuit diagram which shows the conventional DC-DC converter.

Hereinafter, the first embodiment will be described with reference to FIGS.
As shown in FIG. 1, the DC-DC converter 1 includes a converter unit 2 that generates an output voltage Vo lower than the input voltage Vi based on the input voltage Vi, and a control circuit 3 that controls the converter unit 2. Have.

First, an internal configuration example of the converter unit 2 will be described.
A main-side transistor T1 and a synchronization-side transistor T2 are connected in series between an input terminal Pi to which an input voltage Vi is supplied and a power supply line (here, ground) having a potential lower than the input voltage Vi. Has been. The main transistor T1 is a P-channel MOS transistor, and the synchronous transistor T2 is an N-channel MOS transistor.

  The transistor T1 has a first terminal (source) connected to the input terminal Pi and a second terminal (drain) connected to the first terminal (drain) of the transistor T2. The second terminal (source) of the transistor T2 is connected to the ground.

  The control signal DH is supplied from the control circuit 3 to the control terminal (gate) of the transistor T1, whereas the control signal DL is supplied from the control circuit 3 to the control terminal (gate) of the transistor T2. These transistors T1 and T2 are complementarily turned on and off in response to control signals DH and DL.

  A node LX between the transistors T1 and T2 is connected to the first terminal of the coil L. The second terminal of the coil L is connected to the output terminal Po. Thus, the main-side transistor T1 and the coil L are connected in series between the input terminal Pi and the output terminal Po. Here, an output voltage Vo lower than the input voltage Vi is generated at the output terminal Po. This output voltage Vo is supplied to a load (not shown) connected to the output terminal Po. An output current Io is also supplied to this load.

  The second terminal of the coil L is connected to the first terminal of the smoothing capacitor C1, and the second terminal of the capacitor C1 is connected to the ground. The capacitor C1 is included in a smoothing circuit that smoothes the output voltage Vo. The resistance connected in series to the coil L is an equalized DC resistance DCR included in the coil L, and the resistance connected in series to the capacitor C1 is an equivalent series resistance ESR included in the capacitor C1.

  The control circuit 3 adjusts the pulse widths of the control signals DH and DL based on the output voltage Vo fed back from the converter unit 2. The control circuit 3 includes resistors R1 and R2, a comparator 10, a reference voltage generation circuit 20, an RS-flip flop (RS-FF circuit) 30, a timer circuit 40, and a drive circuit 50. Yes.

  A feedback voltage VFB based on the output voltage Vo is supplied to the inverting input terminal of the comparator 10. In the present embodiment, the feedback voltage VFB generated by the resistors R1 and R2 is supplied to the inverting input terminal of the comparator 10. Specifically, the output voltage Vo is fed back by connecting the output terminal Po to the first terminal of the resistor R1. The second terminal of the resistor R1 is connected to the first terminal of the resistor R2, and the second terminal of the resistor R2 is connected to the ground. A connection point between the resistors R1 and R2 is connected to the inverting input terminal of the comparator 10. Here, the resistors R1 and R2 generate a feedback voltage VFB obtained by dividing the output voltage Vo according to the respective resistance values. The value of the feedback voltage VFB corresponds to the resistance value ratio between the resistors R1 and R2 and the potential difference between the output voltage Vo and the ground. Therefore, the resistors R1 and R2 generate a feedback voltage VFB that is proportional to the output voltage Vo.

  The reference voltage VR <b> 1 is supplied from the reference voltage generation circuit 20 to the non-inverting input terminal of the comparator 10. Here, the input voltage Vi, the reference voltage VR0 generated by the reference power source E1, and the output signal SG1 output from the output terminal Q of the RS-FF circuit 30 are input to the reference voltage generation circuit 20. . The reference voltage generation circuit 20 has a rate of change of the coil current IL flowing through the coil L in accordance with a difference current between the first current generated according to the reference voltage VR0 and the second current proportional to the input voltage Vi. Based on the reference voltage VR1, the voltage value changes. For example, the reference voltage generation circuit 20 generates the reference voltage VR1 whose voltage value varies in a phase opposite to the coil current IL in accordance with the difference current between the first current and the second current. The reference voltage generation circuit 20 generates the reference voltage VR1 so that the average value of the reference voltage VR1 matches the reference voltage VR0. The voltage value of the reference voltage VR0 is set according to the target value (target voltage) of the output voltage Vo.

  The comparator 10 generates an output signal S1 corresponding to the comparison result between the feedback voltage VFB and the reference voltage VR1. Specifically, the comparator 10 generates an L level output signal S1 when the feedback voltage VFB is higher than the reference voltage VR1, and the H level output signal S1 when the feedback voltage VFB is lower than the reference voltage VR1. Is generated. The output signal S1 is supplied to the set terminal S of the RS-FF circuit 30.

  An output signal S2 output from the timer circuit 40 is supplied to the reset terminal R of the RS-FF circuit 30. The RS-FF circuit 30 outputs an H level output signal SG1 from the output terminal Q in response to the H level output signal S1, and outputs an L level output signal SG2 from the inverting output terminal XQ. The RS-FF circuit 30 outputs an L level output signal SG1 and an H level output signal SG2 in response to the H level output signal S2. That is, for the RS-FF circuit 30, the H level output signal S1 is a set signal, and the H level output signal S2 is a reset signal. The output signal SG1 output from the RS-FF circuit 30 is supplied to the reference voltage generation circuit 20, the timer circuit 40, and the drive circuit 50.

  In response to the H level output signal SG1, the timer circuit 40 generates an output signal S2 that becomes H level after a predetermined time has elapsed from the rising timing of the output signal SG1. Here, the predetermined time is, for example, a time depending on the input voltage Vi and the output voltage Vo. That is, the timer circuit 40 generates the output signal S2 that becomes H level after the elapse of time depending on the input voltage Vi and the output voltage Vo from the rising timing of the output signal SG1. The output signal S2 is supplied to the reset terminal R of the RS-FF circuit 30.

  Based on the output signals SG1 and SG2 from the RS-FF circuit 30, the drive circuit 50 generates control signals DH and DL for turning on and off the transistors T1 and T2 of the converter unit 2 in a complementary manner. Specifically, the drive circuit 50 generates L level control signals DH and DL in response to the H level output signal SG1 and the L level output signal SG2, and outputs the L level output signal SG1 and the H level output signal SG1. In response to the signal SG2, H level control signals DH and DL are generated. The main-side transistor T1 is turned on in response to the L level control signal DH, and is turned off in response to the H level control signal DH. The synchronous transistor T2 is turned on in response to the H level control signal DL, and turned off in response to the L level control signal DL. In the drive circuit 50, a dead time may be set in the control signals DH and DL so that both transistors T1 and T2 are not turned on simultaneously.

In the present embodiment, the DC-DC converter 1 is an example of a power supply device, and the transistor T1 is an example of a switch circuit.
Next, the operation of the DC-DC converter 1 will be briefly described with reference to FIG. In FIG. 2, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.

  When the reference voltage VR1 becomes higher than the feedback voltage VFB at time t1 shown in FIG. 2, the comparator 10 outputs an H-level output signal S1. In response to the H level output signal S1, the RS-FF circuit 30 outputs an H level output signal SG1 and an L level output signal SG2. The drive circuit 50 generates L level control signals DH and DL in response to the H level output signal SG1 and the L level output signal SG2. Then, the main-side transistor T1 is turned on in response to the L-level control signal DH, and the synchronous-side transistor T2 is turned off in response to the L-level control signal DL. Thus, when the reference voltage VR1 crosses the feedback voltage VFB, the control circuit 3 generates the H-level control signal DH for turning on the main-side transistor T1. In other words, the on-timing of the transistor T1 is set according to the comparison result between the feedback voltage VFB and the reference voltage VR1. In the following description, a period during which the main transistor T1 is on is referred to as an on period Ton (see times t1 to t2).

  In the converter unit 2 in the on period Ton, the input terminal Pi is connected to the output terminal Po through the transistor T1 and the coil L, so that a current path from the input terminal Pi to the output terminal Po through the coil L is formed. In such an on period Ton, the coil current IL corresponding to the potential difference between the input voltage Vi and the output voltage Vo flows through the coil L, and energy is accumulated in the coil L. In the on period Ton, the coil current IL increases with a predetermined slope as time passes. Specifically, the slope m1 of the coil current IL in the on-period Ton is defined such that the voltage values of the input voltage Vi and the output voltage Vo are Vi and Vo, respectively, and the inductance value of the coil L is L.

It becomes. That is, the coil current IL in the on period Ton increases in proportion to the potential difference between the input voltage Vi and the output voltage Vo.

  On the other hand, in response to the H level output signal SG1, the timer circuit 40 outputs the H level output signal S2 after a predetermined time has elapsed from the rising timing of the output signal SG1. Then, the RS-FF circuit 30 outputs the L level output signal SG1 and the H level output signal SG2 in response to the H level output signal S2 (time t2). The drive circuit 50 generates H-level control signals DH and DL in response to the L-level output signal SG1 and the H-level output signal SG2. Then, the main transistor T1 is turned off in response to the H level control signal DH, and the synchronous transistor T2 is turned on in response to the H level control signal DL. As described above, the control circuit 3 turns off the main transistor T1 and turns on the synchronous transistor T2 after a predetermined time has elapsed since turning on the main transistor T1. In other words, when the feedback voltage VFB becomes lower than the reference voltage VR1, the control circuit 3 turns on the main-side transistor T1 for a predetermined time. In the following description, a period in which the main transistor T1 is off is referred to as an off period Toff (see times t2 to t3).

  In the converter unit 2 in the off period Toff, since the ground is connected to the output terminal Po through the transistor T2 and the coil L, a current path from the ground to the output terminal Po through the coil L is formed. In such an off period Toff, the energy stored in the coil L in the on period Ton is released toward the output terminal Po, and an induced current flows through the coil L. In the off period Toff, the coil current IL decreases with a predetermined slope as time passes. Specifically, the slope m2 of the coil current IL in the off period Toff is

It becomes. That is, the coil current IL in the off period Toff decreases in proportion to the output voltage Vo.

  When the reference voltage VR1 crosses the feedback voltage VFB again (time t3), the control circuit 3 turns on the main transistor T1 and turns off the synchronous transistor T2. That is, when the predetermined switching period T ends, the next switching period T is started, and the on period Ton and the off period Toff are sequentially executed in the switching period T. By repeating such an operation, the output voltage Vo is maintained at the target voltage based on the reference voltage VR0. The average value of the coil current IL in each switching period T is the output current Io.

Next, an example of the internal configuration of the timer circuit 40 will be described.
As shown in FIG. 3, the timer circuit 40 includes an operational amplifier 41, resistors R40, R41, and R42, an N channel MOS transistor T40, P channel MOS transistors T41 and T42, a capacitor C40, a switch SW40, and a comparator. 42.

  A voltage VN40 corresponding to the input voltage Vi is supplied to the non-inverting input terminal of the operational amplifier 41. In this example, the voltage VN40 generated by the resistors R40 and R41 is supplied to the non-inverting input terminal of the operational amplifier 41. Specifically, the input voltage Vi is input to the first terminal of the resistor R40 by connecting the input terminal Pi. The second terminal of the resistor R40 is connected to the first terminal of the resistor R41, and the second terminal of the resistor R41 is connected to the ground. A node N40 between the resistors R40 and R41 is connected to the non-inverting input terminal of the operational amplifier 41. Here, the resistors R40 and R41 generate a voltage VN40 obtained by dividing the input voltage Vi in accordance with the respective resistance values. The value of the voltage VN40 corresponds to the ratio of the resistance values of the resistors R40 and R41 and the potential difference between the input voltage Vi and the ground. For this reason, the voltage VN40 proportional to the input voltage Vi is supplied to the non-inverting input terminal of the operational amplifier 41.

  The output terminal of the operational amplifier 41 is connected to the gate of the transistor T40. The source of the transistor T40 is connected to the first terminal of the resistor R42 and the inverting input terminal of the operational amplifier 41, and the second terminal of the resistor R42 is connected to the ground. The drain of the transistor T40 is connected to the drain of the transistor T41.

  A potential difference corresponding to the current flowing through the resistor R42 and the resistance value of the resistor R42 is generated between both terminals of the resistor R42. The operational amplifier 41 generates the gate voltage of the transistor T40 so that the potential of the node between the resistor R42 and the transistor T40 is equal to the voltage VN40 of the node N40. That is, the voltage at the first terminal of the resistor R42 is controlled to be the voltage VN40 at the node N40. Therefore, a current I40 corresponding to the resistance value of the resistor R42 and the potential difference (voltage VN40) between the two terminals flows between both terminals of the resistor R42. Therefore, the current I40 is

Can be expressed as That is, a current I40 proportional to the input voltage Vi flows between both terminals of the resistor R42.

  A bias voltage VB is supplied to the source of the transistor T41. The gate of the transistor T41 is connected to the drain of the transistor T41 and the gate of the P-channel MOS transistor T42. The bias voltage VB is an input voltage Vi or a voltage generated by a power supply circuit (not shown). A bias voltage VB is supplied to the source of the transistor T42. Therefore, these transistors T41 and T42 are included in the current mirror circuit. In this example, the transistor T41 and the transistor T42 have the same electrical characteristics. For this reason, the current mirror circuit causes the current I41 (= VN40 / R42) having the same current value as the current flowing through the transistor T41 to flow through the transistor T42.

  The drain of the transistor T42 is connected to the first terminal of the capacitor C40 and the first terminal of the switch SW40. The second terminal of the capacitor C40 and the second terminal of the switch SW40 are connected to the ground. Thus, the switch SW40 is connected in parallel to the capacitor C40. The switch SW40 is, for example, a P channel MOS transistor. A current I41 depending on the input voltage Vi flows from the transistor T42 through the capacitor C40.

  An output signal SG1 output from the RS-FF circuit 30 (see FIG. 1) is supplied to the control terminal of the switch SW40. Here, the main-side transistor T1 (see FIG. 1) is turned on when the output signal SG1 is at the H level, while the main-side transistor T1 is turned off when the output signal SG1 is at the L level. On the other hand, the switch SW40 is turned on when the output signal SG1 is at the L level (when the transistor T1 is turned off). When the switch SW40 is thus turned on, both terminals of the capacitor C40 are connected to each other, so that the voltage VN41 at the first terminal (node N41) of the capacitor C40 is at the ground level. On the other hand, the switch SW40 is turned off when the output signal SG1 is at the H level (when the transistor T1 is turned on). When the switch SW40 is thus turned off, the capacitor C40 is charged by the current I41 (current depending on the input voltage Vi) supplied from the transistor T42. As a result, the voltage VN41 at the node N41 rises from the ground level with a slope corresponding to the input voltage Vi. That is, the timer circuit 40 resets the voltage VN41 of the node N41 to the ground level by short-circuiting both terminals of the capacitor C40 when the main-side transistor T1 is off. Then, the timer circuit 40 starts charging the capacitor C40 when the transistor T1 is turned on. As a result, the voltage VN41 at the node N41 rises with a slope corresponding to the input voltage Vi.

  Node N41 is connected to the non-inverting input terminal of comparator. An output voltage Vo is supplied to the inverting input terminal of the comparator 42. The comparator 42 outputs an output signal S2 corresponding to the comparison result between the voltage VN41 of the node N41 and the output voltage Vo to the reset terminal R of the RS-FF circuit 30 (see FIG. 1). Specifically, the comparator 42 outputs the L level output signal S2 when the voltage VN41 is lower than the output voltage Vo, while outputting the H level output signal S2 when the voltage VN41 becomes higher than the output voltage Vo. To do. Here, as described above, the voltage VN41 at the node N41 rises with a slope corresponding to the input voltage Vi when the main-side transistor T1 is turned on. Therefore, the period from when the transistor T1 is turned on until the H-level output signal S2 is output depends on the input voltage Vi and the output voltage Vo. Specifically, the on-period Ton of the main-side transistor T1 is

Can be expressed as

  By the way, when the input voltage Vi and the output voltage Vo are stable, the output voltage Vo becomes a voltage according to the input voltage Vi and the on-duty of the transistor T1 on the main side. The on-duty of the transistor T1 is represented by the ratio of the cycle of turning on the transistor T1, that is, the switching cycle T, and the on-period Ton of the transistor T1. Therefore, the output voltage Vo is

It becomes.

  The switching period T is a total value of the on period Ton and the off period Toff in which the transistor T1 is off. Therefore, the on period Ton is

The off-period Toff is

Can be expressed as From Equation 4 and Equation 6 above,

This relationship holds. That is, the switching cycle T (switching frequency) is determined according to the resistance values of the resistors R40 to R42 in the timer circuit 40, the capacitance value of the capacitor C40, and the like. Further, the timer circuit 40 adjusts the timing of outputting the H level output signal S2, that is, the H level pulse width (ON period Ton) of the output signal SG1, in accordance with the input voltage Vi and the output voltage Vo. .

Next, an example of the internal configuration of the reference voltage generation circuit 20 will be described.
As shown in FIG. 4A, the reference voltage generation circuit 20 includes an error amplifier circuit 21, a transconductance amplifier (gm amplifier) 22, resistors R20 and R21, capacitors C20 and C21, a switch element SW20, And a current source 23.

  A reference voltage VR0 is supplied to the non-inverting input terminal of the error amplifier circuit 21. The output terminal of the error amplifier circuit 21 is connected to the first terminal of the resistor R20 and the input terminal of the gm amplifier 22. The second terminal of the resistor R20 is connected to the first terminal of the capacitor C20, and the second terminal of the capacitor C20 is connected to the inverting input terminal of the error amplifier circuit 21.

  The output terminal of the gm amplifier 22 is connected to the first terminal of the resistor R21, and the second terminal of the resistor R21 is connected to the inverting input terminal of the error amplifier circuit 21 and the second terminal of the capacitor C20. The resistors R20 and R21 and the capacitor C20 function as a low pass filter.

  The output terminal of the gm amplifier 22 is connected to the first terminal of the switch element SW20. This gm amplifier 22 converts the output voltage VN20 (voltage of the node N20) of the error amplifier circuit 21 into a current, and generates an amplifier current I20 corresponding to the output voltage VN20. For example, the gm amplifier 22 discharges the amplifier current I20 to the node N21 between the gm amplifier 22 and the switch element SW20.

  The second terminal of the switch element SW20 is connected to the first terminal of the current source 23, and the second terminal of the current source 23 is connected to the ground. The switch element SW20 is, for example, an N channel MOS transistor. The current source 23 passes a current I21 (= α × Vi) proportional to the input voltage Vi. For example, the current source 23 sucks the current I21 from the node N21.

  A node N21 between the gm amplifier 22 and the switch element SW20 is connected to the first terminal of the capacitor C21, and the second terminal of the capacitor C21 is connected to the ground. A current I22 corresponding to the amplifier current I20 and the current I21 flows through the capacitor C21. The voltage at the first terminal (node N21) of the capacitor C21 (charging voltage of the capacitor C21) is output as the reference voltage VR1.

  An output signal SG1 output from the RS-FF circuit 30 (see FIG. 1) is supplied to the control terminal of the switch element SW20. The switch element SW20 is turned off when the output signal SG1 is at the L level (when the transistor T1 is turned off). When the switch element SW20 is turned off in this way, the current source 23 is disconnected from the node N21. For this reason, the amplifier current I20 (current I22) flows through the capacitor C21. Thereby, the capacitor C21 is charged by the current I22 (amplifier current I20). As a result, as shown in FIG. 4B, during the period when the output signal SG1 is at the L level (the off period Toff of the transistor T1), the reference voltage VR1 rises with a predetermined slope as time passes. Specifically, the slope m3 of the reference voltage VR1 in the off period Toff is given by assuming that the capacitance value of the capacitor C21 is C21.

It becomes.

  On the other hand, the switch element SW20 shown in FIG. 4A is turned on when the output signal SG1 is at the H level (when the transistor T1 is turned on). When the switch element SW20 is thus turned on, the current source 23 is connected to the node N21 via the switch element SW20. For this reason, the current I22 corresponding to the amplifier current I20 and the current I21 flows through the capacitor C21. Specifically, a current I22 (= I21−I20) that is a difference current between the amplifier current I20 and the current I21 flows through the capacitor C21. As a result, the capacitor C21 is discharged by the current I22 (the difference current between the amplifier current I20 and the current I21). As a result, as shown in FIG. 4B, during the period in which the output signal SG1 is at the H level (the on period Ton of the transistor T1), the reference voltage VR1 decreases with a predetermined slope as time passes. Specifically, the slope m4 of the reference voltage VR1 in the on period Ton is

It becomes.

  In the reference voltage generation circuit 20 shown in FIG. 4A, when the switch element SW20 is turned on in response to the H level output signal SG1, the capacitor C21 causes the current I21 (proportional to the input voltage Vi ( = Α × Vi) and the differential current between the amplifier current I20 of the gm amplifier 22 and the discharge. Here, the switch element SW20 is controlled to be turned on / off by the output signal SG1 that determines whether the transistor T1 is turned on / off, and the charge accumulated in the capacitor C21 is extracted by the current I21. Therefore, the current discharged from the capacitor C21 is reduced. The average value Ia is

It becomes. Here, D in Equation 11 is the on-duty of the transistor T1.

  The low-pass filter including resistors R20 and R21 and a capacitor C20 cumulatively averages the reference voltage VR1 that is the charging voltage of the capacitor C21. That is, the average value of the reference voltage VR1 is supplied to the inverting input terminal of the error amplifier circuit 21. The error amplifier circuit 21 changes the output voltage VN20 so that the average value of the reference voltage VR1 is equal to the reference voltage VR0. An amplifier current I20 corresponding to the output voltage VN20 is generated by the gm amplifier 22, and the amplifier current I20 flows to charge the capacitor C21. That is, the amplifier current I20 is generated to be equal to the average value Ia of the current discharged from the capacitor C21 by feedback control by the error amplifier circuit 21 and the gm amplifier 22 and the like. Therefore, the amplifier current I20 is

Can be expressed as Here, the on-duty D of the transistor T1 is given by the above equation 5.

It can also be expressed as Therefore, the amplifier current I20 is

It becomes.

  From Equation 9, Equation 10, and Equation 14, the slope m3 of the reference voltage VR1 in the off period Toff of the transistor T1 and the slope m4 of the reference voltage VR1 in the on period Ton are:

Can be expressed as That is, the reference voltage VR1 in the off period Toff increases in proportion to the output voltage Vo, and the reference voltage VR1 in the on period Ton decreases in proportion to the potential difference between the input voltage Vi and the output voltage Vo.

  From the above, it can be said that the reference voltage VR1 is a voltage signal having a phase opposite to that of the coil current IL. Specifically, the reference voltage VR1 can be said to be a voltage signal having a triangular wave having a phase opposite to that of the coil current IL. More specifically, the reference voltage VR1 can be said to be a voltage signal that varies in the opposite direction to the ripple component (variation component) of the coil current IL based on the rate of change of the ripple component. More specifically, as shown in FIG. 2, in the on period Ton (see times t1 to t2), the coil current IL increases with a slope m1 proportional to the potential difference between the input voltage Vi and the output voltage Vo, while the reference voltage VR1 decreases with a slope m4 proportional to the potential difference between the input voltage Vi and the output voltage Vo. In the off period Toff (see times t2 to t3), the coil current IL decreases with a slope m2 proportional to the output voltage Vo, while the reference voltage VR1 increases with a slope m3 proportional to the output voltage Vo. Further, as described above, the reference voltage VR1 and the coil current IL are signals having the same period (frequency) and having phases shifted from each other by about 180 degrees. For this reason, for example, the minimum point of the amplitude of the reference voltage VR1 and the maximum point of the amplitude of the coil current IL coincide with each other in time (see time t2), and the maximum point of the amplitude of the reference voltage VR1 and the minimum of the amplitude of the coil current IL. The point coincides in time (see time t3).

  The reference voltage VR1 is controlled so that the average value thereof is equal to the reference voltage VR0 by feedback control using the error amplifier circuit 21 and the gm amplifier 22 described above.

  Incidentally, the gain of the negative feedback loop of the DC-DC converter 1 is proportional to the input voltage Vi and inversely proportional to the slope amount Vslp of the reference voltage VR1. Therefore, when the frequency is 0 [Hz], the gain at that time is Gain.

Can be expressed as Here, the slope amount Vslp of the reference voltage VR1 in the off period Toff is expressed by the above equation 15 when the time of the off period Toff is Toff.

It becomes. Therefore, as apparent from the above equation 18, the slope amount Vslp of the reference voltage VR1 can be adjusted by adjusting the proportionality coefficient α of the amplifier current I20 (current I21) and the capacitance value of the capacitor C21. Further, as apparent from the above equation 17, the gain Gain of the negative feedback loop can be adjusted by adjusting the proportionality coefficient α of the current I21 and the capacitance value of the capacitor C21.

  The gm amplifier 22 is an example of a voltage-current conversion circuit, the amplifier current I20 is an example of a first current, the current I21 is an example of a second current, and the current I22 is an example of a differential current between the first current and the second current. .

Next, an example of the internal configuration of the gm amplifier 22 will be described.
As shown in FIG. 5, the gm amplifier 22 has an N-channel MOS transistor T20, a resistor R22, and P-channel MOS transistors T21 and T22.

  A node N20 is connected to the gate of the transistor T20, and the output voltage VN20 of the error amplifier circuit 21 is supplied. The source of the transistor T20 is connected to the first terminal of the resistor R22, and the second terminal of the resistor R22 is connected to the ground. The drain of the transistor T20 is connected to the drain of the transistor T21. The transistor T20 is on / off controlled by the output voltage VN20, and the on-resistance is controlled by the output voltage VN20. A current I23 proportional to the output voltage VN20 flows through the transistor T20.

  A bias voltage VB is supplied to the source of the transistor T21. The gate of the transistor T21 is connected to the drain of the transistor T21 and the gate of the transistor T22. The transistor T22 has a source supplied with a bias voltage VB and a drain connected to the node N21. Therefore, these transistors T21 and T22 are included in the current mirror circuit. In this current mirror circuit, the amplifier current I20 proportional to the current I23 flowing through the transistor T21 is caused to flow through the transistor T22 in accordance with the electrical characteristics of the transistors T21 and T22. That is, the transistor T22 discharges the amplifier current I20 to the node N21.

Next, an example of the internal configuration of the current source 23 will be described.
As shown in FIG. 6, the current source 23 includes resistors R23, R24, R25, an operational amplifier 24, an N channel MOS transistor T23, P channel MOS transistors T24, T25, and N channel MOS transistors T26, T27. doing.

  A voltage VN22 corresponding to the input voltage Vi is supplied to the non-inverting input terminal of the operational amplifier 24. In this example, the voltage VN22 generated by the resistors R23 and R24 is supplied to the non-inverting input terminal of the operational amplifier 24. Specifically, the input voltage Vi is input to the first terminal of the resistor R23 by connecting the input terminal Pi. The second terminal of the resistor R23 is connected to the first terminal of the resistor R24, and the second terminal of the resistor R24 is connected to the ground. A node N22 between the resistors R23 and R24 is connected to the non-inverting input terminal of the operational amplifier 24. Here, the resistors R23 and R24 generate a voltage VN22 obtained by dividing the input voltage Vi according to the respective resistance values. The value of the voltage VN22 corresponds to the ratio of the resistance values of the resistors R23 and R24 and the potential difference between the input voltage Vi and the ground. For this reason, the voltage VN22 proportional to the input voltage Vi is supplied to the non-inverting input terminal of the operational amplifier 24.

  The output terminal of the operational amplifier 24 is connected to the gate of the transistor T23. The source of the transistor T23 is connected to the first terminal of the resistor R25 and the inverting input terminal of the operational amplifier 24, and the second terminal of the resistor R25 is connected to the ground. The drain of the transistor T23 is connected to the drain of the transistor T24.

  A potential difference corresponding to the current flowing through the resistor R25 and the resistance value of the resistor R25 occurs between both terminals of the resistor R25. The operational amplifier 24 generates the gate voltage of the transistor T23 so that the potential of the node between the resistor R25 and the transistor T23 is equal to the voltage VN22 of the node N22. That is, the voltage at the first terminal of the resistor R25 is controlled to be the voltage VN22 at the node N22. Therefore, a current I25 corresponding to the resistance value of the resistor R25 and the potential difference (voltage VN22) between the two terminals flows between both terminals of the resistor R25. Therefore, the current I25 is

Can be expressed as That is, a current I25 proportional to the input voltage Vi flows between both terminals of the resistor R25.

  A bias voltage VB is supplied to the source of the transistor T24. The gate of the transistor T24 is connected to the drain of the transistor T24 and the gate of the transistor T25. The transistor T25 has a source supplied with a bias voltage VB and a drain connected to the drain of the transistor T26. Therefore, these transistors T24 and T25 are included in the current mirror circuit. In this current mirror circuit, a current I26 proportional to the current I25 flowing through the transistor T24 is supplied to the transistor T25 in accordance with the electrical characteristics of the transistors T24 and T25. When the mirror ratio of the current mirror circuit including the transistors T24 and T25 is M1, the current I26 is

Can be expressed as

  The source of the transistor T26 is connected to the ground. The gate of the transistor T26 is connected to the drain of the transistor T26 and the gate of the transistor T27. The transistor T27 has a source connected to the ground and a drain connected to the node N21. Therefore, these transistor T26 and transistor T27 are included in the current mirror circuit. In this current mirror circuit, the current I21 proportional to the current I26 flowing through the transistor T26 is supplied to the transistor T27 in accordance with the electrical characteristics of the transistors T26 and T27. That is, the transistor T27 sinks the current I21 from the node N21. This current I21 is M2 when the mirror ratio of the current mirror circuit including the transistors T26 and T27 is M2.

It can also be expressed as Therefore, the proportionality coefficient α of the current I21 is

It becomes. From Equation 22, Equation 17 and Equation 18, the slope of the reference voltage VR1 is appropriately adjusted by appropriately adjusting the resistance values of the resistors R23 to R25, the mirror ratios M1 and M2, and the capacitance value of the capacitor C21 shown in FIG. It can be seen that the amount Vslp and the gain of the negative feedback loop can be adjusted.

  Next, the operation of the DC-DC converter 1 when the load connected to the output terminal Po changes suddenly will be described. FIG. 7 shows a simulation result when the load suddenly increases, specifically, when the output current Io is suddenly increased from 0 [A] to 3 [A]. 7, the input voltage Vi is 12 [V], the output voltage Vo is 1.2 [V], the inductance value of the coil L is 1.5 [μH], and the capacitance value of the capacitor C1 is 44 [V]. μF] and the equivalent series resistance ESR is 0 [Ω]. As described above, FIG. 7 shows a simulation result when the equivalent series resistance ESR is set to a small value (here, 0 [Ω]).

  As shown in FIG. 7, when the load suddenly increases and the output current Io rapidly increases at time t4, the output voltage Vo rapidly decreases. Then, the off-period Toff of the transistor T1 is shortened, and energy is accumulated in the coil L in the on-period Ton so as to increase the output voltage Vo. At this time, the voltage value of the reference voltage VR1 input to the comparator 10 changes based on the rate of change of the coil current IL. Here, the phase of the coil current IL is advanced by 90 degrees with respect to the output voltage Vo. For this reason, it can be said that a phase lead component is introduced into the reference voltage VR1 that varies based on the rate of change of the coil current IL. The transistor T1 is subjected to switching control according to the comparison result between the reference voltage VR1 into which the phase lead component is introduced and the feedback voltage VFB. Therefore, the DC-DC converter 1 operates so as to suppress the OFF period Toff from being shortened when the output voltage Vo is rapidly decreased with a rapid increase in load (see times t4 to t5). Such an operation is substantially the same as the operation at the time of sudden load change in the current mode control DC-DC converter that controls the on-duty of the transistor on the main side by feeding back two signals of the output voltage and the coil current. That is, the DC-DC converter 1 can operate in pseudo current mode control at the time of sudden load change by generating the reference voltage VR1 that varies in accordance with the variation component (AC component) of the coil current IL. Thereby, a phase margin of 90 degrees at the maximum can be ensured, and a phase margin can be secured as compared with the conventional DC-DC converter 4. Therefore, the DC-DC converter 1 can suppress the occurrence of ringing at the time of sudden load change. Hereinafter, this point will be described with reference to the simulation results shown in FIGS.

  FIG. 8 shows the result of a simulation of the frequency characteristics of the DC-DC converter 1 of this embodiment and the conventional DC-DC converter 4. FIG. 8A shows a phase curve representing a change in the phase of the gain of the negative feedback loop with respect to the frequency, and FIG. 8B shows a gain curve representing a change in the gain of the negative feedback loop with respect to the frequency. It is shown. FIG. 9 shows a simulation result of changes in the output voltages Vo and Vo1 when the output current Io is suddenly changed in the DC-DC converters 1 and 4. The simulation conditions in FIGS. 8 and 9 are the same as the simulation conditions shown in FIG. That is, the simulation conditions shown in FIGS. 8 and 9 are that the input voltage Vi is 12 [V], the output voltage Vo is 1.2 [V], the inductance value of the coil L is 1.5 [μH], and the capacitor C1 The capacitance value is 44 [μF], and the equivalent series resistance ESR is 0 [Ω].

  Here, the zero point Z1 that can be generated by the equivalent series resistance ESR shown in FIG.

Can be expressed as When the equivalent series resistance ESR is reduced, the zero point frequency becomes a high frequency, and it is difficult to secure a phase margin at the equivalent series resistance ESR. For this reason, in the conventional DC-DC converter 4, when the equivalent series resistance ESR is small, a sufficient phase margin (for example, a phase margin of 45 degrees or more) cannot be ensured. Specifically, as shown in the simulation result of FIG. 8, in the conventional DC-DC converter 4, when the equivalent series resistance ESR is small (here, 0 [Ω]), the phase margin is only 35.3 degrees. It cannot be ensured, and a sufficient phase margin cannot be ensured. Then, as shown in FIG. 9, there is a problem that when the output current Io suddenly changes and a high-frequency operation is performed, the phase margin is insufficient and ringing occurs in the output voltage Vo1.

  On the other hand, in the DC-DC converter 1 according to the present embodiment, even when it is difficult to ensure the phase margin with the equivalent series resistance ESR, the reference voltage VR1 that varies based on the rate of change of the coil current IL. A sufficient phase margin can be ensured by generating. Specifically, the DC-DC converter 1 has a phase margin of 63.2 degrees in the simulation result of FIG. 8, and can secure a phase margin of about 30 degrees more than the conventional DC-DC converter 4. Further, in the DC-DC converter 1, the frequency band is wider on the high frequency side than the conventional DC-DC converter 4. Then, in the DC-DC converter 1 with sufficient phase margin as described above, as shown in FIG. 9, even if the output current Io changes suddenly and becomes a high frequency operation, ringing occurs in the output voltage Vo. It is suppressed. That is, since the DC-DC converter 1 can secure a sufficient phase margin, the stability to oscillation is improved as compared with the conventional DC-DC converter 4.

  Here, another way of looking at the occurrence of the ringing is as follows. In the conventional DC-DC converter 4, the output voltage Vo increases as the load suddenly increases, as in the operation at the time of sudden load change of the voltage-mode controlled DC-DC converter. When the voltage drops rapidly, the transistor T1 is kept on until the output voltage Vo finishes decreasing. Then, the supply amount of the output current Io becomes excessive and the output voltage Vo1 overshoots, and thereafter, the operation is performed so as to decrease the supply amount of the output current Io. However, at this time, since the supply amount of the output current Io is controlled based on the overshooted output voltage Vo1, the supply amount of the output current Io becomes excessively small. By repeating such an operation, ringing as shown in FIG. 9 occurs in the output voltage Vo. As described above, in the conventional DC-DC converter 4, only the output voltage Vo1 whose phase is delayed by 90 degrees with respect to the coil current IL is fed back to control switching of the main-side transistor. Ringing occurs in the voltage Vo.

  On the other hand, in the DC-DC converter 1, the reference voltage VR1 to be compared with the feedback voltage VFB corresponding to the output voltage Vo is changed corresponding to the ripple component of the coil current IL. Thereby, in the DC-DC converter 1, when the output voltage Vo rapidly decreases as the load suddenly increases, as shown in the time t4 to t5 in FIG. 7, even if the output voltage Vo is decreased, the transistor An off period Toff of T1 is ensured (transistor T1 is turned off). For this reason, it is suppressed that the supply amount of the output current Io becomes excessive, and the occurrence of the overshoot of the output voltage Vo is suppressed. Thereby, in the DC-DC converter 1, it is suppressed that ringing generate | occur | produces in the output voltage Vo at the time of load sudden change. In the simulation result shown in FIG. 7, after the rapid decrease of the output voltage Vo is completed (see time t5), the voltage value of the output voltage Vo gradually increases so that the output voltage Vo approaches the target voltage. .

  Incidentally, as described above, the DC-DC converter 1 generates the reference voltage VR1 that fluctuates according to the ripple component of the coil current IL, and operates in a pseudo current mode control during a sudden load change. However, in the reference voltage generation circuit 20 of the DC-DC converter 1, the error amplification circuit 21 performs feedback control so that the average value (center value) of the reference voltage VR1 matches the reference voltage VR0. Different from mode control. More specifically, in the case of current mode control, as the output current increases, the output of the error amplifier circuit shifts its operating point by the DC component of the output current. On the other hand, since the reference voltage generation circuit 20 of the DC-DC converter 1 always operates so that the average value of the reference voltage VR1 approaches the reference voltage VR0, only the alternating current component (variation component) of the coil current IL is simulated. It can be said that the reference voltage VR1 is generated. In such a DC-DC converter 1, regardless of the voltage value of the input voltage Vi and the current value of the output current Io, the average value of the reference voltage VR1 is maintained at the reference voltage VR0 (constant voltage), and the output voltage Vo is the reference voltage. The target voltage (constant voltage) based on the voltage VR0 is maintained.

As described above, according to this embodiment, the following effects can be obtained.
(1) The reference voltage VR1 that changes based on the rate of change of the coil current IL is generated, and the transistor T1 is switched at a timing according to the comparison result between the reference voltage VR1 and the feedback voltage VFB. Thereby, it is possible to operate in a pseudo current mode control at the time of sudden load change, and it is possible to secure a phase margin of 90 degrees at the maximum. Therefore, occurrence of ringing in the output voltage Vo at the time of sudden load change can be suitably suppressed.

  (2) The reference voltage VR1 is generated so that the average value of the reference voltage VR1 is equal to the reference voltage VR0. Thereby, regardless of the voltage value of the input voltage Vi and the current value of the output current Io, the output voltage Vo can be maintained at the target voltage (constant voltage) based on the reference voltage VR0. That is, even when the input voltage Vi and the output current Io change, it is possible to suppress the voltage value of the output voltage Vo when the reference voltage VR1 is crossed. As a result, the output voltage Vo can be stabilized.

  (3) By generating the reference voltage VR1 that changes based on the rate of change of the coil current IL, a sufficient phase margin can be ensured even when the equivalent series resistance ESR is small. For this reason, a ceramic capacitor having a small equivalent series resistance ESR can be used as the capacitor C1. Thereby, size reduction and cost reduction of the DC-DC converter 1 can be achieved.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. In the DC-DC converter 1a of this embodiment, the internal configuration of the reference voltage generation circuit 20a that generates the reference voltage VR2 and the configuration of the comparator 11 that inputs the reference voltage VR2 are different from those of the first embodiment. Hereinafter, the difference from the first embodiment will be mainly described.

  As shown in FIG. 10, the reference voltage generation circuit 20a in the control circuit 3a is output from the input voltage Vi, the reference voltage VR0 generated by the reference power supply E1, and the output terminal Q of the RS-FF circuit 30. Output signal SG1 is input. The reference voltage generation circuit 20a has a voltage value based on a rate of change of the coil current IL according to a difference current between a first current generated according to the reference voltage VR0 and a second current proportional to the input voltage Vi. The reference voltage VR2 in which changes is generated. For example, the reference voltage generation circuit 20a generates the reference voltage VR2 whose voltage value varies in a phase relationship with the coil current IL according to the difference current between the first current and the second current. In addition, the reference voltage generation circuit 20a generates the reference voltage VR2 so that the average value of the reference voltage VR2 matches the reference voltage VR0.

  The comparator 11 has four input terminals, specifically, two inverting input terminals and two non-inverting input terminals. The feedback voltage VFB corresponding to the output voltage Vo is input to one inverting input terminal of the comparator 11, and the reference voltage VR2 is input to the other inverting input terminal of the comparator 11. The reference voltage VR0 is input to each of the two non-inverting input terminals of the comparator 11.

  The comparator 11 generates an output signal S1a corresponding to the comparison result of the feedback voltage VFB, the reference voltage VR2, and the two reference voltages VR0. Specifically, the comparator 11 generates the L-level output signal S1a when the result of adding the feedback voltage VFB and the reference voltage VR2 is higher than the result of adding the two reference voltages VR0. Further, the comparator 11 generates the H-level output signal S1a when the result of adding the feedback voltage VFB and the reference voltage VR2 is lower than the result of adding the two reference voltages VR0. The output signal S1a is a signal whose signal level transitions at the same timing as the output signal S1 of the first embodiment.

Next, an example of the internal configuration of the reference voltage generation circuit 20a will be described.
As shown in FIG. 11, the reference voltage generation circuit 20a includes an error amplification circuit 21a, a gm amplifier 22a, resistors R20a and R21a, capacitors C20a and C21a, a switch element SW20a, and a current source 23a. Yes.

  The reference voltage VR0 is supplied to the non-inverting input terminal of the error amplifier circuit 21a. The output terminal of the error amplifier circuit 21a is connected to the first terminal of the resistor R20a and the input terminal of the gm amplifier 22a. The second terminal of the resistor R20a is connected to the first terminal of the capacitor C20a, and the second terminal of the capacitor C20a is connected to the inverting input terminal of the error amplifier circuit 21a.

  The output terminal of the gm amplifier 22a is connected to the first terminal of the resistor R21a, and the second terminal of the resistor R21a is connected to the inverting input terminal of the error amplifier circuit 21a and the second terminal of the capacitor C20a. The resistors R20a and R21a and the capacitor C20a function as a low pass filter.

  The output terminal of the gm amplifier 22a is connected to the first terminal of the switch element SW20a. The gm amplifier 22a converts the output voltage VN20a of the error amplifier circuit 21a (the voltage of the node N20a) into a current, and generates an amplifier current I20a corresponding to the output voltage VN20a. For example, the gm amplifier 22a sucks the amplifier current I20a from the node N21a between the gm amplifier 22a and the switch element SW20a.

  The second terminal of the switch element SW20a is connected to the first terminal of the current source 23a, and the bias voltage VB is supplied to the second terminal of the current source 23a. The switch element SW20a is, for example, an N channel MOS transistor. Further, the current source 23a passes a current I21a (= α × Vi) proportional to the input voltage Vi. For example, the current source 23a discharges the current I21a to the node N21a.

  A node N21a between the gm amplifier 22a and the switch element SW20a is connected to the first terminal of the capacitor C21a, and the second terminal of the capacitor C21a is connected to the ground. A current I22a corresponding to the amplifier current I20a and the current I21a flows through the capacitor C21a. Then, the voltage at the first terminal (node N21a) of the capacitor C21a (charging voltage of the capacitor C21a) is output as the reference voltage VR2.

  An output signal SG1 output from the RS-FF circuit 30 (see FIG. 1) is supplied to the control terminal of the switch element SW20a. The switch element SW20a is turned off when the output signal SG1 is at the L level (when the main transistor T1 is turned off). Thus, when switch element SW20a is turned off, current source 23a is disconnected from node N21a. For this reason, the capacitor C21a is discharged by the amplifier current I20a (current I22a). As a result, as shown in FIG. 11B, during the period when the output signal SG1 is at the L level (the off period Toff of the transistor T1), the reference voltage VR2 decreases with a predetermined slope as time passes. Specifically, the slope m5 of the reference voltage VR2 in the off period Toff is given by assuming that the capacitance value of the capacitor C21a is C21a.

It becomes.

  On the other hand, the switch element SW20a shown in FIG. 11A is turned on when the output signal SG1 is at the H level (when the transistor T1 is turned on). When the switch element SW20a is turned on in this way, the current source 23a is connected to the node N21a via the switch element SW20a. Therefore, a current I22a corresponding to the amplifier current I20a and the current I21a flows through the capacitor C21a. Specifically, a current I22a (= I21a−I20a) that is a difference current between the amplifier current I20a and the current I21a flows through the capacitor C21a. As a result, the capacitor C21a is charged with the current I22a (the difference current between the amplifier current I20a and the current I21a). As a result, as shown in FIG. 11B, during the period in which the output signal SG1 is at the H level (the on period Ton of the transistor T1), the reference voltage VR2 increases with a predetermined slope as time passes. Specifically, the slope m6 of the reference voltage VR2 in the on period Ton is

It becomes.

  In the reference voltage generation circuit 20a shown in FIG. 11A, when the switch element SW20a is turned on in response to the H level output signal SG1, the capacitor C21a causes the current I21a (proportional to the input voltage Vi) = Α × Vi) and the differential current between the amplifier current I20a of the gm amplifier 22a is charged. Here, since the switch element SW20a is ON / OFF controlled by the output signal SG1 that determines ON / OFF of the transistor T1, and the electric charge is accumulated in the capacitor C21a by the current I21a, the average value of the current charged in the capacitor C21a Ib is

It becomes.

  Further, the low pass filter including the resistors R20a and R21a and the capacitor C20a cumulatively averages the reference voltage VR2 that is the charging voltage of the capacitor C21a. That is, the average value of the reference voltage VR2 is supplied to the inverting input terminal of the error amplifier circuit 21a. The error amplifier circuit 21a changes the output voltage VN20a so that the average value of the reference voltage VR2 is equal to the reference voltage VR0. An amplifier current I20a corresponding to the output voltage VN20a is generated by the gm amplifier 22a, and the amplifier current I20a flows to discharge the capacitor C21a. That is, the amplifier current I20a is generated to be equal to the average value Ib of the current charged in the capacitor C21a by feedback control by the error amplifier circuit 21a and the gm amplifier 22a. Therefore, the amplifier current I20a is

Can be expressed as Furthermore, when the on-duty D of the transistor T1 is replaced by the ratio of the input voltage Vi and the output voltage Vo according to the above equation 13, the amplifier current I20a is

It becomes.

  From Equation 24, Equation 25, and Equation 28, the slope m5 of the reference voltage VR2 in the off period Toff of the transistor T1 and the slope m6 of the reference voltage VR2 in the on period Ton are:

Can be expressed as That is, the reference voltage VR2 in the off period Toff decreases in proportion to the output voltage Vo, and the reference voltage VR2 in the on period Ton increases in proportion to the potential difference between the input voltage Vi and the output voltage Vo.

  From the above, it can be said that the reference voltage VR2 is a voltage signal in phase with the coil current IL. Specifically, the reference voltage VR2 can be said to be a voltage signal having a triangular wave in phase with the coil current IL. More specifically, the reference voltage VR2 can be said to be a voltage signal that varies in the same direction as the ripple component (variation component) of the coil current IL based on the rate of change of the ripple component. More specifically, as shown in FIGS. 2 and 11B, in the off period Toff, the coil current IL decreases with a slope m2 proportional to the output voltage Vo, while the reference voltage VR2 is proportional to the output voltage Vo. It decreases at an inclination m5. In the ON period Ton, the coil current IL increases with a slope m1 proportional to the potential difference between the input voltage Vi and the output voltage Vo, while the reference voltage VR2 has a slope proportional to the potential difference between the input voltage Vi and the output voltage Vo. Ascend at m6. Thus, the reference voltage VR2 and the coil current IL are signals having the same period (frequency) and having the same phase.

  The reference voltage VR2 is controlled so that the average value thereof is equal to the reference voltage VR0 by feedback control using the error amplifier circuit 21a and the gm amplifier 22a described above.

Next, an example of the internal configuration of the gm amplifier 22a will be described.
As shown in FIG. 12, the gm amplifier 22a has an N-channel MOS transistor T20 and a resistor R22. That is, the gm amplifier 22a has a configuration in which the transistors T21 and T22 are omitted from the gm amplifier 22 of the first embodiment.

  The node N20a is connected to the gate of the transistor T20, and the output voltage VN20a of the error amplifier circuit 21a is supplied. The source of the transistor T20 is connected to the first terminal of the resistor R22, and the second terminal of the resistor R22 is connected to the ground. The drain of the transistor T20 is connected to the node N21a. The transistor T20 is on / off controlled by the output voltage VN20a, and the on-resistance is controlled by the output voltage VN20a. The amplifier current I20a proportional to the output voltage VN20a flows through the transistor T20. That is, the transistor T20 sucks the amplifier current I20a from the node N21a.

Next, an example of the internal configuration of the current source 23a will be described.
As shown in FIG. 13, the current source 23a includes resistors R23, R24, and R25, an operational amplifier 24, an N-channel MOS transistor T23, and P-channel MOS transistors T24 and T25. That is, the current source 23a has a configuration in which the transistors T26 and T27 are omitted from the current source 23 of the first embodiment.

  The non-inverting input terminal of the operational amplifier 24 is supplied with a voltage VN22 generated by dividing the input voltage Vi by the resistors R23 and R24. The output terminal of the operational amplifier 24 is connected to the gate of the transistor T23. The source of the transistor T23 is connected to the first terminal of the resistor R25 and the inverting input terminal of the operational amplifier 24. A current I25 corresponding to the resistance value of the resistor R25 and the potential difference (voltage VN22) between the two terminals flows between both terminals of the resistor R25.

  The transistors T24 and T25 are current mirror connected. The drain of the transistor T25 is connected to the node N21a. The current mirror circuit including these transistors T24 and T25 causes the current I21a proportional to the current I25 flowing through the transistor T24 to flow through the transistor T25 in accordance with the electrical characteristics of the transistors T24 and T25. That is, the transistor T25 discharges the current I21a to the node N21a. This current I21a is obtained from the above equation 19 when the mirror ratio of the current mirror circuit including the transistors T24 and T25 is M1.

Can be expressed as Therefore, the proportionality coefficient α of the current I21a is

It becomes. From the equation 32, the equation 17 and the equation 18, the slope value of the reference voltage VR2 and the resistance value of the resistors R23 to R25, the mirror ratio M1, and the capacitance value of the capacitor C21a shown in FIG. It can be seen that the gain Gain of the negative feedback loop can be adjusted.

According to this embodiment described above, the same effects as those of the first embodiment can be obtained.
(Other embodiments)
In addition, each said embodiment can also be implemented in the following aspects which changed this suitably.

  In the reference voltage generation circuits 20 and 20a of the above embodiments, the reference voltages VR1 and VR2 are generated so that the average value of the reference voltages VR1 and VR2 is equal to the reference voltage VR0. For example, the reference voltages VR1 and VR2 may be generated by changing the reference voltage VR0 based on the rate of change of the coil current IL. That is, the reference voltages VR1 and VR2 may be generated by adding a ripple corresponding to the ripple component of the coil current IL to the reference voltage VR0.

  In each of the above embodiments, the reference voltages VR1 and VR2 are generated by changing the reference voltage VR0 based on the rate of change of the coil current IL. For example, the first feedback voltage may be generated by changing the feedback voltage VFB (second feedback voltage) based on the rate of change of the coil current IL. That is, a ripple corresponding to the ripple component of the coil current IL may be added to the feedback voltage VFB (second feedback voltage) to generate the first feedback voltage. Specifically, the ripple component of the coil current IL is changed according to the difference current between the current generated according to the feedback voltage VFB (third current) and the current proportional to the input voltage Vi (fourth current). A corresponding ripple may be added to the feedback voltage VFB to generate the first feedback voltage. Furthermore, in this case, it is preferable to generate the first feedback voltage so that the average value of the first feedback voltage is equal to the feedback voltage VFB, as in the above embodiments. In this case, the circuit that generates the first feedback voltage is a feedback voltage generation circuit.

  In each of the embodiments and the modifications described above, the divided voltage obtained by dividing the output voltage Vo by the resistors R1 and R2 is used as the feedback voltage VFB. For example, the output voltage Vo itself may be used as the feedback voltage VFB (second feedback voltage).

  In each of the above embodiments, the output signal SG1 is supplied to the control terminals of the switch elements SW20 and SW20a of the reference voltage generation circuits 20 and 20a. However, the signals corresponding to the on period and the off period of the main-side transistor T1. If it is, it will not be restrict | limited in particular. For example, the output signal SG2 and the control signals DH and DL may be supplied to the control terminals of the switch elements SW20 and SW20a, or the voltage of the node LX between the transistors T1 and T2 is supplied to the control terminals of the switch elements SW20 and SW20a. You may make it do.

  In each of the above embodiments, the timer circuit 40 is configured to output the output signal S2 that becomes H level after the elapse of time depending on the input voltage Vi and the output voltage Vo from the rising timing of the output signal S1. The configuration of the timer circuit 40 may be changed as appropriate. For example, the timer circuit 40 may be configured to output the output signal S2 that becomes H level after a fixed time has elapsed. In addition, the timer circuit 40 may be configured to output the output signal S2 that becomes H level after a lapse of time depending on only the input voltage Vi (or only the output voltage Vo).

Alternatively, a one-shot flip-flop circuit may be provided instead of the RS-FF circuit 30 and the timer circuit 40.
In each of the above embodiments, the P-channel MOS transistor T1 is disclosed as an example of the switch circuit, but an N-channel MOS transistor may be used. A bipolar transistor may be used as the switch circuit. Alternatively, a switch circuit including a plurality of transistors may be used.

  In the above embodiments, the reference voltage VR0 may be generated outside the control circuits 3 and 3a. That is, the reference power source E1 may be provided outside the control circuits 3 and 3a.

  The feedback voltage VFB in each of the above embodiments may be generated outside the control circuits 3 and 3a. That is, the resistors R1 and R2 may be provided outside the control circuits 3 and 3a.

The transistors T1 and T2 in the above embodiments may be included in the control circuits 3 and 3a. Moreover, you may make it include the converter part 2 in the control circuits 3 and 3a.
In each of the above embodiments, the synchronous rectification type DC-DC converter is embodied, but the asynchronous rectification type DC-DC converter may be embodied.

  In each of the above embodiments, the feedback voltage VFB and the reference voltage VR1 are compared, and the embodiment is embodied as a DC-DC converter that sets the on-timing of the main-side transistor T1 according to the comparison result. For example, the feedback voltage VFB and the reference voltage VR1 may be compared and a DC-DC converter that sets the off timing of the main-side transistor T1 according to the comparison result may be used.

  FIG. 14 shows an example of an electronic device 100 including the DC-DC converter 1 (or DC-DC converter 1a). The electronic device 100 includes a main body 110 and a power supply 130 that supplies power to the main body 110.

First, an internal configuration example of the main body 110 will be described.
A central processing unit (CPU) 111 that executes a program is connected to a memory 112 that stores a program executed by the CPU 111 or data processed by the CPU 111. In addition, a keyboard 114 </ b> A and a pointing device 114 </ b> B are connected to the CPU 111 via an interface (I / F) 113. The pointing device 114B is, for example, a flat device having a mouse, a trackball, a touch panel, or an electrostatic sensor.

  In addition, a display 116 is connected to the CPU 111 via an interface 115, and a communication unit 118 is connected via an interface 117. The display 116 is, for example, a liquid crystal display or an electroluminescence panel. The communication unit 118 is, for example, a local area network board.

  Further, an external storage device 120 is connected to the CPU 111 via an interface 119, and a removable recording medium access device 122 is connected via an interface 121. The external storage device 120 is, for example, a hard disk. Examples of the removable recording medium accessed by the access device 122 include a CD (Compact Disc), a DVD (Digital Versatile Disk), and a flash memory card.

Next, an internal configuration example of the power supply unit 130 will be described.
The DC-DC converter 1 and the AC adapter 131 are connected to the main body 110 via the switch SW. Power is supplied to the main body 110 from either the DC-DC converter 1 or the AC adapter 131. In the example of FIG. 14, for example, the DC-DC converter 1 converts an input voltage Vi from the battery 132 into an output voltage Vo, and supplies the output voltage Vo to the main body 110.

  Such electronic devices include notebook personal computers, communication devices such as mobile phones, information processing devices such as personal digital assistants (PDAs), video equipment such as digital cameras and video cameras, and receivers such as television devices. Etc.

1,1a DC-DC converter (power supply)
2 Converter unit 3, 3a Control circuit 10, 11 Comparator 20, 20a Reference voltage generation circuit 21, 21a Error amplification circuit 22, 22a gm amplifier (voltage current conversion circuit)
23, 23a Current source 30 RS-FF circuit 40 Timer circuit 50 Drive circuit 100 Electronic device 110 Main body (internal circuit)
T1 P-channel MOS transistor (switch circuit)
SW20, SW20a Switch element L Coil R20, R21 Resistance (low-pass filter)
C20 capacitor (low-pass filter)
C21 capacitor

Claims (10)

A converter unit having a switch circuit to which an input voltage is supplied, and a coil connected between the switch circuit and an output terminal for outputting an output voltage;
A control circuit that switches the switch circuit at a timing according to a comparison result between a feedback voltage according to the output voltage and a reference voltage;
The control circuit includes:
The reference voltage that changes based on the rate of change of the coil current flowing through the coil is generated according to a differential current between a first current generated according to a reference voltage and a second current proportional to the input voltage. A power supply device comprising a reference voltage generation circuit.   2. The power supply device according to claim 1, wherein the reference voltage generation circuit generates the reference voltage whose voltage value fluctuates in a phase opposite to or in phase with the coil current.   The power supply apparatus according to claim 1, wherein the reference voltage generation circuit generates the reference voltage so that an average value of the reference voltages is equal to the reference voltage. The reference voltage generation circuit includes:
An error amplification circuit in which the reference voltage is input to a non-inverting input terminal;
A voltage-current conversion circuit that generates the first current according to the output voltage of the error amplifier circuit;
A current source for generating the second current;
A switching element interposed between the voltage-current conversion circuit and the current source;
A capacitor connected to a connection point between the voltage-current conversion circuit and the switch element,
The connection point is fed back to the inverting input terminal of the error amplifier circuit,
The power supply apparatus according to claim 1, wherein the switch element is switched at a timing when the switch circuit is switched.   The power supply apparatus according to claim 4, wherein the connection point is fed back to an inverting input terminal of the error amplifier circuit through a low-pass filter. A converter unit having a switch circuit to which an input voltage is supplied, and a coil connected between the switch circuit and an output terminal for outputting an output voltage;
A control circuit that switches the switch circuit at a timing according to a comparison result between the reference voltage and the first feedback voltage,
The control circuit includes:
Based on the rate of change of the coil current flowing through the coil in accordance with the difference current between the third current generated according to the second feedback voltage according to the output voltage and the fourth current proportional to the input voltage. A power supply apparatus comprising: a feedback voltage generation circuit that generates the first feedback voltage that changes.   The power supply apparatus according to claim 6, wherein the feedback voltage generation circuit generates the first feedback voltage so that an average value of the first feedback voltage is equal to the second feedback voltage. The power supply control circuit generates the output voltage from the input voltage by switching a switch circuit to which the input voltage is supplied at a timing according to a comparison result between a feedback voltage corresponding to the output voltage and a reference voltage. And
A coil connected between the switch circuit and an output terminal for outputting the output voltage according to a differential current between a first current generated according to a reference voltage and a second current proportional to the input voltage A control circuit comprising a reference voltage generation circuit that generates the reference voltage that changes based on a rate of change of a coil current flowing through the coil. An electronic device having a power supply having a control circuit and an internal circuit to which an output voltage of the power supply is supplied,
The control circuit includes:
A switch circuit to which the input voltage is supplied according to a differential current between a first current generated according to a reference voltage and a second current proportional to the input voltage of the power supply, and an output terminal that outputs the output voltage A reference voltage generation circuit that generates a reference voltage that changes based on a rate of change in the coil current flowing in the coil connected between
An electronic apparatus, wherein the switch circuit is switched at a timing according to a comparison result between a feedback voltage corresponding to the output voltage and the reference voltage. A power supply control method for generating an output voltage from the input voltage by switching a switch circuit to which an input voltage is supplied,
A coil connected between the switch circuit and an output terminal for outputting the output voltage according to a differential current between a first current generated according to a reference voltage and a second current proportional to the input voltage A reference voltage that changes based on the rate of change of the coil current flowing through
A method for controlling a power supply, comprising: switching the switch circuit at a timing according to a comparison result between a feedback voltage corresponding to the output voltage and the reference voltage.