JP2014166092A - Power supply unit, control circuit of power supply and control method of power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply unit capable of improving power conversion efficiency.SOLUTION: A DC-DC converter 1 includes a coil L1 and four switch circuits SW1-SW4 connected to the coil L1. The DC-DC converter 1 includes a first control section 20 which generates a PWM signal S3 controlling a first period in which an input terminal Pi and ground GND are connected via the coil L1 on the basis of the difference voltage between an output voltage Vo1 and an output voltage Vo2. The DC-DC converter 1 also includes a second control section 30 which generates a PWM signal S4 controlling a second period in which the input terminal Pi and an output terminal Po1 are connected via the coil L1 and a third period in which the ground GND and an output terminal Po2 are connected via the coil L1, on the basis of the difference voltage between a reference voltage Vr and a feedback voltage VFB3 that is in accordance with the potential difference between the output voltage Vo1 and the output voltage Vo2.

Description

  The present invention relates to a power supply device, a power supply control circuit, and a power supply control method.

  Electronic devices such as personal computers and mobile phones have a built-in switching power supply circuit (DC-DC converter) that supplies a drive voltage to an internal circuit that performs signal processing. The switching power supply circuit converts a DC voltage supplied from, for example, an AC adapter or a battery into a driving voltage suitable for the operation of the internal circuit. For example, the switching power supply circuit controls on / off of the main switch to boost and step down the DC input voltage to generate a DC output voltage, and feed back the DC output voltage supplied to the load to a constant target voltage. Control is in progress.

  Incidentally, in recent years, with the widespread use of portable electronic devices such as notebook personal computers and mobile phones, there is an increasing demand for miniaturization of the switching power supply circuit. Therefore, in order to meet such a demand, a single inductor multiple output (SIMO) DC-DC converter capable of obtaining a plurality of outputs with one inductor (coil) has been proposed (for example, Patent Documents 1 to 3). For example, in a power source that requires a positive power source and a negative power source such as an audio amplifier, a single inductor multi-output type DC-DC converter that can obtain a boosted output and an inverted output with one coil is used. In this type of DC-DC converter, since a single coil is shared by a plurality of outputs, an increase in the number of parts and an increase in circuit area due to an increase in the number of outputs can be suppressed.

FIG. 7 shows an example of an output unit of a single inductor multi-output type DC-DC converter 100 that can obtain a boost output and an inverted output with one coil.
A switch circuit SW11 and a switch circuit SW12 are connected in series between an input terminal Pi to which the input voltage Vin is supplied and an output terminal Po12 from which an output voltage Vout2 obtained by inverting the input voltage Vin is generated. A node between the switch circuits SW11 and SW12 is connected to the first terminal of the coil L11. The second terminal of the coil L11 is connected to the first terminal of the switch circuit SW13, and the second terminal of the switch circuit SW13 is connected to the ground GND. The second terminal of the coil L11 is connected to the first terminal of the switch circuit SW14. The second terminal of the switch circuit SW14 is connected to an output terminal Po11 that generates an output voltage Vout1 higher than the input voltage Vin. Then, an output voltage Vout1 and an output current Iout1 that are voltages across the capacitor C11 are supplied from the output terminal Po11 to the load 2A. Further, an output voltage Vout2 and an output current Iout2 that are voltages across the capacitor C12 are supplied from the output terminal Po12 to the load 3A.

Next, a control method for on / off control of the switch circuits SW11 to SW14 of the DC-DC converter 100 will be described with reference to FIG.
First, the switch circuits SW11 and SW13 are turned on, and the switch circuits SW12 and SW14 are turned off. Then, the first terminal of the coil L11 is connected to the input terminal Pi through the switch circuit SW11, and the second terminal of the coil L11 is connected to the ground GND through the switch circuit SW3. In this connected state, a coil current IL corresponding to the input voltage Vin flows in the coil L11 (see solid line arrow), and energy is accumulated in the coil L11 (see solid line arrow). As shown in FIG. 8, the coil current IL increases in proportion to the input voltage Vin in the period P11 in which the connection state is established.

  Subsequently, the switch circuits SW11 and SW13 are turned off, and the switch circuits SW12 and SW14 are turned on. Then, the first terminal of the coil L11 is connected to the output terminal Po12 through the switch circuit SW12, and the second terminal of the coil L11 is connected to the output terminal Po11 through the switch circuit SW14. In this connected state, the coil current IL is supplied to both output terminals Po1 and Po2 (see the wavy arrow in FIG. 7). At this time, since the coil current IL flows from the capacitor C12 toward the capacitor C11, the output voltage Vout1 becomes a positive power source higher than the input voltage Vin, and the output voltage Vout2 becomes a negative power source. As shown in FIG. 8, the coil current IL decreases at a predetermined slope during the period P12 when the connection state is established.

Next, another control method for on / off control of the switch circuits SW11 to SW14 of the DC-DC converter 100 will be described.
For example, the first comparison result obtained by comparing the error signal based on the difference between the output voltage Vout1 that is the boost output and the reference signal and the triangular wave, and the error signal and the triangular wave based on the difference between the output voltage Vout2 that is the inverted output and the reference signal. A second comparison result is generated. Further, a comparison result that rises or falls quickly is selected from the first comparison result and the second comparison result, and the switch circuits SW11 to SW14 are turned on / off based on the selected comparison result, and the output voltage Vout1 and the output are output. The voltage Vout2 is controlled separately.

US Patent Application Publication No. 2008/0130331 Special table 2010-536320 gazette Japanese Patent No. 4857888

  However, the above-described two control methods have a problem that the current amplitude of the coil current IL is increased, resulting in a large loss and poor power conversion efficiency. Specifically, in the former control method, the slope (decrease slope) of the coil current IL in the period P12 is − (Vout1−Vout2) / L11, and the slope is proportional to the potential difference between the output voltage Vout1 and the output voltage Vout2. Become. For this reason, for example, when the output voltage Vout1 is + 5V and the output voltage Vout2 is −5V, the coil current IL has a large inclination of −10 / L in the period P12. As a result, the ripple ΔIL of the coil current IL is increased, so that the power conversion efficiency is deteriorated. On the other hand, in the latter control method, the output selection circuit that selects one of the first comparison result and the second comparison result operates at a frequency different from the frequency of the triangular wave. The ripple ΔIL is not stable. That is, if the period for controlling the output voltage Vout1 (boost output) is T1, and the period for controlling the output voltage Vout2 (inverted output) is T2, a frequency component of 1 / (T1 + T2) appears in the coil current IL. When the coil current IL fluctuates due to such a frequency component, the peak current of the coil current IL becomes larger than necessary, and the power conversion efficiency deteriorates.

  According to an aspect of the present invention, a first switch circuit that connects a coil, a first terminal of the coil, and an input terminal to which an input voltage is supplied, a first terminal of the coil, and the input voltage A third switch circuit that connects a second switch circuit that connects a first output terminal that generates an inverted first output voltage, a second terminal of the coil, and a power supply line that is lower in potential than the input voltage. A fourth switch circuit that connects the second terminal of the coil and a second output terminal that generates a second output voltage higher than the input voltage, and the first output voltage and the second output voltage. A first control unit that generates a first control signal for controlling a first period of connecting the input terminal and the power supply line via the coil, the first output voltage, and the At least one of the second output voltages and the reference voltage And a second period in which the input terminal and the second output terminal are connected via the coil, and the power supply line and the first output terminal are connected via the coil. A second control unit that generates a second control signal for controlling the third period, and the first control signal and the second control signal have the same period.

  According to one aspect of the present invention, there is an effect that power conversion efficiency can be improved.

The block circuit diagram which shows the DC-DC converter of 1st Embodiment. The wave form diagram which shows the operation | movement of the DC-DC converter of 1st Embodiment. (A)-(c) is explanatory drawing which shows operation | movement of the DC-DC converter of 1st Embodiment. The block circuit diagram which shows the DC-DC converter of 2nd Embodiment. The circuit diagram which shows the example of an internal structure of a detection circuit. (A), (b) is a wave form diagram which shows operation | movement of a detection circuit. The block circuit diagram which shows the conventional DC-DC converter. The wave form diagram which shows the operation | movement of the conventional DC-DC converter.

(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS.
As shown in FIG. 1, the DC-DC converter 1 is a single inductor multi-output type DC-DC converter that generates a large number of output voltages Vo1, Vo2 with one inductor (coil) L1. The DC-DC converter 1 generates an output voltage Vo1 higher than the input voltage Vin and an output voltage Vo2 that is an inverted voltage of the input voltage Vin based on the input voltage Vin supplied to the input terminal Pi. It is a DC-DC converter. That is, the output voltage Vo1 is a boosted output (plus power supply), and the output voltage Vo2 is an inverted output (minus power supply). The output voltage Vo1 is supplied to the load 2 connected to the output terminal Po1, and the output voltage Vo2 is supplied to the load 3 connected to the output terminal Po2. Here, examples of the loads 2 and 3 are built in an internal circuit of a portable electronic device (personal computer, mobile phone, game device, digital camera, etc.) and other electronic devices, or a notebook personal computer. Examples include rechargeable batteries such as lithium batteries.

The DC-DC converter 1 includes a switch circuit group 10, a capacitor C 1, a capacitor C 2, and a control unit 11 that controls the switch circuit group 10.
The switch circuit group 10 includes four switch circuits SW1 to SW4 and a coil L1. For example, the switch circuit SW1 is a P-channel MOS transistor, and the switch circuit SW3 is an N-channel MOS transistor. The switch circuit SW2 always operates as a diode having the output terminal Po2 side that outputs the output voltage Vo2 as an anode, and the switch circuit SW4 always operates as a diode that has the output terminal Po1 side that outputs the output voltage Vo1 as a cathode.

  A first terminal (for example, a source terminal) of the switch circuit SW1 is connected to an input terminal Pi to which an input voltage Vin is supplied. The second terminal (for example, drain terminal) of the switch circuit SW1 is connected to the cathode of the switch circuit SW2, and the anode of the switch circuit SW2 is connected to the output terminal Po2. The output terminal Po2 is connected to the first terminal of the capacitor C2, and the second terminal of the capacitor C2 is connected to a power supply line (here, ground GND) having a potential lower than the input voltage Vin. Then, an output voltage Vo2 that is a voltage across the capacitor C2 is supplied to the load 3 from the output terminal Po2. The capacitor C2 is included in a smoothing circuit that smoothes the output voltage Vo2.

  A node N1 between the switch circuit SW1 and the switch circuit SW2 is connected to the first terminal of the coil L1. A second terminal of the coil L1 is connected to a first terminal (for example, a drain terminal) of the switch circuit SW3, and a second terminal (for example, a source terminal) of the switch circuit SW3 is connected to the ground GND. A node N2 between the coil L1 and the switch circuit SW3 is connected to the anode of the switch circuit SW4, and the cathode of the switch circuit SW4 is connected to the output terminal Po1. The output terminal Po1 is connected to the first terminal of the capacitor C1, and the second terminal of the capacitor C1 is connected to the ground GND. Then, an output voltage Vo1 that is a voltage across the capacitor C1 is supplied to the load 2 from the output terminal Po1. The capacitor C1 is included in a smoothing circuit that smoothes the output voltage Vo1.

  A control signal SG1 is supplied from the control unit 11 to a control terminal (for example, a gate terminal) of the switch circuit SW1. A control signal SG3 is supplied from the control unit 11 to a control terminal (for example, a gate terminal) of the switch circuit SW3. Switch circuits SW1 and SW3 are turned on / off in response to control signals SG1 and SG3, respectively. The output voltage Vo1 and the output current Io1 are output from the output terminal Po1 via the switch circuit SW4, and the output voltage Vo2 and the output current Io2 are output from the output terminal Po2 via the switch circuit SW2. These output terminals Po1 and Po2 are connected to the control unit 11.

The switch circuits SW1 to SW4, the coil L1, and the capacitors C1 and C2 are examples of an output unit.
The control unit 11 includes a first control unit 20, a second control unit 30, a logic circuit 40, and an oscillator 50.

  The first control unit 20 generates the PWM signal S3 based on the difference between the output voltage Vo1 and the output voltage Vo2. The first control unit 20 generates a PWM signal S3 that performs on / off control of the switch circuits SW1 and SW3 so that the difference result approaches the target value. For example, the first control unit 20 adjusts the ON time of the switch circuits SW1 and SW3 so that desired power is supplied to the loads 2 and 3 based on the difference result.

The first control unit 20 includes a feedback voltage generation circuit 21, a feedback voltage generation circuit 22, an error amplification circuit 23, and a PWM comparison circuit 24.
The feedback voltage generation circuit 21 generates a feedback voltage VFB1 corresponding to the output voltage Vo1. The feedback voltage generation circuit 21 has resistors R1 and R2. Specifically, the output terminal Po1 is connected to the first terminal of the resistor R1, and the second terminal of the resistor R1 is connected to the first terminal of the resistor R2. The second terminal of the resistor R2 is connected to the ground GND. A node N3 between the resistors R1 and R2 is connected to the inverting input terminal of the error amplifier circuit 23. Here, the resistors R1 and R2 generate a feedback voltage VFB1 obtained by dividing the output voltage Vo1 at the node N3 according to the respective resistance values. The value of the feedback voltage VFB1 corresponds to the ratio of the resistance values of the resistors R1 and R2 and the potential difference between the output voltage Vo1 and the ground GND. Therefore, the resistors R1 and R2 generate a feedback voltage VFB1 that is proportional to the output voltage Vo1. The feedback voltage VFB1 is supplied to the inverting input terminal of the error amplifier circuit 23.

  The feedback voltage generation circuit 22 generates a feedback voltage VFB2 corresponding to the output voltage Vo2. The feedback voltage generation circuit 22 has resistors R3 and R4. Specifically, the positive terminal of the reference power supply E1 is connected to the first terminal of the resistor R3, and the first terminal of the resistor R4 is connected to the second terminal of the resistor R3. The second terminal of the resistor R4 is connected to the output terminal Po2. A node N4 between the resistors R3 and R4 is connected to the non-inverting input terminal of the error amplifier circuit 23. Here, the resistors R3 and R4 generate a feedback voltage VFB2 obtained by dividing the output voltage Vo2 at the node N4 according to the respective resistance values. The value of the feedback voltage VFB2 corresponds to the ratio between the resistance values of the resistors R3 and R4 and the potential difference between the output voltage Vo2 and the reference voltage Vr generated by the reference power supply E1. The feedback voltage VFB2 is supplied to the non-inverting input terminal of the error amplifier circuit 23.

The error amplifying circuit 23 compares the feedback voltage VFB1 and the feedback voltage VFB2, and outputs an error signal S1 obtained by amplifying the difference voltage between the two voltages to the PWM comparison circuit 24.
The error signal S <b> 1 is supplied from the error amplification circuit 23 to the non-inverting input terminal of the PWM comparison circuit 24. A periodic signal CK having a predetermined period T is supplied from the oscillator 50 to the inverting input terminal of the PWM comparison circuit 24. The periodic signal CK is, for example, a sawtooth wave signal (a sawtooth waveform signal that rises from a reference value with a predetermined rising characteristic and rapidly drops to a reference value upon reset).

  The PWM comparison circuit 24 compares the error signal S1 and the periodic signal CK. The PWM comparison circuit 24 generates an L level PWM signal S3 when the level of the periodic signal CK becomes higher than the error signal S1, and when the level of the periodic signal CK becomes lower than the error signal S1, the PWM comparison circuit 24 generates an H level PWM. A signal S3 is generated. The PWM signal S3 has the same cycle as the cycle T. Then, the PWM signal S3 is supplied to the logic circuit 40.

  The second control unit 30 generates the PWM signal S4 based on the potential difference between the output voltage Vo1 and the output voltage Vo2. The second control unit 30 generates a PWM signal S4 that controls on / off of the switch circuits SW1 and SW3 so that the potential difference approaches the target value. For example, the second control unit 30 adjusts the off time of the switch circuit SW3 so that desired power is supplied to the load 2 based on the potential difference, and the desired power is supplied to the load 3. Then, the OFF time of the switch circuit SW1 is adjusted.

The second control unit 30 includes a feedback voltage generation circuit 31, an error amplification circuit 32, and a PWM comparison circuit 33.
The feedback voltage generation circuit 31 generates a feedback voltage VFB3 corresponding to the potential difference between the output voltage Vo1 and the output voltage Vo2. The feedback voltage generation circuit 31 has resistors R5 and R6. Specifically, the output terminal Po1 is connected to the first terminal of the resistor R5, and the second terminal of the resistor R5 is connected to the first terminal of the resistor R6. The second terminal of the resistor R6 is connected to the ground GND. A node N5 between the resistors R5 and R6 is connected to the inverting input terminal of the error amplifier circuit 32. Here, the resistors R5 and R6 generate a feedback voltage VFB3 obtained by dividing the potential difference between the output voltage Vo1 and the output voltage Vo2 at the node N5 according to the respective resistance values. The value of the feedback voltage VFB3 corresponds to the ratio of the resistance values of the resistors R5 and R6 and the potential difference between the output voltage Vo1 and the output voltage Vo2. The feedback voltage VFB3 is supplied to the inverting input terminal of the error amplifier circuit 32.

  A reference voltage Vr is supplied to the non-inverting input terminal of the error amplifier circuit 32. The error amplifier circuit 32 compares the feedback voltage VFB3 with the reference voltage Vr, and outputs an error signal S2 obtained by amplifying the difference voltage between the two voltages to the PWM comparator circuit 33.

  The error signal S <b> 2 is supplied from the error amplifier circuit 32 to the non-inverting input terminal of the PWM comparison circuit 33. A periodic signal CK is supplied from the oscillator 50 to the inverting input terminal of the PWM comparison circuit 33.

  The PWM comparison circuit 33 compares the error signal S2 with the periodic signal CK. The PWM comparison circuit 33 generates an L-level PWM signal S4 when the level of the periodic signal CK is higher than the error signal S2, and the H-level PWM when the level of the periodic signal CK is lower than the error signal S2. A signal S4 is generated. The PWM signal S4 has the same cycle (frequency) as the PWM signal S3, that is, has the same cycle as the cycle T. Furthermore, the PWM signal S4 is a signal synchronized with the PWM signal S3. The PWM signal S4 is supplied to the logic circuit 40.

The logic circuit 40 includes an inverter circuit 41, a NAND circuit 42, a driver circuit 43, a NOR circuit 44, and a driver circuit 45.
The inverter circuit 41 outputs an output signal obtained by logically inverting the PWM signal S3 to the NAND circuit 42. The NAND circuit 42 outputs to the driver circuit 43 an output signal S5 having a result obtained by performing a NAND operation on the output signal of the inverter circuit 41 and the PWM signal S4.

  The output terminal of the driver circuit 43 is connected to the control terminal of the switch circuit SW3. For example, the driver circuit 43 outputs an H level (for example, input voltage Vin level) control signal SG3 to the switch circuit SW3 in response to an H level (for example, input voltage Vin level) output signal S5. Further, the driver circuit 43 outputs an L level (eg, ground GND level) control signal SG3 to the switch circuit SW3 in response to an L level (eg, ground GND level) output signal S5. The switch circuit SW3 is turned on in response to the H level control signal SG3 and turned off in response to the L level control signal SG3.

The NOR circuit 44 outputs to the driver circuit 45 an output signal S6 having a result obtained by performing a NOR operation on the PWM signal S3 and the PWM signal S4.
The output terminal of the driver circuit 45 is connected to the control terminal of the switch circuit SW1. For example, the driver circuit 45 outputs a control signal SG1 of H level (for example, input voltage Vin level) to the switch circuit SW1 in response to the output signal S6 of H level (for example, input voltage Vin level). The driver circuit 45 outputs an L level (eg, ground GND level) control signal SG1 to the switch circuit SW1 in response to an L level (eg, ground GND level) output signal S6. The switch circuit SW1 is turned on in response to the L level control signal SG1, and turned off in response to the H level control signal SG1.

  In such a logic circuit 40, when an H level PWM signal S3 is input, the driver circuit 43 outputs an H level control signal SG3 regardless of the signal level of the PWM signal S4, and the driver circuit 45 outputs an L level. Control signal SG1 is output. On the other hand, in the logic circuit 40, when the PWM signal S4 is input when the PWM signal S3 is at the L level, the driver circuit 43 outputs the control signal SG3 at the L level and the driver circuit 45 outputs the L level. Control signal SG1 is output. In the logic circuit 40, when the PWM signal S3 is at the L level and the L level PWM signal S4 is input, the driver circuit 43 outputs the H level control signal SG3 and the driver circuit 45 outputs the H level. Control signal SG1 is output.

  In the present embodiment, the DC-DC converter 1 is an example of a power supply device and a power supply, the control unit 11 is an example of a control circuit, the switch circuit SW1 is an example of a first switch circuit, and the switch circuit SW2 is an example of a second switch circuit. The switch circuit SW3 is an example of a third switch circuit, and the switch circuit SW4 is an example of a fourth switch circuit. The output terminal Po1 is an example of the second output terminal, the output terminal Po2 is an example of the first output terminal, the ground GND is an example of the power supply line, the PWM signal S3 is an example of the first control signal, and the PWM signal S4 is the second control signal. For example, the feedback voltage VFB1 is an example of a second feedback voltage, the feedback voltage VFB2 is an example of a first feedback voltage, the feedback voltage VFB3 is an example of a third feedback voltage, and the error signal S1 is an example of a first error signal.

Next, the operation of the DC-DC converter 1 will be described with reference to FIGS.
When the periodic signal CK is reset to the reference value at a constant period T at time t1 shown in FIG. 2, the level of the periodic signal CK becomes lower than the error signals S1 and S2. Then, the PWM comparison circuit 24 outputs an H level PWM signal S3, and the PWM comparison circuit 33 outputs an H level PWM signal S4. In response to the H level PWM signal S3, an L level control signal SG1 and an L level control signal SG3 are generated. In response to the L level control signal SG1 and the L level control signal SG3, the switch circuits SW1 and SW3 are turned on, respectively.

  Then, as shown in FIG. 3A, the first terminal of the coil L1 is connected to the input terminal Pi through the switch circuit SW1, and the second terminal of the coil L1 is connected to the ground GND through the switch circuit SW3. That is, the input terminal Pi and the ground GND are connected via the coil L1. For this reason, a current path from the input terminal Pi to the ground GND through the coil L1 is formed. During this connection state, specifically, in the first period P1 from time t1 to time t2 in FIG. 2, the coil current IL corresponding to the input voltage Vin flows in the coil L1, and energy is accumulated in the coil L1. . In the first period P1, the coil current IL increases with a predetermined slope as time passes. Specifically, the increase slope m1 of the coil current IL in the first period P1 is defined as L1 as the inductance value of the coil L1.

It becomes. That is, the coil current IL in the first period P1 increases in proportion to the input voltage Vin.

  Next, when the level of the periodic signal CK that gradually increases with a predetermined rising characteristic from time t1 becomes higher than the error signal S1 (see time t2), the PWM signal S3 output from the PWM comparison circuit 24 changes from H level to L. Transition to level. In response to the L level PWM signal S3 and the H level PWM signal S4, an L level control signal SG1 and an L level control signal SG3 are generated. As a result, the switch circuit SW1 is turned on and the switch circuit SW3 is turned off.

  Then, as shown in FIG. 3B, the first terminal of the coil L1 is connected to the input terminal Pi through the switch circuit SW1, and the second terminal of the coil L1 is connected to the output terminal Po1 through the switch circuit SW4. That is, the input terminal Pi and the output terminal Po1 are connected via the coil L1. For this reason, a current path from the input terminal Pi to the output terminal Po1 through the coil L1 is formed. During this connection state, specifically, in the second period P2 from time t2 to time t3 in FIG. 2, the energy stored in the coil L1 in the first period P1 is released toward the output terminal Po1. An induced current flows through the coil L1. In the second period P2, the coil current IL decreases with a predetermined slope as time passes. Specifically, the decreasing slope m2 of the coil current IL in the second period P2 is

It becomes. That is, the coil current IL in the second period P2 decreases in proportion to the potential difference between the output voltage Vo1 and the input voltage Vin. When the energy is discharged, the voltage direction of the coil L1 is the same direction as the input voltage Vin. Therefore, the output voltage Vo1 boosted from the input voltage Vin is generated at the output terminal Po1.

  Subsequently, when the level of the periodic signal CK becomes higher than the error signal S2 (see time t3), the PWM signal S4 output from the PWM comparison circuit 33 changes from the H level to the L level. In response to the L level PWM signal S4 and the L level PWM signal S3, an H level control signal SG1 and an H level control signal SG3 are generated. As a result, the switch circuit SW1 is turned off and the switch circuit SW3 is turned on.

  Then, as shown in FIG. 3C, the first terminal of the coil L1 is connected to the output terminal Po2 through the switch circuit SW2, and the second terminal of the coil L1 is connected to the ground GND through the switch circuit SW3. That is, the output terminal Po2 and the ground GND are connected via the coil L1. For this reason, a current path from the output terminal Po2 to the ground GND through the coil L1 is formed. During this connection state, specifically, in the third period P3 from time t3 to time t4 in FIG. 2, the energy stored in the coil L1 in the first period P1 is directed from the output terminal Po2 to the ground GND. The induced current flows through the coil L1. In the third period P3, the coil current IL decreases with a predetermined slope as time passes. Specifically, the decreasing slope m3 of the coil current IL in the third period P3 is

It becomes. That is, the coil current IL in the third period P3 decreases in proportion to the output voltage Vo2.

  Thereafter, when the periodic signal CK is reset again to the reference value at a constant period T (see time t4), the switch circuit SW1 is turned on and the switch circuit SW3 is turned on. Thereby, the next period T is started, and in the period T, the first period P1, the second period P2, and the third period P3 are executed in this order.

  Here, an average value obtained by averaging the total amount (region A1 + A2) of the coil current IL in the second period P2 and the third period P3, that is, the period in which the energy accumulated in the coil L1 is released, in the period T is obtained. The total value Io1 + Io2 of the output currents Io1 and Io2 supplied to the loads 2 and 3 is obtained. In addition, an average value obtained by averaging the total amount of the coil current IL (see the region A1) in the period T2 in the second period P2 in which the input terminal Pi and the output terminal Po1 are connected via the coil L1 in the period T is the load 2. The output current Io1 is supplied. Then, an average value obtained by averaging the total amount of the coil current IL (see the region A2) in the third period P3 in which the output terminal Po2 and the ground GND are connected via the coil L1 in the period T is supplied to the load 3. Output current Io2.

Next, feedback control by the first control unit 20 and the second control unit 30 will be described in detail. First, feedback control by the first control unit 20 will be described.
In a series of operations in each cycle T as described above, the first control unit 20 makes the feedback voltages VFB1 and VFB2 equal based on the feedback voltages VFB1 and VFB2 generated according to the output voltages Vo1 and Vo2, respectively. As described above, the switch circuits SW1 and SW3 are turned on / off. That is, the first control unit 20 sets the time of the first period P1 during which the input terminal Pi and the ground GND are connected via the coil L1 so that the difference voltage between the feedback voltages VFB1 and VFB2 approaches 0 (zero). Control the width. In other words, in the first control unit 20, a desired current to be supplied to the loads 2 and 3 in the second period P2 and the third period P3, that is, the output current Io1 based on the potential difference between the output voltage Vo1 and the output voltage Vo2. , Io2 total value Io1 + Io2 is controlled so that the total amount of coil current IL in each period T is controlled.

  Specifically, in the series of operations in each cycle T described above, when the sum of the absolute value of the output voltage Vo1 and the absolute value of the output voltage Vo2 is higher than the target value, the error amplification circuit 23 outputs the sum. Error signal S1 decreases. Then, the H-level pulse width of the PWM signal S3 is shortened, and the first period P1 for storing energy in the coil L1 is shortened. As a result, the amount of coil current IL flowing through the coil L1 in the first period P1 decreases, and the energy accumulated in the coil L1 decreases. Accordingly, the energy released from the coil L1 decreases in the second period P2 and the third period P3. Accordingly, the amount of coil current IL supplied to the capacitor C1 and the amount of coil current IL supplied from the capacitor C2 to the ground GND are reduced, so that the total value is lowered.

  On the contrary, when the total value becomes lower than the target value, the error signal S1 output from the error amplifier circuit 23 increases. Then, the H-level pulse width of the PWM signal S3 becomes longer, and the first period P1 for storing energy in the coil L1 becomes longer. As a result, the amount of coil current IL flowing through the coil L1 in the first period P1 increases, and the energy accumulated in the coil L1 increases. Along with this, the energy released from the coil L1 increases in the second period P2 and the third period P3. Therefore, the amount of coil current IL supplied to the capacitor C1 and the amount of coil current IL supplied from the capacitor C2 to the ground GND are increased, so that the total value is increased. By such an operation, the total value is maintained at a target value (a constant value).

Next, feedback control by the second control unit 30 will be described.
In the series of operations in each cycle T, when the output voltage Vo1 becomes higher than the target voltage, the feedback voltage VFB3 becomes higher than the reference voltage Vr, and the error signal S2 output from the error amplifier circuit 32 decreases. Then, the H level pulse width of the PWM signal S4 is shortened, and the time during which the switch circuit SW3 is turned off when the switch circuit SW1 is on (second period P2) is shortened. That is, the input terminal Pi and the output terminal Po1 are connected via the coil L1, and the time during which the coil current IL is supplied to the capacitor C1 is shortened. As a result, the output voltage Vo1 is lowered. Here, assuming that the potential difference between the output voltages Vo1 and Vo2 is constant, when the output voltage Vo1 becomes higher than the target voltage, the remaining output voltage Vo2 (voltage lower than the ground GND) becomes higher than the target voltage. . At this time, when the error signal S2 decreases as described above, the pulse width of the L level of the PWM signal S4 becomes longer, and the time (the third period P3) that the switch circuit SW1 is turned off and the switch circuit SW3 is turned on becomes longer. . That is, the output terminal Po2 (capacitor C2) is connected to the ground GND through the coil L1, and the time during which the coil current IL is supplied from the output terminal Po2 (capacitor C2) to the ground GND becomes longer. As a result, the output voltage Vo2 that is the inverted voltage of the input voltage Vin is lowered.

  Also, when the output voltage Vo1 matches the target voltage, and the output voltage Vo2 lower than the ground GND becomes higher than the target voltage, the feedback voltage VFB3 becomes higher than the reference voltage Vr, and error amplification The error signal S2 output from the circuit 32 decreases. Then, the pulse width of the L level of the PWM signal S4 becomes longer, and the time (third period P3) during which the switch circuit SW1 is turned off and the switch circuit SW3 is turned on becomes longer. That is, it takes a long time for the coil current IL to be supplied from the output terminal Po2 (capacitor C2) to the ground GND. As a result, the output voltage Vo2 that is the inverted voltage of the input voltage Vin is lowered.

  Conversely, when the output voltage Vo1 becomes lower than the target voltage, the feedback voltage VFB3 becomes lower than the reference voltage Vr, and the error signal S2 output from the error amplifier circuit 32 increases. Then, the H level pulse width of the PWM signal S4 becomes longer, and the time (second period P2) during which the switch circuit SW1 is turned on and the switch circuit SW3 is turned off becomes longer. That is, the input terminal Pi and the output terminal Po1 are connected via the coil L1, and the time during which the coil current IL is supplied to the capacitor C1 becomes longer. As a result, the output voltage Vo1 increases.

  When the output voltage Vo2 lower than the ground GND becomes lower than the target voltage, the feedback voltage VFB3 becomes higher than the reference voltage Vr, and the error signal S2 output from the error amplifier circuit 32 increases. Then, the L-level pulse width of the PWM signal S4 is shortened, and the time (third period P3) in which the switch circuit SW1 is turned off and the switch circuit SW3 is turned on is shortened. That is, the time during which the coil current IL is supplied from the output terminal Po2 (capacitor C2) to the ground GND is shortened. As a result, the output voltage Vo2 that is an inverted voltage of the input voltage Vin increases.

  By such an operation, the output voltage Vo1 is maintained at a target voltage (a constant value) based on the reference voltage Vr and the resistors R5 and R6, and the output voltage Vo2 is maintained at a target voltage (a constant voltage based on the reference voltage Vr and the resistors R5 and R6). Value).

  As described above, the second control unit 30 switches the switch circuits SW1 and SW3 based on the feedback voltage VFB3 generated according to the potential difference between the output voltages Vo1 and Vo2, so that the feedback voltage VFB3 approaches the reference voltage Vr. On / off control. That is, in the second control unit 30, the time widths of the second period P2 and the third period P3 are controlled so that the potential difference between the output voltages Vo1 and Vo2 approaches the target voltage based on the reference voltage Vr and the resistors R5 and R6. Is done. In other words, the second control unit 30 has a time width necessary for supplying the coil current IL to the capacitor C1 so that the desired output current Io1 flows to the load 2 based on the potential difference between the output voltages Vo1 and Vo2. In addition to being controlled (determined), a time width necessary for supplying the coil current IL to the capacitor C2 is controlled so that a desired output current Io2 flows through the load 3. Thus, the ratio of the period during which the coil current IL is distributed to the capacitor C1 and the capacitor C2 is controlled by the feedback control by the second control unit 30.

  As described above, in the DC-DC converter 1, the first period P1, the second period P2, and the third period P3 are controlled by the two synchronized PWM signals S3 and S4 having the same frequency. Specifically, the PWM signal S3 controls (determines) the time width of the first period P1 and the total time width of the second period P2 and the third period P3. More specifically, the time width of the time for storing energy in the coil L1 (first period P1) is determined by the PWM signal S3. The remaining time obtained by removing the time width of the first period P1 determined from the period T is the time for releasing the energy accumulated in the coil L1 (second period P2 and third period P3). Used. Furthermore, the ratio of the period (second period P2 and third period P3) in which the coil current IL is distributed to the capacitor C1 and the capacitor C2 in the remaining time is controlled (determined) by the PWM signal S4. Thereby, the time width of the second period P2 for supplying the coil current IL to the capacitor C1 and the time width of the third period P3 for supplying the coil current IL to the capacitor C2 can be controlled. For this reason, even when the output current Io1 and the output current Io2 have different current values, the ratio between the second period P2 and the third period P3 in the remaining time is automatically adjusted and output. The voltages Vo1 and Vo2 are generated stably.

  The switch circuits SW1 and SW3 are controlled to be turned on / off by PWM signals S3 and S4 (control signals SG1 and SG3) having the same period (same frequency) as the period T of the periodic signal CK. For this reason, the switch circuit SW1 and the switch circuit SW3 are turned on / off at the same frequency as the PWM signals S3 and S4 (periodic signal CK). Thereby, it is possible to prevent the occurrence of a problem that a frequency component appears in the coil current IL due to the difference between the frequency of the PWM signals S3 and S4 and the switching frequency fsw of the switch circuits SW1 and SW3. Therefore, an increase in the peak current of the coil current IL due to the frequency component can be suppressed. For this reason, compared with a prior art, a loss can be reduced and conversion efficiency can be improved.

  Further, since the control signals SG1 and SG3 for controlling on / off of the switch circuits SW1 and SW3 are signals having the same cycle (same frequency), the switch circuit SW1 and the switch circuit SW3 are turned on / off at the same switching frequency fsw. The As a result, it is possible to prevent the occurrence of a problem that a frequency component appears in the coil current IL due to the different frequencies of the control signals SG1 and SG3. Therefore, an increase in the peak current of the coil current IL due to the frequency component can be suppressed. For this reason, compared with a prior art, a loss can be reduced and conversion efficiency can be improved.

  Furthermore, since the switch circuit SW1 and the switch circuit SW3 are turned on / off at the same switching frequency fsw as described above, the DC− in the current continuous mode (CCM) in which the coil current IL continuously changes in each cycle. Even when the DC converter 1 is operated, the output voltages Vo1 and Vo2 can be stably generated. That is, since it is possible to prevent the occurrence of the problem that low frequency components appear in the output voltages Vo1 and Vo2 due to the different frequencies of the control signals SG1 and SG3, the DC-DC converter 1 is controlled in the CCM region. Even in the case of operation, the output voltages Vo1 and Vo2 can be stably generated.

  From another viewpoint, when the output voltages Vo1 and Vo2 are in a steady state, the current value of the coil current IL at the start time of each cycle T (see time t1) and each cycle T are controlled by feedback control by the control unit 11. The coil current IL is controlled so as to coincide with the coil current IL at the end time (see time t4). More specifically, the increase in the coil current IL in the first period P1 is controlled to be equal to the decrease in the coil current IL in the second period P2 and the third period P3. The relationship between the increased amount and the decreased amount of the coil current IL is as follows. When the times of the first to third periods P1 to P3 are P1, P2 and P3, respectively,

It becomes. The relationship between the cycle T and the first to third periods P1 to P3 is as follows:

It becomes. And the time width of the 1st-3rd period P1-P3 is controlled by feedback control by the control part 11 so that the relationship of these Formula 4 and Formula 5 may be satisfy | filled. That is, the time width of the first period P1 is controlled by the feedback control by the first control unit 20 so that the relationship of Expression 4 and Expression 5 is satisfied. Further, the time widths of the second and third periods P2 and P3 are controlled by the feedback control by the second control unit 30 so that the relationship of Expression 4 and Expression 5 is satisfied.

According to this embodiment described above, the following effects can be obtained.
(1) A first period P1 (first period in which energy is stored in the coil L1) in which the input terminal Pi and the ground GND are connected via the coil L1, based on the difference voltage between the output voltage Vo1 and the output voltage Vo2. The time width of P1) was controlled. Thus, the total amount of the coil current IL in the predetermined period T is determined based on the difference voltage between the two output voltages Vo1 and Vo2. That is, the total amount of the coil current IL is controlled so that a desired current Io1 + Io2 supplied to the loads 2 and 3 flows based on the difference voltage between the two output voltages Vo1 and Vo2. Therefore, the cross regulation can be improved as compared with the case where the time width of the first period P1 is controlled according to only one of the output voltages Vo1 and Vo2.

  The switch circuits SW1 and SW3 are controlled to be turned on / off by PWM signals S3 and S4 (control signals SG1 and SG3) having the same period (same frequency) as the period T of the periodic signal CK. For this reason, the switch circuit SW1 and the switch circuit SW3 are turned on / off at the same frequency as the PWM signals S3 and S4 (periodic signal CK). Thereby, it is possible to prevent the occurrence of a problem that a frequency component appears in the coil current IL due to the difference between the frequency of the PWM signals S3 and S4 and the switching frequency fsw of the switch circuits SW1 and SW3. Therefore, an increase in the peak current of the coil current IL due to the frequency component can be suppressed. For this reason, compared with a prior art, a loss can be reduced and conversion efficiency can be improved.

  (3) Furthermore, the ratio between the second period P2 and the third period P3 is controlled based on the potential difference between the output voltage Vo1 and the output voltage Vo2. For this reason, the ratio of the period during which the coil current IL is distributed to the capacitors C1 and C2 is determined based on the potential difference between the two output voltages Vo1 and Vo2. Thereby, even if the number of the coils L1 is one, the two output voltages Vo1 and Vo2 can be continuously controlled within one period T. Further, since the first to third periods P1 to P3 are controlled by two synchronized PWM signals S3 and S4 having the same frequency, the current values of the output current Io1 and the output current Io2 are different. However, it can be stably operated in the CCM region.

  (4) In each period T, after energy is accumulated in the coil L1 in the first period P1, the input terminal Pi and the output terminal Po1 are connected via the coil L1 to control the output voltage Vo1 (second During the period P2), the output terminal Vo2 is connected to the ground GND via the coil L1, and the output voltage Vo2 is controlled (third period P3). Thereby, the decreasing slope of the coil current IL in the period (second period P2 and third period P3) in which the energy accumulated in the coil L1 is released can be reduced. For this reason, the ripple ΔIL of the coil current IL can be reduced as compared with the related art having the period P12 in which the output terminals Po11 and Po12 are connected to control the output voltages Vout1 and Vout2. As a result, loss can be reduced and power conversion efficiency can be improved as compared with the prior art.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. The DC-DC converter 1A of this embodiment is different from the first embodiment in that a feedback voltage generation circuit, an internal configuration of the feedback voltage generation circuit, and a detection circuit 60 are added. Hereinafter, the difference from the first embodiment will be mainly described. The same members as those shown in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description of these elements is omitted.

As shown in FIG. 4, the feedback voltage generation circuit 21A in the first controller 20 includes resistors R1, R2, and R7, and switches SS1 and SS2.
The resistor R1 has a first terminal connected to the output terminal Po1, and a second terminal connected to the first terminal of the switch SS1. The second terminal of the switch SS1 is connected to the first terminal of the resistor R2. The first terminal of the resistor R2 is connected to the first terminal of the switch SS2. The second terminal of the switch SS2 is connected to the first terminal of the resistor R7. The second terminal of the resistor R7 is connected to the plus side terminal of the reference power supply E1. The detection signal VS1 is supplied from the detection circuit 60 to the control terminal of the switch SS1 via the inverter circuit 61, and the detection signal VS1 is supplied from the detection circuit 60 to the control terminal of the switch SS2. These switches SS1 and SS2 are on / off controlled in response to the detection signal VS1. The switches SS1 and SS2 are, for example, N channel MOS transistors.

The feedback voltage generation circuit 22A has resistors R3, R4, R7 and switches SS3, SS4.
The second terminal of the resistor R3 is connected to the first terminal of the switch SS3, and the second terminal of the switch SS3 is connected to the first terminal of the resistor R4. The second terminal of the resistor R3 is connected to the first terminal of the switch SS4, and the second terminal of the switch SS4 is connected to the first terminal of the resistor R8. A second terminal of the resistor R8 is connected to the ground GND. The detection signal VS2 is supplied from the detection circuit 60 to the control terminal of the switch SS3 via the inverter circuit 62, and the detection signal VS2 is supplied to the control terminal of the switch SS4. These switches SS3 and SS4 are on / off controlled in response to the detection signal VS2. The switches SS3 and SS4 are, for example, N channel MOS transistors.

  The detection circuit 60 is supplied with the PWM signal S3 and the PWM signal S4. Based on the PWM signal S3 and the PWM signal S4, the detection circuit 60 detects whether the time width of the second period P2 is 0 s or whether the time width of the third period P3 is 0 s. To do. Based on the detection result, the detection circuit 60 generates a detection signal VS1 for on / off control of the switches SS1 and SS2 and a detection signal VS2 for on / off control of the switches SS3 and SS4.

  For example, when the detection circuit 60 detects that the time width of the second period P2 is 0 s, the detection circuit 60 generates an H level detection signal VS1 and an L level detection signal VS2. Here, when the time width of the second period P2 is 0 s, only the first period P1 and the third period P3 are executed within one period T, and the switch circuit SW3 is always turned on within one period T. It is in a state of being. Therefore, when the detection circuit 60 detects that the switch circuit SW3 is not turned off within one cycle of the PWM signals S3 and S4 (control signals SG1 and SG3), the detection circuit 60 generates the detection signal VS1 at the H level. I can say that.

  At this time, in the feedback voltage generation circuit 21A, in response to the detection signal VS1 at H level, the switch SS1 is turned off and the switch SS2 is turned on, and the output terminal Po1 is disconnected from the node N3 and the error amplification circuit 23. As a result, the output terminal Po1 is disconnected from the feedback loop of the first control unit 20 including the feedback voltage generation circuit 21A, the error amplification circuit 23, and the PWM comparison circuit 24. Since the switch SS2 is turned on, the reference power source E1 is connected to the inverting input terminal of the error amplifier circuit 23 via the resistor R7, and the feedback voltage VFB1 corresponding to the reference voltage Vr is supplied. On the other hand, in the feedback voltage generation circuit 22A, in response to the L level detection signal VS2, the switch SS3 is turned on and the switch SS4 is turned off. As a result, the feedback voltage VFB2 corresponding to the potential difference between the output voltage Vo2 and the reference voltage Vr is supplied to the non-inverting input terminal of the error amplifier circuit 23.

  In this case, the error amplifying circuit 23 and the PWM comparison circuit 24 perform on / off control of the switch circuit SW1 so that the feedback voltage VFB1 corresponding to the reference voltage Vr and the feedback voltage VFB2 corresponding to the output voltage Vo2 become equal. As a result, the output voltage Vo2 is maintained at the target voltage based on the reference voltage Vr and the resistors R3, R4, and R7. At this time, as described above, the switch circuit SW3 is maintained in the ON state.

  On the other hand, when the detection circuit 60 detects that the time width of the third period P3 is 0 s, the detection circuit 60 generates the L level detection signal VS1 and the H level detection signal VS2. Here, when the time width of the third period P3 is 0 s, the switch circuit SW1 is always on in one cycle T. Therefore, when the detection circuit 60 detects that the switch circuit SW1 is not turned off within one cycle of the PWM signals S3 and S4 (control signals SG1 and SG3), the detection circuit 60 generates the H-level detection signal VS2. I can say that.

  At this time, in the feedback voltage generation circuit 22A, in response to the H level detection signal VS2, the switch SS3 is turned off and the switch SS4 is turned on, and the output terminal Po2 is disconnected from the node N4 and the error amplification circuit 23. As a result, the output terminal Po2 is disconnected from the feedback loop of the first control unit 20 including the feedback voltage generation circuit 22A, the error amplification circuit 23, and the PWM comparison circuit 24. Since the switch SS4 is turned on, the ground GND is connected to the non-inverting input terminal of the error amplifying circuit 23 via the resistor R8, and the feedback voltage VFB2 corresponding to the ground GND potential is supplied. On the other hand, in the feedback voltage generation circuit 21A, in response to the L level detection signal VS1, the switch SS1 is turned on and the switch SS2 is turned off. As a result, the feedback voltage VFB1 corresponding to the output voltage Vo1 is supplied to the inverting input terminal of the error amplifier circuit 23.

  In this case, the error amplifying circuit 23 and the PWM comparison circuit 24 turn on and off the switch circuit SW3 so that the feedback voltage VFB1 corresponding to the output voltage Vo1 and the feedback voltage VFB2 corresponding to the ground GND potential are equal. As a result, the output voltage Vo1 is maintained at the target voltage based on the ground GND potential and the resistors R1, R2, and R8. At this time, as described above, the switch circuit SW1 is maintained in the ON state.

Next, an example of the internal configuration of the detection circuit 60 will be described.
As shown in FIG. 5, the detection circuit 60 includes inverter circuits 61 and 62, an OR circuit 63, and D-flip flip circuits (D-FF circuits) 64 to 67.

  The inverter circuit 61 supplies a signal obtained by logically inverting the PWM signal S3 to the clock terminals of the D-FF circuits 64-67. The inverter circuit 62 outputs a signal obtained by logically inverting the PWM signal S4 to the OR circuit 63. The OR circuit 63 supplies an output signal having a result obtained by performing an OR operation between the output signal of the inverter circuit 62 and the PWM signal S3 to the reset terminal R of the D-FF circuit 64.

  A high potential power supply voltage VDD generated by a power supply circuit (not shown) is supplied to the input terminal D of the D-FF circuit 64. The output signal Q1 is output from the output terminal Q of the D-FF circuit 64 to the input terminal D of the D-FF circuit 65 in the next stage. The detection signal VS1 is output from the output terminal Q of the D-FF circuit 65.

  Such D-FF circuits 64 and 65, inverter circuits 61 and 62, and OR circuit 63 detect the H level when the switch circuit SW3 is detected not to be turned off within one cycle of the PWM signals S3 and S4. It functions as a first detection circuit that generates VS1.

  The high potential power supply voltage VDD is supplied to the input terminal D of the D-FF circuit 66. The PWM signal S4 is supplied to the reset terminal R of the D-FF circuit 66. The output signal Q2 is output from the output terminal Q of the D-FF circuit 66 to the input terminal D of the D-FF circuit 67 at the next stage. The detection signal VS2 is output from the output terminal Q of the D-FF circuit 67.

  The D-FF circuits 66 and 67 and the inverter circuit 61 generate a second detection signal VS2 when detecting that the switch circuit SW1 is not turned off within one cycle of the PWM signals S3 and S4. Functions as a detection circuit.

In the present embodiment, the DC-DC converter 1A is an example of a power supply device and a power supply, the detection signal VS1 is an example of a first detection signal, and the detection signal VS2 is an example of a second detection signal.
Next, the operation of the detection circuit 60 will be described. First, the operation of the detection circuit 60 when the third period P3 becomes 0 s will be described.

  When a period in which the PWM signal S4 is at the L level occurs within one period T of the PWM signals S3 and S4 as in the period Ta shown in FIG. 6A, D is generated by the L level PWM signal S4. The FF circuit 66 is reset and the output signal Q1 becomes L level (see time t10). For this reason, the D-FF circuit 67 outputs an L level detection signal VS2. In response to the L level detection signal VS1, the switch SS3 is turned on and the switch SS4 is turned off.

  On the other hand, when the period during which the PWM signal S4 is at the L level does not occur within one cycle T of the PWM signals S3 and S4 as in the period Tb, that is, when the third period P3 becomes 0 s, Within the period T, the D-FF circuit 66 is not reset. More specifically, the output signal Q2 of the D-FF circuit 66 becomes H level in response to the falling edge of the PWM signal S3 (see time t11). Thereafter, since the PWM signal S4 does not transit to the L level, the output signal Q2 that has become the H level does not transit to the L level, and the H level output signal Q2 is input to the D-FF circuit 67 in the next cycle T. Supplied to terminal D. Then, in response to the falling edge of the PWM signal S3 of the next period T, the D-FF circuit 67 outputs an H level detection signal VS2 (see time t12). In response to the H level detection signal VS2, the switch SS3 is turned off and the switch SS4 is turned on.

Next, the operation of the detection circuit 60 when the second period P2 becomes 0 s will be described.
In the period Tc of the PWM signals S3 and S4 as in the period Tc shown in FIG. 6B, when the H level pulse of the PWM signal S4 is generated during the period in which the PWM signal S3 is L level, The D-FF circuit 64 is reset by the L level output signal output from the OR circuit 63 (see time t20). Therefore, an L level output signal Q1 is output from the D-FF circuit 64, and an L level detection signal VS1 is output from the D-FF circuit 65. In response to the L level detection signal VS1, the switch SS1 is turned on and the switch SS2 is turned off.

  On the other hand, as in the period Td, in the period Td of the PWM signals S3 and S4, when the PWM signal S3 is at the L level and the H level pulse of the PWM signal S4 is not generated, that is, the second period P2 is When 0 s is reached, the D-FF circuit 64 is not reset within the period T. More specifically, the output signal Q1 of the D-FF circuit 66 becomes H level in response to the falling edge of the PWM signal S3. Thereafter, since a period in which the PWM signal S3 is at the L level and the PWM signal S4 is at the H level does not occur, the output signal of the OR circuit 63 does not transition to the L level. Therefore, the H level output signal Q1 is supplied to the input terminal D of the D-FF circuit 65 in the next cycle T without the output signal Q1 having the H level transitioning to the L level. In response to the falling edge of the PWM signal S3 of the next period T, the D-FF circuit 65 outputs an H level detection signal VS1. In response to the H level detection signal VS1, the switch SS1 is turned off and the switch SS2 is turned on.

Next, the operation of the DC-DC converter 1A when the load 2 changes suddenly and becomes no load will be described.
When the load 2 changes suddenly and becomes no load, the output voltage Vo1 increases rapidly, and the output voltage Vo1 becomes higher than the target voltage (overshoots). When the second period P2 becomes 0 s as described above after the sudden change of the load 2, this is detected by the detection circuit 60 and the detection signal VS1 of the H level and the detection signal VS2 of the L level are output from the detection circuit 60. The In response to these detection signals VS1 and VS2, the switches SS1 and SS4 are turned off and the switches SS2 and SS3 are turned on. As a result, the output terminal Po1 that generates the output voltage Vo1 overshooted as described above is disconnected from the error amplifier circuit 23. Therefore, the first control unit 20 performs feedback control according to only the output voltage Vo2 out of the output voltage Vo1 and the output voltage Vo2. For this reason, even when the load 2 suddenly changes and becomes no load and the output voltage Vo1 overshoots, the influence of the output voltage Vo1 on the output voltage Vo2 can be reduced. That is, it is possible to suitably suppress the output voltage Vo2 from overshooting or undershooting with the overshoot of the output voltage Vo1. The output voltage Vo2 can be stabilized at the target voltage by the feedback control by the first control unit 20.

  Although detailed description is omitted here, when the third period P3 becomes 0 s due to a sudden change in the load 3, the output terminal Po2 is disconnected from the error amplifying circuit 23 so that the output voltage Vo1 is set to the target voltage. Can be stabilized.

According to the embodiment described above, the following effects are obtained in addition to the effects (1) to (4) of the first embodiment.
(5) When the second period P2 is detected to be 0 s, the H level detection signal VS1 is generated and the output terminal Po1 is disconnected from the error amplifier circuit 23. Further, when it is detected that the third period P3 becomes 0 s, an H level detection signal VS2 is generated, and the output terminal Po2 is disconnected from the error amplifier circuit 23. Accordingly, even when one output voltage overshoots or undershoots due to a sudden load change or the like, it is possible to suppress the other output voltage from undershooting or overshooting accordingly. That is, voltage fluctuations of the output voltages Vo1 and Vo2 at the time of sudden load change can be improved.

(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
In each of the above embodiments, in each cycle T, the first period P1, the second period P2, and the third period P3 are executed in this order. For example, in each cycle T, the first period P1, the third period P3, and the second period P2 may be executed in this order.

  In each of the above embodiments, the ratio between the second period P2 and the third period P3 is controlled based on the potential difference between the output voltage Vo1 and the output voltage Vo2. For example, the ratio between the second period P2 and the third period P3 may be controlled based only on the output voltage Vo1 of the output voltages Vo1 and Vo2. In this case, for example, in the period T, the first control unit 20 determines the time width of the first period P1, and based on the output voltage Vo1, the first output current Io1 flows through the load 2 so as to flow. The time width of the second period P2 is determined. Then, the remaining time obtained by removing the determined time width from the period T is allocated to the third period P3. Alternatively, the ratio between the second period P2 and the third period P3 may be controlled based only on the output voltage Vo2 of the output voltages Vo1 and Vo2. In this case, for example, in the period T, the first control unit 20 determines the time width of the first period P1 and, based on the output voltage Vo2, the first output current Io2 flows through the load 3. The time width of the third period P3 is determined. Then, the remaining time obtained by excluding the determined time width from the period T is allocated to the second period P2.

  In each of the above embodiments, a P-channel MOS transistor is disclosed as an example of the switch circuit SW1, but an N-channel MOS transistor may be used. Further, a bipolar transistor may be used as the switch circuit SW1. Alternatively, a switch circuit including a plurality of transistors may be used as the switch circuit SW1.

  In each of the above embodiments, an N-channel MOS transistor is disclosed as an example of the switch circuit SW3. However, a P-channel MOS transistor may be used. A bipolar transistor may be used as the switch circuit SW2. Alternatively, a switch circuit including a plurality of transistors may be used as the switch circuit SW2.

-The internal structure of the control part 11 (1st control part 20, the 2nd control part 30, and the logic circuit 40) in said each embodiment is not specifically limited.
In the above embodiments, the oscillator 50 generates the periodic signal CK that is a sawtooth wave signal. Not limited to this, the oscillator 50 may generate a triangular wave signal.

In each of the above embodiments, the voltage control mode DC-DC converter is embodied. However, the current control mode DC-DC converter may be embodied.
In each of the above embodiments and each of the modifications, the PWM control type DC-DC converter is embodied. However, a PFM (Pulse Frequency Modulation) control type DC-DC converter or a PSM (Pulse Skipping Modulation) control type DC is used. -It may be embodied in a DC converter. However, even in this case, it is preferable that the control signal for on / off control of the switch circuit SW1 and the control signal for on / off control of the switch circuit SW3 are signals having the same cycle.

DESCRIPTION OF SYMBOLS 1,1A DC-DC converter 11 Control part 20 1st control part 21, 22, 21A, 22A Feedback voltage generation circuit 23 Error amplification circuit 24 PWM comparison circuit 30 2nd control part 31 Feedback voltage generation circuit 32 Error amplification circuit 33 PWM Comparison circuit 40 Logic circuit 50 Oscillator 60 Detection circuit 61, 62 Inverter circuit 63 OR circuit 64-67 D-FF circuit L1 Coil SW1-SW4 Switch circuit Pi input terminal Po1, Po2 Output terminal

Claims (9)

Coils,
A first switch circuit connecting a first terminal of the coil and an input terminal to which an input voltage is supplied;
A second switch circuit connecting the first terminal of the coil and a first output terminal that generates a first output voltage obtained by inverting the input voltage;
A third switch circuit for connecting the second terminal of the coil and a power supply line having a potential lower than the input voltage;
A fourth switch circuit connecting the second terminal of the coil and a second output terminal that generates a second output voltage higher than the input voltage;
Generating a first control signal for controlling a first period of connecting the input terminal and the power line via the coil based on a voltage difference between the first output voltage and the second output voltage; 1 control unit;
A second period for connecting the input terminal and the second output terminal via the coil based on a differential voltage between at least one of the first output voltage and the second output voltage and a reference voltage; A second control unit for generating a second control signal for controlling a third period for connecting the power supply line and the first output terminal via the coil;
The power supply apparatus according to claim 1, wherein the first control signal and the second control signal have the same period.   The power supply apparatus according to claim 1, wherein the first control signal is a signal synchronized with the second control signal.   The first controller generates an error signal according to a difference voltage between a first feedback voltage corresponding to the first output voltage and a second feedback voltage corresponding to the second output voltage. The power supply device according to claim 1, further comprising: A first detection circuit that generates a first detection signal when it is detected that the third switch circuit is not turned off within one cycle of the first control signal;
4. The power supply device according to claim 3, wherein the first control unit disconnects the second output terminal from the error amplifier circuit in response to the first detection signal. 5. A second detection circuit that generates a second detection signal when it is detected that the first switch circuit is not turned off within one cycle of the first control signal;
5. The power supply device according to claim 3, wherein the first control unit disconnects the first output terminal from the error amplification circuit in response to the second detection signal. 6.   The second controller is configured to control the second error signal based on a second error signal corresponding to a difference voltage between a third feedback voltage corresponding to the potential difference between the first output voltage and the second output voltage and the reference voltage. 6. The power supply device according to claim 1, wherein the second control signal for controlling a ratio between the period and the third period is generated. 7. The second switch circuit is a diode having a cathode connected to the first terminal of the coil and an anode connected to the first output terminal;
The fourth switch circuit is a diode having an anode connected to the first terminal of the coil and a cathode connected to the second output terminal;
The power supply apparatus according to claim 1, wherein the first control unit and the second control unit perform on / off control of the first switch circuit and the third switch circuit. . A first switch circuit connecting a coil, a first terminal of the coil and an input terminal to which an input voltage is supplied, and a first output voltage generated by inverting the first terminal of the coil and the input voltage. A second switch circuit that connects one output terminal, a third switch circuit that connects a second terminal of the coil and a power line lower in potential than the input voltage, a second terminal of the coil, and the input voltage A power supply control circuit comprising: a fourth switch circuit connecting a second output terminal that generates a higher second output voltage;
Generating a first control signal for controlling a first period of connecting the input terminal and the power line via the coil based on a voltage difference between the first output voltage and the second output voltage; 1 control unit;
A second period for connecting the input terminal and the second output terminal via the coil based on a differential voltage between at least one of the first output voltage and the second output voltage and a reference voltage; A second control unit for generating a second control signal for controlling a third period for connecting the power supply line and the first output terminal via the coil;
The power supply control circuit, wherein the first control signal and the second control signal have the same cycle. A first switch circuit connecting a coil, a first terminal of the coil and an input terminal to which an input voltage is supplied, and a first output voltage generated by inverting the first terminal of the coil and the input voltage. A second switch circuit that connects one output terminal, a third switch circuit that connects a second terminal of the coil and a power line lower in potential than the input voltage, a second terminal of the coil, and the input voltage A fourth switch circuit that connects a second output terminal that generates a higher second output voltage, and a method for controlling a power supply,
Based on a difference voltage between the first output voltage and the second output voltage, a first control signal for controlling a first period for connecting the input terminal and the power supply line via the coil is generated.
Based on a difference voltage between at least one of the first output voltage and the second output voltage and a reference voltage, the input terminal has the same period as the first control signal, and the input terminal Generating a second control signal for controlling a second period for connecting the second output terminal and a third period for connecting the power supply line and the first output terminal via the coil; Power supply control method.