JP5605177B2 - Control circuit, electronic device and power supply control method - Google Patents

Description

  The present invention relates to a control circuit, an electronic device, and a power supply control method.

  In an electronic device or the like, a switching power supply is used to supply power to a load, and for example, a DC-DC converter that converts a DC voltage into another DC voltage is used. Conventionally, various control methods have been proposed for DC-DC converters (see, for example, Patent Documents 1 to 4).

FIG. 22 shows an example of a conventional DC-DC converter.
The comparator 70 in the control circuit 6 compares the output voltage Vo and the reference voltage VR11, and outputs an output signal S11 having a level corresponding to the comparison result to the set terminal S of the RS-flip flop (RS-FF) circuit 71. Output. The oscillator 72 outputs a clock signal CLK having a constant frequency to the reset terminal R of the RS-FF circuit 71.

  The RS-FF circuit 71 enters a reset state in response to the H level clock signal CLK and outputs the L level control signal S12 and the H level control signal S13. Then, the drive circuit 73 outputs the H level control signals DH and DL to turn off the transistor T11 and turn on the transistor T12. At this time, the switch SW11 is turned on in response to the H-level control signal S13 output from the RS-FF circuit 71. Then, since the capacitor C12 is charged according to the current I11 supplied from the current source 74, the reference voltage VR11 increases from the reference voltage VR0 with a fixed slope (= I11 / C12).

  When the reference voltage VR11 becomes higher than the output voltage Vo, the comparator 70 outputs an H level signal S11. In response to the H level signal S11, the RS-FF circuit 71 enters a set state and outputs an H level control signal S12 and an L level control signal S13. Then, the drive circuit 73 outputs L level control signals DH and DL to turn on the transistor T11 of the converter unit 5 and turn off the transistor T12.

  In such a DC-DC converter 4, the output voltage Vo output from the output terminal Po is

という基準電圧ＶＲ０に応じた目標電圧に維持される。なお、Ｔｏｆｆは、トランジスタＴ１１がオフしているオフ時間である。

The target voltage corresponding to the reference voltage VR0 is maintained. Toff is an off time during which the transistor T11 is off.

JP 2010-63333 A JP 2008-228461 A JP-A-11-332222 JP 2008-160905 A

  However, in the DC-DC converter 4, when the input voltage Vi or the load varies, the switching duty of the transistor T11 varies. Here, as is apparent from the above equation (1), the output voltage Vo depends on the OFF time Toff of the transistor T11. For this reason, for example, when the off time Toff becomes longer as the input voltage Vi increases, the output voltage Vo increases as the off time Toff varies. In addition, when the output current Io increases due to load fluctuations, the off-time Toff decreases as the loss due to the output current Io increases, so the output voltage Vo decreases. As described above, the DC-DC converter 4 has a problem that the line regulation and the load regulation are poor because the output voltage Vo fluctuates with the change of the duty according to the fluctuation of the input voltage Vi and the output current Io.

According to one aspect of the present invention, a switching control unit that switches a switch circuit to which an input voltage of a power supply is supplied according to a comparison result between a first feedback voltage corresponding to an output voltage of the power supply and a first reference voltage. When the amplifier for generating a current corresponding to the difference between the second feedback voltage and a second reference voltage corresponding to the output voltage, by changing the second feedback voltage at a rate of change corresponding to the integral of the current A first additional circuit for generating the first feedback voltage or generating the first reference voltage by changing the second reference voltage at the rate of change; and the first feedback voltage or the first reference voltage. A timing adjustment circuit that adjusts a start timing to be changed at the change rate to a timing delayed by a predetermined time from the switching timing of the switch circuit .

  According to one aspect of the present invention, there is an effect that fluctuations in output voltage can be suppressed.

The block circuit diagram which shows the DC-DC converter of 1st Embodiment. The timing chart which shows operation | movement of the DC-DC converter of 1st Embodiment. (A)-(c) is a timing chart for demonstrating operation | movement of the DC-DC converter of 1st Embodiment. The block circuit diagram which shows the DC-DC converter of 2nd Embodiment. The circuit diagram which shows the internal structural example of the delay circuit of 2nd Embodiment. (A), (b) is a timing chart for demonstrating operation | movement of the DC-DC converter of 2nd Embodiment. The block circuit diagram which shows the DC-DC converter of 3rd Embodiment. The circuit diagram which shows the internal structural example of the delay circuit of 3rd Embodiment. The timing chart which shows the operation | movement of the DC-DC converter of 3rd Embodiment. (A), (b) is a timing chart for demonstrating operation | movement of the DC-DC converter of 3rd Embodiment. (A), (b) is a characteristic view which shows the frequency characteristic of the DC-DC converter of 3rd Embodiment. The block circuit diagram which shows the DC-DC converter of 4th Embodiment. The circuit diagram which shows the internal structural example of an offset voltage generation circuit. The circuit diagram which shows the internal structural example of a current source. The timing chart which shows the operation | movement of the DC-DC converter of 4th Embodiment. The block circuit diagram which shows the DC-DC converter of a modification. The circuit diagram which shows the internal structural example of the comparator of a modification. The circuit diagram which shows the internal structural example of the comparator of a modification. The block circuit diagram which shows the DC-DC converter of a modification. The block circuit diagram which shows the DC-DC converter of a modification. 1 is a schematic configuration diagram illustrating an electronic device. The block circuit diagram which shows the conventional DC-DC converter.

(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS.
As shown in FIG. 1, the DC-DC converter 1 includes a converter unit 2 that generates an output voltage Vo lower than the input voltage Vi based on the input voltage Vi, and a control circuit 3 that controls the converter unit 2. Have.

First, an internal configuration example of the converter unit 2 will be described.
A main-side transistor T1 and a synchronization-side transistor T2 are connected in series between an input terminal Pi to which an input voltage Vi is supplied and a power supply line (here, ground) having a potential lower than the input voltage Vi. Has been. The main transistor T1 is a P-channel MOS transistor, and the synchronous transistor T2 is an N-channel MOS transistor.

  The transistor T1 has a first terminal (source) connected to the input terminal Pi and a second terminal (drain) connected to the first terminal (drain) of the transistor T2. The second terminal (source) of the transistor T2 is connected to the ground.

  The control signal DH is supplied from the control circuit 3 to the control terminal (gate) of the transistor T1, whereas the control signal DL is supplied from the control circuit 3 to the control terminal (gate) of the transistor T2. These transistors T1 and T2 are complementarily turned on and off in response to the control signals DH and DL. The transistor T1 is an example of a switch circuit.

  A node N1 between the transistors T1 and T2 is connected to the first terminal of the coil L1. The second terminal of the coil L1 is connected to the output terminal Po that outputs the output voltage Vo. Thus, the main-side transistor T1 and the coil L1 are connected in series between the input terminal Pi and the output terminal Po. The second terminal of the coil L1 is connected to the first terminal of the smoothing capacitor C1, and the second terminal of the capacitor C1 is connected to the ground. The smoothing capacitor C1 is included in a smoothing circuit that smoothes the output voltage Vo. The resistance connected in series to the coil L1 is an equalized DC resistance DCR included in the coil L1, and the resistance connected in series to the capacitor C1 is an equivalent series resistance ESR included in the capacitor C1.

  In such a converter unit 2, when the main transistor T1 is turned on and the synchronous transistor T2 is turned off, a coil current IL corresponding to the potential difference between the input voltage Vi and the output voltage Vo flows through the coil L1. Thereby, energy is accumulated in the coil L1. When the main transistor T1 is turned off and the synchronous transistor T2 is turned on, the energy stored in the coil L1 is released, so that an induced current (coil current IL) flows through the coil L1. By such an operation, an output voltage Vo that is stepped down from the input voltage Vi is generated. The output voltage Vo is supplied to a load (not shown) connected to the output terminal Po. An output current Io is also supplied to the load.

The control circuit 3 adjusts the pulse widths of the control signals DH and DL based on the output voltage Vo fed back from the converter unit 2. Next, an internal configuration example of the control circuit 3 will be described.
The reference voltage generation circuit 10 is supplied with the output voltage Vo from the converter unit 2. The reference voltage generation circuit 10 generates a reference voltage VR1 having a predetermined slope according to the output voltage Vo. Specifically, the reference voltage generation circuit 10 adds an offset to the reference voltage VR0 set according to the target value of the output voltage Vo and responds to the potential difference between the output voltage Vo and the reference voltage VR0. A reference voltage VR1 is generated by adding a slope. In the present embodiment, the slope is added during the off period in which the transistor T1 is off. The reference voltage VR1 is supplied to the non-inverting input terminal of the comparator 20.

The output voltage Vo is supplied to the inverting input terminal of the comparator 20. The comparator 20 generates a signal S1 corresponding to the comparison result between the output voltage Vo and the reference voltage VR1.
The RS-FF circuit 21 has the set terminal S connected to the output terminal of the comparator 20 and the reset terminal R connected to the oscillator 22. The oscillator 22 generates a clock signal CLK having a predetermined frequency (for example, a signal having a pulse signal generated at a constant period). The RS-FF circuit 21 outputs an H level control signal S2 from the output terminal Q in response to the H level signal S1 supplied to the set terminal S, and also outputs an L level control signal from the inverting output terminal XQ. S3 is output. In response to the H level clock signal CLK supplied to the reset terminal R, the RS-FF circuit 21 outputs the L level control signal S2 and the H level control signal S3. That is, for the RS-FF circuit 21, the H level signal S1 is a set signal, and the H level clock signal CLK is a reset signal. The control signal S2 output from the RS-FF circuit 21 is supplied to the drive circuit 23, and the control signal S3 is supplied to the reference voltage generation circuit 10 and the drive circuit 23.

  Based on the control signals S2 and S3 input from the RS-FF circuit 21, the drive circuit 23 generates control signals DH and DL that complementarily turn on and off the transistors T1 and T2 of the converter unit 2. In the drive circuit 23, a dead time may be set in the control signals DH and DL so that both transistors T1 and T2 are not turned on simultaneously.

  Note that the comparator 20, the RS-FF circuit 21, the oscillator 22, and the drive circuit 23 in this embodiment are examples of a switching control unit. The output voltage Vo in the present embodiment is an example of the first feedback voltage and the second feedback voltage, the reference voltage VR1 is an example of the first reference voltage, and the reference voltage VR0 is an example of the second reference voltage.

Next, an internal configuration example of the reference voltage generation circuit 10 that generates the reference voltage VR1 will be described.
An output voltage Vo is supplied to the inverting input terminal of the transconductance amplifier (gm amplifier) 11. A reference voltage VR0 generated by the first power supply E1 is supplied to the non-inverting input terminal of the gm amplifier 11.

  The gm amplifier 11 generates an amplifier current Ia corresponding to the potential difference between the output voltage Vo and the reference voltage VR0. Specifically, when the mutual conductance (current conversion gain) of the gm amplifier 11 is gm, the amplifier current Ia generated by the gm amplifier 11 is

と表わすことができる。すなわち、基準電圧ＶＲ０よりも出力電圧Ｖｏが高くなるほど、アンプ電流Ｉａが小さくなる一方、基準電圧ＶＲ０よりも出力電圧Ｖｏが低くなるほど、アンプ電流Ｉａが大きくなる。なお、本実施形態では、ｇｍアンプ１１の電流変換利得ｇｍは高利得に設定されている。

Can be expressed as That is, as the output voltage Vo becomes higher than the reference voltage VR0, the amplifier current Ia decreases. On the other hand, as the output voltage Vo becomes lower than the reference voltage VR0, the amplifier current Ia increases. In the present embodiment, the current conversion gain gm of the gm amplifier 11 is set to a high gain.

  The output terminal of the gm amplifier 11 is connected to the first terminal of the capacitor C2. The second terminal of the capacitor C2 is connected to the negative terminal of the second power supply E2 that generates the offset voltage Voff. The positive terminal of the second power source E2 is connected to the positive terminal of the first power source E1. Therefore, the voltage VN2 of the second terminal (node N2) of the capacitor C2 is

と表わすことができる。すなわち、電圧ＶＮ２は、基準電圧ＶＲＯに対して、オフセット電圧Ｖｏｆｆが付加（減算）された電圧である。

Can be expressed as That is, the voltage VN2 is a voltage obtained by adding (subtracting) the offset voltage Voff to the reference voltage VRO.

  A node N3 between the gm amplifier 11 and the capacitor C2 is connected to the first terminal of the switch SW1. The second terminal of the switch SW1 is connected to the node N2. That is, the switch SW1 is connected in parallel with the capacitor C2. The capacitor C2 and the switch SW1 change the voltage VN2 of the node N2 at a rate of change corresponding to the integration of the amplifier current Ia to generate the reference voltage VR1.

  More specifically, the control signal S3 output from the inverted output terminal XQ of the RS-FF circuit 21 is supplied to the control terminal of the switch SW1. The switch SW1 is turned off when the control signal S3 is at the H level, and is turned on when the control signal S3 is at the L level. When the switch SW1 is turned off, the capacitor C2 is charged by the amplifier current Ia supplied from the gm amplifier 11. As a result, the voltage at the first terminal of the capacitor C2 rises from the voltage VN2 at the second terminal (node N2) of the capacitor C2 with a slope (= Ia / C2) corresponding to the amplifier current Ia. That is, the voltage at the first terminal of the capacitor C2 rises at a slope (rate of change corresponding to the integration of the amplifier current Ia) controlled such that the output voltage Vo is equal to the reference voltage VR0. The voltage at the first terminal of the capacitor C2 is supplied to the non-inverting input terminal of the comparator 20 as the reference voltage VR1.

  Thus, the reference voltage VR1 is a voltage obtained by adding a slope (charge voltage of the capacitor C2) according to the amplifier current Ia to the voltage VN2 obtained by adding the offset voltage Voff to the reference voltage VR0. Here, the offset voltage Voff is a voltage for generating a potential difference between the output voltage Vo compared with the comparator 20 and the reference voltage VR1 (voltage VN2) when the slope is added. . Specifically, the offset voltage Voff is a reference when the slope is added so that the slope whose slope is controlled so that the output voltage Vo becomes equal to the reference voltage VR0 is surely added to the reference voltage VR1. This is a voltage for offsetting the voltage VR1 from the reference voltage VR0. Further, the offset voltage Voff is set to a voltage higher than the ripple component of the smoothing capacitor C1.

  The gm amplifier 11 is an example of an amplifier, the capacitor C2 and the switch SW1 are examples of a first additional circuit, and the second power source E2 is an example of a second additional circuit. The amplifier current Ia is an example of an amplifier current, and the offset voltage Voff is an example of an offset.

  Next, the operation of the control circuit 3 configured as described above will be described with reference to FIG. In FIG. 2, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.

  When the reference voltage VR1 becomes higher than the output voltage Vo (time t1), the comparator 20 outputs an H level signal S1. In response to the H level signal S1, the RS-FF circuit 21 outputs an H level control signal S2 and an L level control signal S3. The drive circuit 23 generates L level control signals DH and DL in response to the H level control signal S2 and the L level control signal S3. Then, the main-side transistor T1 is turned on in response to the L-level control signal DH, and the synchronous-side transistor T2 is turned off in response to the L-level control signal DL. As described above, when the reference voltage VR1 crosses the output voltage Vo, the control circuit 3 generates the H-level control signal DH for turning on the main-side transistor T1. In other words, the on-timing of the transistor T1 is set according to the comparison result between the output voltage Vo and the reference voltage VR1. In the following description, the time during which the main-side transistor T1 is on is referred to as an on-time Ton (see times t1 to t2).

  As described above, when the L-level control signal S3 is output from the RS-FF circuit 21 (time t1), the switch SW1 in the reference voltage generation circuit 10 is turned on. Then, both terminals of the capacitor C2 are short-circuited. As a result, the electric charge stored in the capacitor C2 is discharged, and the voltage at the first terminal (node N3) of the capacitor C2, that is, the reference voltage VR1 is reset to the voltage VN2 at the node N2. For this reason, the reference voltage VR1 during the ON period of the transistor T1 is at a constant level equal to the voltage VN2 (time t1 to t2).

  Subsequently, an H level clock signal CLK is output from the oscillator 22 at a constant cycle (time t2). In response to the H level clock signal CLK, the RS-FF circuit 21 outputs an L level control signal S2 and an H level control signal S3. The drive circuit 23 generates H-level control signals DH and DL in response to the L-level control signal S2 and the H-level control signal S3. Then, the main transistor T1 is turned off in response to the H level control signal DH, and the synchronous transistor T2 is turned on in response to the H level control signal S3. In this way, the control circuit 3 generates the L-level control signal DH for turning off the main-side transistor T1 at regular intervals. In the following description, the time during which the main-side transistor T1 is off is referred to as off-time Toff (see times t2 to t3).

  Further, as described above, when the H-level control signal S3 is output from the RS-FF circuit 21 (time t2), the switch SW1 in the reference voltage generation circuit 10 is turned off. Then, the capacitor C2 is charged by the amplifier current Ia supplied from the gm amplifier 11. As a result, as shown at times t2 to t3, the reference voltage VR1 rises at a slope (= Ia / C2) corresponding to the amplifier current Ia during the off period of the transistor T1. Specifically, a voltage that rises at a slope corresponding to the amplifier current Ia during the off period is added to the voltage VN2 of the node N2, and the added voltage is supplied to the comparator 20 as the reference voltage VR1. Therefore, when the voltage added to the voltage VN2 of the node N2 is the slope voltage Vs, the reference voltage VR1 is

と表わすことができる。すなわち、参照電圧ＶＲ１は、基準電圧ＶＲ０からオフセット電圧Ｖｏｆｆが減算された電圧ＶＮ２に対して、アンプ電流Ｉａに応じたスロープを持つスロープ電圧Ｖｓが付加されて生成される。この参照電圧ＶＲ１は、上記式（４）から明らかなように、ｇｍアンプ１１にて生成されるアンプ電流Ｉａの増減に応じてそのスロープの傾斜が変動する。具体的には、図２に示すように、アンプ電流Ｉａが大きくなるほど、参照電圧ＶＲ１のスロープの傾斜が急峻（変化量が大）になる一方、アンプ電流Ｉａが小さくなるほど、参照電圧ＶＲ１のスロープの傾斜が緩やか（変化量が小）になる。

Can be expressed as That is, the reference voltage VR1 is generated by adding the slope voltage Vs having a slope corresponding to the amplifier current Ia to the voltage VN2 obtained by subtracting the offset voltage Voff from the reference voltage VR0. As apparent from the above equation (4), the slope of the slope of the reference voltage VR1 varies according to the increase / decrease of the amplifier current Ia generated by the gm amplifier 11. Specifically, as shown in FIG. 2, the slope of the slope of the reference voltage VR1 becomes steeper (the amount of change is larger) as the amplifier current Ia becomes larger, while the slope of the reference voltage VR1 becomes smaller as the amplifier current Ia becomes smaller. The slope of is gradual (the amount of change is small).

  When the reference voltage VR1 again crosses the output voltage Vo (time t3), the control circuit 3 turns on the main-side transistor T1. At this time, in the control circuit 3, according to the potential difference between the output voltage Vo and the reference voltage VR0, the slope of the slope of the reference voltage VR1 (ratio of change according to the integration of the amplifier current Ia) so that the potential difference becomes small. Is adjusted to control the on-timing of the transistor T1.

Next, the operation of the DC-DC converter 1 (particularly, the reference voltage generation circuit 10) will be described with reference to FIGS.
First, the relationship among the input voltage Vi, the output voltage Vo, the on-time Ton of the transistor T1, and the off-time Toff of the transistor T1 will be described. The output voltage Vo when the input voltage Vi and the output voltage Vo are stable is a voltage according to the input voltage Vi and the on-duty of the transistor T1 on the main side. Here, the on-duty of the transistor T1 is represented by the ratio of the cycle of turning on the transistor T1, that is, the switching cycle T and the on-time Ton of the transistor T1. Therefore, the output voltage Vo is

となる。

It becomes.

  The switching period T is a total value of the on time Ton and the off time Toff. Therefore, the on time Ton and the off time Toff are respectively

と表わすことができる。

Can be expressed as

Next, the operation of the DC-DC converter 1 when the input voltage Vi increases will be described.
As shown in FIG. 3, when the reference voltage VR1 becomes higher than the output voltage Vo, the comparator 20 outputs an H level signal S1. The transistor T1 is turned on according to the signal S1. That is, the transistor T1 is turned on at the intersection of the waveform of the output voltage Vo and the waveform of the reference voltage VR1. For this reason, the time from when the transistor T1 is turned off until this intersection is the off time Toff of the transistor T1. Here, when the input voltage Vi increases (see broken line → solid line), as is clear from the above equation (6), the on-time Ton of the transistor T1 is shortened and the off-time Toff is lengthened.

  First, as a comparative example, an operation when using a reference voltage VR1a to which only a slope voltage with a fixed slope is added to the reference voltage VR0 will be described. As shown in FIG. 3B, when the input voltage Vi increases and the off time Toff becomes long, the slope of the slope of the reference voltage VR1a is fixed, so that the off time Toff becomes long. The voltage change amount of the reference voltage VR1a at time Toff increases. For this reason, the voltage value of the output voltage Vo crossing this reference voltage VR1 becomes high. Thus, in the case of the comparative example, the voltage values of both voltages Vo and VR1a at the intersection of the output voltage Vo and the reference voltage VR1a vary depending on the off time Toff. Therefore, in the case of the comparative example, as shown in FIG. 3C, the output voltage Vo varies according to the variation of the input voltage Vi (the variation of the off time Toff).

  On the other hand, the slope of the reference voltage VR1 of this embodiment is controlled so that the output voltage Vo and the reference voltage VR0 are equal to the reference voltage VR0 together with the offset voltage Voff having a fixed voltage value. A slope voltage Vs is added. Here, when the off time Toff becomes longer as the input voltage Vi increases, the output voltage Vo increases as the off time Toff increases as described above. At this time, the gm amplifier 11 in the reference voltage generation circuit 10 sets the current value of the amplifier current Ia so that the output voltage Vo is specifically equal to the reference voltage VR0 so as to suppress an increase in the output voltage Vo. Make it smaller. Then, the slope of the slope voltage Vs, that is, the slope of the slope of the reference voltage VR1 becomes gentle. For this reason, even if the OFF time Toff becomes longer as the input voltage Vi increases, the increase in the voltage value of the output voltage Vo that crosses the reference voltage VR1 is suppressed by the amount that the slope of the slope of the reference voltage VR1 becomes gentler. be able to.

  Specifically, in the reference voltage generation circuit 10, the negative feedback control by the gm amplifier 11 causes the change in the slope voltage Vs during the off time Toff to be equal to the voltage value of the offset voltage Voff as shown in the following equation. The slope of the slope voltage Vs (current value of the amplifier current Ia) is controlled.

このため、入力電圧Ｖｉと出力電圧Ｖｏとの関係で決まるオフ時間Ｔｏｆｆ（上記式（６）参照）における参照電圧ＶＲ１は、上記式（４）に上記式（７）を代入すると、

For this reason, the reference voltage VR1 in the off time Toff (see the above equation (6)) determined by the relationship between the input voltage Vi and the output voltage Vo is obtained by substituting the above equation (7) into the above equation (4).

となる。したがって、参照電圧ＶＲ１が基準電圧ＶＲ０になった時に、その参照電圧ＶＲ１が出力電圧Ｖｏを横切ることになる。このため、参照電圧ＶＲ１を横切る出力電圧Ｖｏの電圧値は基準電圧ＶＲ０に維持される。換言すると、参照電圧生成回路１０は、参照電圧ＶＲ１のスロープの傾斜を調整することでトランジスタＴ１のオフ時間Ｔｏｆｆを制御し、出力電圧Ｖｏを基準電圧ＶＲ０に維持している。これにより、図２に示すように、入力電圧Ｖｉが変動しても、その変動に伴う出力電圧Ｖｏの変動を抑制することができる（左部分→右部分参照）。このように、本実施形態のＤＣ−ＤＣコンバータ１では、入力電圧Ｖｉが変動しても、略一定の出力電圧Ｖｏを生成することができる。

It becomes. Therefore, when the reference voltage VR1 becomes the reference voltage VR0, the reference voltage VR1 crosses the output voltage Vo. For this reason, the voltage value of the output voltage Vo crossing the reference voltage VR1 is maintained at the reference voltage VR0. In other words, the reference voltage generation circuit 10 controls the off time Toff of the transistor T1 by adjusting the slope of the slope of the reference voltage VR1, and maintains the output voltage Vo at the reference voltage VR0. Thereby, as shown in FIG. 2, even if the input voltage Vi fluctuates, the fluctuation of the output voltage Vo accompanying the fluctuation can be suppressed (see the left part → the right part). As described above, the DC-DC converter 1 according to the present embodiment can generate the substantially constant output voltage Vo even when the input voltage Vi varies.

  Although detailed description is omitted here, when the input voltage Vi decreases, similarly, the fluctuation of the output voltage Vo accompanying the fluctuation can be suppressed (for example, the solid line → the broken line in FIG. 3A). reference).

  Further, the relationship between the reference voltage VR1 and the output voltage Vo will be described more specifically. As described above, the transistor T1 is turned on when the reference voltage VR1 crosses the output voltage Vo. Therefore, the output voltage Vo when the transistor T1 is turned on is equal to the reference voltage VR1 at that time. Therefore, the output voltage Vo when the transistor T1 is turned on is

と表わすことができる。この式（９）に上記式（２）を代入すると、

Can be expressed as Substituting the above equation (2) into this equation (9),

となる。本実施形態では、上述したように、ｇｍアンプ１１の電流変換利得ｇｍを高く設定している。具体的には、ｇｍアンプ１１の電流変換利得ｇｍが、

It becomes. In the present embodiment, as described above, the current conversion gain gm of the gm amplifier 11 is set high. Specifically, the current conversion gain gm of the gm amplifier 11 is

という関係を満たすように高く設定している。この式（１１）から上記式（１０）は、

It is set high to satisfy the relationship. From this equation (11), the above equation (10)

と近似することができる。すなわち、この式（１２）を満たすようにｇｍアンプ１１の電流変換利得ｇｍを設定することにより、出力電圧Ｖｏを表わす式からオフ時間Ｔｏｆｆの項がキャンセルされ、トランジスタＴ１をオンする時の出力電圧Ｖｏが基準電圧ＶＲ０（一定電圧）と略等しくなる。換言すると、高利得のｇｍアンプ１１によって、出力電圧Ｖｏが基準電圧ＶＲ０と等しくなるように参照電圧ＶＲ１のスロープの傾斜が制御され、出力電圧Ｖｏが基準電圧ＶＲ０で略一定に維持される。詳述すると、本実施形態の参照電圧生成回路１０では、高利得のｇｍアンプ１１によって、出力電圧Ｖｏと基準電圧ＶＲ０の電位差に応じたアンプ電流Ｉａが生成され、その電流Ｉａによって参照電圧ＶＲ１のスロープの傾斜が制御される。このような参照電圧生成回路１０では、ｇｍアンプ１１によって高利得の負帰還が掛かるため、そのｇｍアンプ１１で生成されたアンプ電流Ｉａによって、出力電圧Ｖｏが基準電圧ＶＲ０と等しくなるように参照電圧ＶＲ１のスロープの傾斜が制御される。このように制御されると、トランジスタＴ１のオフ時間Ｔｏｆｆにおける参照電圧ＶＲ１（スロープ電圧Ｖｓ）の変化分がオフセット電圧Ｖｏｆｆの電圧値と等しくなる。このため、出力電圧Ｖｏは、上記式（１２）に示すように、入力電圧Ｖｉ、出力電流Ｉｏやオフ時間Ｔｏｆｆに依存せず、基準電圧ＶＲ０のみに依存した略一定値に維持される。したがって、本実施形態のＤＣ−ＤＣコンバータ１は、入力電圧Ｖｉや出力電流Ｉｏが変動しても、安定した出力電圧Ｖｏを生成することができる。すなわち、ＤＣ−ＤＣコンバータ１では、ラインレギュレーション及びロードレギュレーションを改善することができる。

And can be approximated. That is, by setting the current conversion gain gm of the gm amplifier 11 so as to satisfy this equation (12), the term of the off time Toff is canceled from the equation representing the output voltage Vo, and the output voltage when the transistor T1 is turned on. Vo becomes substantially equal to the reference voltage VR0 (constant voltage). In other words, the slope of the slope of the reference voltage VR1 is controlled by the high gain gm amplifier 11 so that the output voltage Vo becomes equal to the reference voltage VR0, and the output voltage Vo is maintained substantially constant at the reference voltage VR0. More specifically, in the reference voltage generation circuit 10 of the present embodiment, the high gain gm amplifier 11 generates an amplifier current Ia corresponding to the potential difference between the output voltage Vo and the reference voltage VR0, and the current Ia generates the reference voltage VR1. The slope of the slope is controlled. In such a reference voltage generation circuit 10, since high gain negative feedback is applied by the gm amplifier 11, the reference voltage VR is set so that the output voltage Vo becomes equal to the reference voltage VR0 by the amplifier current Ia generated by the gm amplifier 11. The slope of the slope of VR1 is controlled. When controlled in this way, the change in the reference voltage VR1 (slope voltage Vs) during the off time Toff of the transistor T1 becomes equal to the voltage value of the offset voltage Voff. Therefore, as shown in the above equation (12), the output voltage Vo does not depend on the input voltage Vi, the output current Io, or the off time Toff, and is maintained at a substantially constant value that depends only on the reference voltage VR0. Therefore, the DC-DC converter 1 of the present embodiment can generate a stable output voltage Vo even when the input voltage Vi and the output current Io fluctuate. That is, in the DC-DC converter 1, line regulation and load regulation can be improved.

According to this embodiment described above, the following effects can be obtained.
(1) According to the potential difference between the output voltage Vo and the reference voltage VR0, the amplifier current Ia is generated by the gm amplifier 11 so that the potential difference becomes small, and a slope corresponding to the current Ia is added to the reference voltage VR0. A reference voltage VR1 is generated. At this time, since negative feedback is applied by the gm amplifier 11, the slope of the slope of the reference voltage VR1 is controlled by the amplifier current Ia generated by the gm amplifier 11 so that the output voltage Vo becomes equal to the reference voltage VR0. For example, even when the off time Toff becomes longer due to fluctuations in the input voltage Vi and the output current Io, the slope of the slope of the reference voltage VR1 becomes gentle so as to suppress an increase in the output voltage Vo due to fluctuations in the off time Toff. To be controlled. Therefore, even if the input voltage Vi and the output current Io fluctuate, it is possible to suppress the fluctuation of the voltage value of the output voltage Vo when crossing the reference voltage VR1. In other words, line regulation and load regulation can be improved.

  (2) Even if the capacitance of the capacitor C2 for generating the slope varies, the slope of the slope of the reference voltage VR1 is set so that the output voltage Vo becomes equal to the reference voltage VR0 by the negative feedback control by the gm amplifier 11. Therefore, variation in capacitance can be compensated for by controlling the slope. That is, when there is a variation in the capacitance of the capacitor C2, the slope of the slope of the reference voltage VR1 is adjusted by the amount of the variation. For this reason, even if the capacitance of the capacitor C2 varies, it is not necessary to adjust the output voltage Vo by trimming or the like, or to adjust the slope of the reference voltage VR1 by another circuit. Therefore, an increase in circuit scale can be suitably suppressed.

  (3) The voltage VN2 is generated by adding the offset voltage Voff to the reference voltage VR0, and the reference voltage VR1 is generated by adding a slope of slope corresponding to the amplifier current Ia to the voltage VN2. . As described above, the reference voltage VR1 (voltage) when the slope is started to be added to the reference voltage VR0 (when the slope starts to change at a rate corresponding to the integration of the amplifier current Ia). VN2) is offset from the reference voltage VR0. Furthermore, the reference voltage VR1 when the slope is added is offset from the reference voltage VR0 so that the reference voltage VR1 after the slope is added crosses the output voltage Vo at the level of the reference voltage VR0. Thereby, before the slope is added, the output voltage Vo compared with the comparator 20 and the reference voltage VR1 can be suitably suppressed from being the same potential. Further, by adding the offset voltage Voff, a slope whose slope is controlled so that the output voltage Vo becomes equal to the reference voltage VR0 can be reliably added to the reference voltage VR1, and the output voltage Vo can be added to the reference voltage VR0. It can be stabilized in a state consistent with. In other words, it can be said that the offset voltage Voff is a voltage for stabilizing the output voltage Vo in a state where it matches the reference voltage VR0 after forming the slope with the reference voltage VR1.

Furthermore, since the output voltage Vo is stable in a state where it matches the reference voltage VR0, the target voltage of the output voltage Vo can be easily set.
(4) An offset voltage Voff, which is a fixed voltage, is added to the reference voltage VRO. Thus, the voltage VN2 at the node N2 to which the slope is added is always constant. For this reason, the voltage VN2 at the node N2 is excellent in noise resistance.

  (5) The control circuit 3 can stabilize the output voltage Vo by controlling the slope of the reference voltage VR1. Therefore, the output voltage Vo can be stabilized without requiring a ripple component of the output voltage Vo. For this reason, a capacitor (for example, a multilayer ceramic capacitor) having a small resistance value of the equivalent series resistance ESR can be used as the smoothing capacitor C1. As a result, it is possible to reduce the size and cost of the DC-DC converter.

  (6) A control method is adopted in which the output voltage Vo and the reference voltage VR1 are always compared by the comparator 20, and the main-side transistor T1 is immediately switched according to the comparison result. In this control method, since the transistor T1 can be switched without going through an error amplifier or the like, a high-speed response to a sudden load change is possible.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. The DC-DC converter 1a of this embodiment is different from the first embodiment in that a delay circuit 30 is added and a switch SW1 is replaced with a P-channel MOS transistor T3. Hereinafter, the difference from the first embodiment will be mainly described.

  As shown in FIG. 4, the control signal S3 is supplied from the RS-FF circuit 21 to the delay circuit 30 of the control circuit 3a. As shown in FIG. 6, the delay circuit 30 outputs an L level delay signal Sd1 in response to an L level control signal S3, and in response to an H level control signal S3, the H level control signal S3. Is delayed by a predetermined delay time Td1, and an H level delay signal Sd1 is output. Here, the delay time Td1 is set to be longer than the discharge time Th for discharging the charge accumulated in the capacitor C2 in the reference voltage generation circuit 10a. As shown in FIG. 4, the delay signal Sd1 is supplied to the gate of the P-channel MOS transistor T3 in the reference voltage generation circuit 10a.

  The transistor T3 is connected in parallel with the capacitor C2. That is, the first terminal (source) of the transistor T3 is connected to the first terminal (node N3) of the capacitor C2. The second terminal (drain) of the transistor T3 is connected to the second terminal (node N2) of the capacitor C2. The transistor T3 is turned off in response to the H level delay signal Sd1, and is turned on in response to the L level delay signal Sd1.

The reference voltage generation circuit 10a outputs a reference voltage VR2 having a slope corresponding to the potential difference between the output voltage Vo and the reference voltage VR0 to the non-inverting input terminal of the comparator 20.
In this embodiment, the transistor T3 and the capacitor C2 are an example of a first additional circuit, the capacitor C2 is an example of a first capacitor, the transistor T3 is an example of a first switch, and the delay circuit 30 is an example of a timing adjustment circuit. . The reference voltage VR2 is an example of a first reference voltage, and the control signal S3 is an example of a control signal.

Next, an example of the internal configuration of the delay circuit 30 will be described with reference to FIG.
The control signal S3 output from the RS-FF circuit 21 is supplied to the gate of the P-channel MOS transistor T31 and to the inverter circuit 31.

  The output terminal of the inverter circuit 31 is connected to the first terminal of the resistor R31. The second terminal of the resistor R31 is connected to the first terminal of the capacitor C31, and the second terminal of the capacitor C31 is connected to the ground.

  A node N4 between the resistor R31 and the capacitor C31 is connected to the drain of the transistor T31. A bias voltage VB is supplied to the source of the transistor T31. The bias voltage VB is, for example, a voltage generated by a power supply circuit (not shown) or the input voltage Vi.

The node N4 is connected to the input terminal of the inverter circuit 32. The delay signal Sd1 is output from the inverter circuit 32.
Next, the operation of the delay circuit 30 configured as described above will be described with reference to FIG.

  When the L-level control signal S3 is supplied from the RS-FF circuit 21 (time t4), the transistor T31 is turned on. Then, since the bias voltage VB (H level signal) is supplied to the input terminal of the inverter circuit 32, the L level delay signal Sd1 is immediately output from the inverter circuit 32. Thus, the delay circuit 30 immediately outputs the L-level delay signal Sd1 at the timing (time t4) when the main-side transistor T1 switches from the OFF state to the ON state based on the L-level control signal S3.

  At this time, the inverter circuit 31 outputs an H level signal (for example, a bias voltage VB) in response to the L level control signal S3. For this reason, electric charge is accumulated in the capacitor C31 according to the current supplied through the resistor R31, and the potential of the first terminal of the capacitor C31 rises.

  Subsequently, when the control signal S3 output from the RS-FF circuit 21 transits from the L level to the H level (time t5), the transistor T31 is turned off. Further, an L level signal (for example, a ground potential) is output from the inverter circuit 31 in response to the H level control signal S3. However, since the potential of the first terminal of the capacitor C31 at this time, that is, the potential of the node N4 is close to the bias voltage VB, the inverter circuit 32 outputs an L-level delay signal Sd1. The electric charge accumulated in the capacitor C31 is discharged according to the time constant of the resistor R31 and the capacitor C31, and when the potential of the node N4 approaches the ground potential, the inverter circuit 32 outputs an H level delay signal Sd1. The As described above, the delay circuit 30 responds to the time constant of the resistor R31 and the capacitor C31 from the timing (time t5) when the main-side transistor T1 switches from the on state to the off state based on the control signal S3 of the H level. Delayed by the delay time Td1, the H-level delay signal Sd1 is output (time t7).

  Here, the H-level delay signal Sd1 generated by the delay circuit 30 is supplied to the gate of the transistor T3 in the reference voltage generation circuit 10a. When the transistor T3 is turned off in response to the H level delay signal Sd1, charging of the capacitor C2 is started, and the reference voltage VR2 rises from the voltage VN2 of the node N2 with a slope corresponding to the amplifier current Ia. That is, the delay circuit 30 delays the timing of adding a slope to the voltage VN2 at the node N2 by the delay time Td1 from the off timing (time t5) of the main transistor T1. In other words, the delay circuit 30 delays the start timing of changing the voltage VN2 of the node N2 at a rate of change corresponding to the integration of the amplifier current Ia by the delay time Td1 from the off timing (time t5) of the main transistor T1. I am letting.

Next, the operation of the DC-DC converter 1a will be described with reference to FIG.
As shown in FIG. 6 (a), the RS-FF circuit 21 responds to the H level signal S1 input from the comparator 20 when the output voltage Vo becomes lower than the reference voltage VR2. Control signal S2 and L level control signal S3 are output (see time t4). An L level control signal DH is generated in accordance with the H level control signal S2, and the transistor T1 is turned on by the L level control signal DH. In response to the L level control signal S3, the delay circuit 30 immediately outputs the L level delay signal Sd1. In response to the L level delay signal Sd1, the transistor T3 is turned on. Then, the electric charge accumulated in the capacitor C2 is gradually discharged, and the reference voltage VR2 gradually approaches the voltage VN2 (= VR0−Voff) at the node N2 from the reference voltage VR0 level. The discharge time Th of the capacitor C2 is determined by the time constant between the on-resistance of the transistor T3 and the capacitance value of the capacitor C2.

  Subsequently, when the H level clock signal CLK is output at time t5 before the discharge of the electric charge accumulated in the capacitor C2 is completed, the L level control signal S2 and the H level control are output from the RS-FF circuit 21. Signal S3 is output. Further, an H level control signal DH is generated in accordance with the L level control signal S2, and the transistor T1 is turned off by the H level control signal DH.

  At this time, as a comparative example, when the control signal S3 is directly supplied to the gate of the transistor T3, the transistor T3 is turned off in response to the H-level control signal S3. Therefore, as shown at time t8 in FIG. 6B, charging of the capacitor C2 is started before the reference voltage VR2a (solid line waveform) is reset to the voltage VN2 of the node N2. As a result, the voltage to which the slope is added (reference voltage VR2a at time t8) becomes higher than the voltage VN2 (= VR0−Voff) at the node N2. As a result, as compared with the case of the reference voltage VR2b (refer to the broken line waveform) that is reset to the voltage VN2 during the on time Ton, the time from when the transistor T1 is turned off until the reference voltage crosses the output voltage Vo, that is, the transistor T1. The off-time Toff becomes shorter. Therefore, in this case, even if the input voltage Vi and the output current Io are constant, the on-duty of the transistor T1 cannot be kept constant due to the shortening of the off time Toff. Such a problem is that when the input voltage Vi becomes sufficiently higher than the output voltage Vo (Vi >> Vo), the on-time Ton of the transistor T1 becomes extremely short, and the on-time Ton becomes the discharge time Th of the capacitor C2. Occurs when it becomes shorter. More specifically, the above-described problem occurs when the time during which the transistor T3 is turned on is shorter than the discharge time Th of the capacitor C2.

  On the other hand, in the DC-DC converter 1a of this embodiment, the H level control signal S3 is delayed by the delay time Td1 and supplied to the gate of the transistor T3. That is, the timing at which the slope is added to the voltage VN2 at the node N2 is delayed by a delay time Td1 longer than the discharge time Th of the capacitor C2 from the off timing of the transistor T1. Thereby, as shown in FIG. 6A, even when the on-time Ton is shorter than the discharge time Th of the capacitor C2, the time during which the transistor T3 is turned on by the delay time Td1 is set to be shorter than the discharge time Th. Can be long. Therefore, as shown in FIG. 6A, after the discharge of the capacitor C2 is always completed, the delay signal Sd1 rises to the H level, the transistor T3 is turned off, and charging of the capacitor C2 is started (time t7). That is, the addition of the slope is started after the discharge of the capacitor C2 is always completed. For this reason, the voltage to which the slope is added is always the voltage VN2 (= VR0−Voff) of the node N2. Thereby, if the input voltage Vi and the output current Io are constant, the on-duty of the transistor T1 can be kept constant. As a result, it is possible to suppress the occurrence of problems such as oscillation of the output voltage Vo and deterioration of regulation due to fluctuations in the on-duty of the transistor T1.

  Subsequently, when charging of the capacitor C2 is started as described above (time t7), the reference voltage VR2 rises from the voltage VN2 at a predetermined slope (= Ia / C2). That is, after the delay time Td1 has elapsed from the turn-off timing of the transistor T1, a slope voltage Vs having a slope corresponding to the amplifier current Ia is added to the voltage VN2 at the node N2. The slope voltage Vs is added to the voltage VN2 only during the time that the transistor T3 is off, that is, the charging time Tc of the capacitor C2. Here, as shown in FIG. 6A, the charging time Tc of the capacitor C2 is shorter than the off time Toff of the transistor T1 by the delay time Td1 (Tc = Toff−Td1). Therefore, the reference voltage VR2 of this embodiment is replaced with the above equation (4),

と表わすことができる。さらに、トランジスタＴ１がオンする時の出力電圧Ｖｏは、

Can be expressed as Furthermore, the output voltage Vo when the transistor T1 is turned on is

と表わすことができる。このとき、参照電圧生成回路１０ａでは、ｇｍアンプ１１による負帰還制御によって、コンデンサＣ２の充電時間Ｔｃにおけるスロープ電圧Ｖｓの変化分がオフセット電圧Ｖｏｆｆの電圧値と等しくなるように、スロープ電圧Ｖｓのスロープの傾斜が制御される。すなわち、ｇｍアンプ１１による負帰還制御によって、

Can be expressed as At this time, in the reference voltage generation circuit 10a, by the negative feedback control by the gm amplifier 11, the slope of the slope voltage Vs is set so that the change in the slope voltage Vs during the charging time Tc of the capacitor C2 becomes equal to the voltage value of the offset voltage Voff. Is controlled. That is, by negative feedback control by the gm amplifier 11,

となるように、アンプ電流Ｉａの電流値が制御される。このため、入力電圧Ｖｉと出力電圧Ｖｏとの関係で決まるオフ時間Ｔｏｆｆ（上記式（６）参照）において、基準電圧ＶＲ０レベルとなった参照電圧ＶＲ２が出力電圧Ｖｏを横切ることになる。これにより、本実施形態のＤＣ−ＤＣコンバータ１ａでは、オン時間Ｔｏｎ中にコンデンサＣ２の放電が完了し、且つコンデンサＣ２の充電時間がオフ時間Ｔｏｆｆと等しい場合（破線波形）と略同様のオンデューティに維持することができる。すなわち、遅延回路３０を追加しても、その遅延回路３０の遅延時間Ｔｄ１に起因してトランジスタＴ１のオンデューティが変動することはほとんどない。換言すると、遅延回路３０の遅延時間Ｔｄ１は、トランジスタＴ１のオンデューティにほとんど影響を及ぼさない。

Thus, the current value of the amplifier current Ia is controlled. For this reason, in the off time Toff determined by the relationship between the input voltage Vi and the output voltage Vo (see the above equation (6)), the reference voltage VR2 that has reached the reference voltage VR0 level crosses the output voltage Vo. Thereby, in the DC-DC converter 1a of this embodiment, the on-duty is substantially the same as when the discharging of the capacitor C2 is completed during the on-time Ton and the charging time of the capacitor C2 is equal to the off-time Toff (dashed line waveform). Can be maintained. That is, even when the delay circuit 30 is added, the on-duty of the transistor T1 hardly varies due to the delay time Td1 of the delay circuit 30. In other words, the delay time Td1 of the delay circuit 30 hardly affects the on-duty of the transistor T1.

  As shown in FIG. 6A, the slope of the slope of the reference voltage VR2 is steeper than the slope of the slope of the reference voltage VR2b shown by the broken line waveform, that is, the reference voltage VR2b calculated by the above equation (4). It has become. This is because, at the reference voltage VR2, the current value of the amplifier current Ia generated by the gm amplifier 11 increases as the charging time Tc of the capacitor C2 decreases by the delay time Td1.

As described above, according to the embodiment, in addition to the effects (1) to (6) of the first embodiment, the following effects can be obtained.
(7) The timing for adding the slope to the voltage VN2 at the node N2 is delayed by the delay time Td1 from the off timing of the main-side transistor T1. Further, the delay time Td1 is set longer than the discharge time Th of the capacitor C2. Thus, even when the on-time Ton is shorter than the discharge time Th of the capacitor C2, the addition of the slope to the voltage VN2 is always started after the discharge of the capacitor C2 for generating the slope is completed. be able to. Therefore, the voltage to which the slope is added (the voltage when the voltage rise is started) can always be maintained at the voltage VN2 of the node N2. For this reason, if the input voltage Vi and the output current Io are constant, the on-duty of the transistor T1 can be maintained substantially constant.

(Third embodiment)
Hereinafter, the third embodiment will be described with reference to FIGS. The DC-DC converter 1b of this embodiment is different from the second embodiment in that the delay circuit 30 is replaced with a delay circuit 40. Hereinafter, the difference from the second embodiment will be mainly described.

  As shown in FIG. 7, the input circuit Vi is supplied to the delay circuit 40 of the control circuit 3b together with the control signal S3 from the RS-FF circuit 21. The delay circuit 40 immediately outputs the L level delay signal Sd2 in response to the L level control signal S3. Further, in response to the H level control signal S3, the delay circuit 40 delays the H level control signal S3 by a delay time Td2 depending on the input voltage Vi and outputs the H level delay signal Sd2. Here, the delay time Td2 is a time set to be longer than the discharge time of the capacitor C2 in the reference voltage generation circuit 10b, and is a time that varies depending on the input voltage Vi. More specifically, the delay circuit 40 makes the charging time Tc (see FIG. 10A) of the capacitor C2 constant even if the off time Toff of the transistor T1 varies with the variation of the input voltage Vi. In addition, the delay time Td2 is controlled. In other words, the delay circuit 40 controls the delay time Td2 so that the period during which the reference voltage VR1 is changed at a rate of change corresponding to the integration of the amplifier current Ia is constant.

The reference voltage generation circuit 10b outputs a reference voltage VR3 having a slope corresponding to the potential difference between the output voltage Vo and the reference voltage VR0 to the non-inverting input terminal of the comparator 20.
The delay circuit 40 is an example of a timing adjustment circuit, and the reference voltage VR3 is an example of a first reference voltage.

Next, an example of the internal configuration of the delay circuit 40 will be described with reference to FIG.
An input terminal Pi to which an input voltage Vi is supplied is connected to the first terminal of the resistor R41. The second terminal of the resistor R41 is connected to the first terminal of the resistor R42, and the second terminal of the resistor R42 is connected to the ground. A connection point between the resistors R41 and R42 is connected to an inverting input terminal of the comparator 41. Therefore, a divided voltage V1 obtained by dividing the input voltage Vi by the resistors R41 and R42 is supplied to the inverting input terminal of the comparator 41.

  The current source 42 flows a current I1. In the current source 42, a bias voltage VB is supplied to a first terminal, and a first terminal of a capacitor C41 is connected to a second terminal. The second terminal of the capacitor C41 is connected to the ground.

  A connection point between the current source 42 and the capacitor C41 is connected to a non-inverting input terminal of the comparator 41. Therefore, the voltage of the first terminal of the capacitor C41, that is, the charging voltage V2 of the capacitor C41 is supplied to the non-inverting input terminal of the comparator 41.

  The connection point between the current source 42 and the capacitor C41 is also connected to the first terminal of the switch SW41. The second terminal of the switch SW41 is connected to the ground. That is, the switch SW41 is connected in parallel with the capacitor C41.

  A control signal S3 is supplied to the control terminal of the switch SW41 from the RS-FF circuit 21 shown in FIG. The switch SW41 is turned off when the control signal S3 is at the H level, and is turned on when the control signal S3 is at the L level. That is, the switch SW41 is turned on while the main-side transistor T1 is on, and is turned off when the transistor T1 is off.

  The comparator 41 generates a delay signal Sd2 having a level corresponding to the comparison result between the divided voltage V1 and the charging voltage V2. This delay signal Sd2 is supplied to the gate of the transistor T3 of the reference voltage generation circuit 10b shown in FIG.

Next, the operation of the delay circuit 40 configured as described above will be described with reference to FIG.
When the control signal S3 output from the RS-FF circuit 21 falls from the H level to the L level (time t9), the switch SW41 is turned on. Then, both terminals of the capacitor C41 are short-circuited. As a result, the charge stored in the capacitor C41 is discharged, and the charging voltage V2 of the capacitor C2 is reset to the ground level. At this time, since the charging voltage V2 becomes lower than the divided voltage V1, the L-level delay signal Sd2 is immediately output from the comparator 41. As described above, the delay circuit 40 immediately outputs the L-level delay signal Sd2 at the ON timing (time t9) of the main-side transistor T1 based on the L-level control signal S3.

  On the other hand, when the control signal S3 output from the RS-FF circuit 21 transitions from the L level to the H level (time t10), the switch SW41 is turned off. Then, the capacitor C41 starts charging with the current I1 that the current source 42 flows. As a result, the charging voltage V2 rises at a fixed slope (= I1 / C41) during the off period in which the transistor T1 is turned off in response to the H level control signal DH. When the charging voltage V2 becomes higher than the divided voltage V1 (time t11), the comparator 41 outputs an H level delay signal Sd2. That is, the time from when the H level control signal S3 is input until the charging voltage V2 crosses the divided voltage V1 is the delay time Td2 (see times t10 to t11). Here, since the slope of the charging voltage V2 is fixed, the divided voltage V1 increases as the input voltage Vi increases, and the time Td2 until the charging voltage V2 crosses the divided voltage V1 increases. On the other hand, when the input voltage Vi is lowered, the divided voltage V1 is lowered, and the time Td2 until the charging voltage V2 crosses the divided voltage V1 is shortened. That is, the delay time Td2 of the delay circuit 40 is increased or decreased in proportion to the input voltage Vi. As described above, the delay circuit 40 delays by the delay time Td2 proportional to the input voltage Vi from the off timing (time t10) of the main-side transistor T1 based on the H-level control signal S3, thereby delaying the H-level delay. The signal Sd2 is output.

  Here, the H-level delay signal Sd2 generated by the delay circuit 40 is supplied to the gate of the transistor T3 in the reference voltage generation circuit 10b. When the transistor T3 is turned off in response to the H level delay signal Sd2, charging of the capacitor C2 is started, and the reference voltage VR3 rises from the voltage VN2 of the node N2 with a slope corresponding to the amplifier current Ia. That is, the delay circuit 40 delays the timing for adding a slope to the voltage VN2 at the node N2 by the delay time Td2 from the off timing (time t10) of the main transistor T1.

  As a result, the charging time Tc of the capacitor C2 becomes a time obtained by subtracting the delay time Td2 from the off time Toff of the transistor T1, as shown in FIG. 9 (Tc = Toff−Td2). For this reason, by changing the delay time Td2 in proportion to the input voltage Vi as described above, even if the OFF time Toff varies with the variation of the input voltage Vi, the variation in the charging time Tc of the capacitor C2 is suppressed. can do. Thereby, since the fluctuation | variation of the inclination of the reference voltage VR3 accompanying the fluctuation | variation of the input voltage Vi is suppressed, the fluctuation | variation of the gain of the negative feedback loop of the DC-DC converter 1b can be suppressed.

  Hereinafter, the reason will be described in detail with reference to FIGS. FIG. 11 (a) shows a gain curve representing a change in gain Gain of the negative feedback loop of the DC-DC converter with respect to frequency, and FIG. 11 (b) shows a change in phase of gain Gain with respect to frequency. A representative phase curve is shown.

  First, the gain of the negative feedback loop of the DC-DC converter 1b is proportional to the input voltage Vi and proportional to the reciprocal of the slope of the reference voltage VR3. Here, the reference voltage VR3 is

と表わすことができる。したがって、ＤＣ−ＤＣコンバータ１ｂの負帰還ループの利得をＧａｉｎとすると、

Can be expressed as Therefore, when the gain of the negative feedback loop of the DC-DC converter 1b is Gain,

という関係式で表わすことができる。なお、ｇｍアンプ１１の電流変換利得ｇｍは、上記利得Ｇａｉｎには影響しない。

It can be expressed by the relational expression Note that the current conversion gain gm of the gm amplifier 11 does not affect the gain Gain.

  As apparent from the above equation (17), the gain Gain of the DC-DC converter 1b increases as the input voltage Vi increases, and the gain Gain of the DC-DC converter 1b increases as the slope of the reference voltage VR3 becomes gentler. For example, as a comparative example, as shown in FIG. 10B, when the input voltage Vi increases, if the slope of the reference voltage VR3a becomes gentle (see broken line → solid line), two factors (rise of the input voltage Vi) The gain Gain increases due to the inclination fluctuation of the reference voltage VR3a. Specifically, as shown in FIG. 11, the gain G2 when the slope of the reference voltage VR3a becomes gentle as the input voltage Vi increases, the slope of the reference voltage is fixed regardless of the increase of the input voltage Vi. It becomes higher than the gain G1 in the case of. At this time, since the phase P2 when the gain G2 is 0 dB is smaller than the phase P1 when the gain G1 is 0 dB, the phase margin is small. For this reason, in the comparative example, the DC-DC converter easily oscillates and the operation becomes unstable.

  On the other hand, in the DC-DC converter 1b of the present embodiment, the delay time Td2 of the delay circuit 40 is varied in proportion to the input voltage Vi. Specifically, the delay circuit 40 adjusts the delay time Td2 so that the charging time Tc of the capacitor C2 becomes constant regardless of the fluctuation of the input voltage Vi. In other words, in the delay circuit 40, the resistance values of the resistors R41 and R42, the current value of the current I1, and the capacitance value of the capacitor C41 are set so that the delay time Td2 is adjusted in this way. Therefore, as shown in FIG. 10A, when the input voltage Vi increases (broken line → solid line), the delay time is increased by an amount corresponding to the increase in the off time Toff of the transistor T1 as the input voltage Vi increases. Td2 also becomes longer. Specifically, when the off time Toff of the transistor T1 increases by the time ΔT as the input voltage Vi increases, the delay time Td2 also increases by the time ΔT as the input voltage Vi increases. Thereby, it is suppressed that the charging time Tc of the capacitor C2 becomes longer as the input voltage Vi increases, and the charging time Tc is maintained substantially constant. As a result, even when the input voltage Vi increases, the current value of the amplifier current Ia generated by the gm amplifier 11, that is, the slope of the slope of the reference voltage VR3 can be maintained substantially constant, and the DC-DC converter 1b Variations in the gain Gain of the negative feedback loop can be suppressed. Specifically, in the DC-DC converter 1b of the present embodiment, even if the input voltage Vi increases, the gain Gain of the negative feedback loop of the DC-DC converter 1b is limited to only one factor (an increase in the input voltage Vi). Therefore, the gain does not increase to the gain G2, but is substantially equal to the gain G1. That is, an increase in the gain Gain of the DC-DC converter 1b can be suppressed as compared with the case where the slope of the reference voltage VR3a becomes gentle as the input voltage Vi increases.

According to the embodiment described above, in addition to the effects (1) to (6) of the first embodiment and (7) of the second embodiment, the following effects can be obtained.
(8) The timing for adding the slope to the voltage VN2 at the node N2 is delayed by a delay time Td2 proportional to the input voltage Vi from the off timing of the transistor T1 on the main side. Thereby, it can suppress that the charging time Tc of the capacitor | condenser C2 fluctuates with the fluctuation | variation of the input voltage Vi. Therefore, since the fluctuation of the slope of the reference voltage VR3 is suppressed, the fluctuation of the gain Gain of the DC-DC converter 1b accompanying the fluctuation of the input voltage Vi can be suppressed. As a result, it is possible to suppress the phase margin from becoming small, and the DC-DC converter 1b can be stably operated.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to FIGS. The DC-DC converter 1c of this embodiment is different from the second embodiment in that the second power source E2 is replaced with an offset voltage generation circuit 50. Hereinafter, the difference from the second embodiment will be mainly described.

  In the control circuit 3b of the third embodiment, the delay time Td2 of the delay circuit 40 is made to depend on the input voltage Vi, so that fluctuations in the gain Gain of the negative feedback loop of the DC-DC converter 1b are suppressed. In contrast, in the control circuit 3c of the present embodiment, the offset voltage subtracted from the reference voltage VR0 is made to depend on the input voltage Vi so as to suppress fluctuations in the gain Gain of the negative feedback loop of the DC-DC converter 1c. did.

  As shown in FIG. 12, the offset voltage generation circuit 50 of the reference voltage generation circuit 10c is supplied with the reference voltage VR0 from the first power supply E1 and the input voltage Vi. The offset voltage generation circuit 50 generates an offset voltage Vof1 (see FIG. 13) depending on the input voltage Vi, and generates a voltage VN21 obtained by subtracting the offset voltage Vof1 from the reference voltage VR0. Then, the offset voltage generation circuit 50 outputs the generated voltage VN21 to the node N2.

  The reference voltage generation circuit 10c generates a reference voltage VR4 by adding a slope corresponding to the potential difference between the output voltage Vo and the reference voltage VR0 to the voltage VN21 of the node N2, and generates the reference voltage VR4 in the non-inverted state of the comparator 20 Output to the input terminal.

  The offset voltage generation circuit 50 is an example of a second additional circuit, the offset voltage Vof1 is an example of an offset, the voltage value of the offset voltage Vof1 is an example of an offset amount, and the reference voltage VR4 is an example of a first reference voltage.

Next, an example of the internal configuration of the offset voltage generation circuit 50 will be described with reference to FIGS.
As shown in FIG. 13, the reference voltage VR <b> 0 is supplied to the non-inverting input terminal of the operational amplifier 51. The output terminal of the operational amplifier 51 is connected to the inverting input terminal of the operational amplifier 51 through a resistor R51.

  A current Ioff proportional to the input voltage Vi is supplied from the current source 52 to the resistor R51. Therefore, the voltage at the connection point between the resistor R51 and the current source 52, that is, the offset voltage Vof1 is

となる。すなわち、オフセット電圧Ｖｏｆ１は、入力電圧Ｖｉに比例して電圧値が変動する。

It becomes. That is, the voltage value of the offset voltage Vof1 varies in proportion to the input voltage Vi.

  The operational amplifier 51 outputs a voltage VN21 obtained by subtracting the offset voltage Vof1 from the reference voltage VR0 to the node N2. That is, the voltage VN21 is

と表わすことができる。

Can be expressed as

Next, an example of the internal configuration of the current source 52 will be described with reference to FIG.
An input terminal Pi to which an input voltage Vi is supplied is connected to the first terminal of the resistor R52. The second terminal of the resistor R52 is connected to the first terminal of the resistor R53, and the second terminal of the resistor R53 is connected to the ground. A connection point between the resistors R52 and R53 is connected to a non-inverting input terminal of the operational amplifier 53. Therefore, a divided voltage V3 obtained by dividing the input voltage Vi by the resistors R52 and R53 is supplied to the non-inverting input terminal of the operational amplifier 53.

  The output terminal of the operational amplifier 53 is connected to the gate of the N-channel MOS transistor T51. Transistor T51 has its drain connected to the drain of P-channel MOS transistor T52 and its source connected to the inverting input terminal of operational amplifier 53 and the first terminal of resistor R54. The second terminal of the resistor R54 is connected to the ground.

  The operational amplifier 53 controls the transistor T51 so that the voltage at the inverting input terminal is equal to the divided voltage V3 of the input voltage Vi. That is, the voltage at the first terminal of the resistor R54 is controlled to be the divided voltage V3. Therefore, a current I2 corresponding to the resistance value of the resistor R54 and the potential difference (divided voltage V3) between the two terminals flows between both terminals of the resistor R54. That is, the current I2 is a current proportional to the input voltage Vi.

  The transistor T52 is supplied at its source with a bias voltage VB, and has its gate connected to the drain of the transistor T52 and the gate of a P-channel MOS transistor T53. A bias voltage VB is supplied to the source of the transistor T53. Therefore, the transistor T52 and the transistor T53 are included in the current mirror circuit. This current mirror circuit causes a current Ioff proportional to the current I2 flowing through the resistor R54 to flow through the transistor T53 in accordance with the electrical characteristics of the transistors T52 and T53.

The drain of the transistor T53 is connected to the second terminal of the resistor R51 shown in FIG. 13, and a current Ioff proportional to the input voltage Vi is supplied to the resistor R51.
As described above, the offset voltage generation circuit 50 generates the offset voltage Vof1 proportional to the input voltage Vi in accordance with the current Ioff proportional to the input voltage Vi, and subtracts the offset voltage Vof1 from the reference voltage VR0 to generate the voltage VN21. Is generated. Specifically, the offset voltage generation circuit 50 generates the offset voltage Vof1 and the voltage VN21 so that the slope of the reference voltage VR4 is constant regardless of the fluctuation of the input voltage Vi. Furthermore, in the offset voltage generation circuit 50, the resistance values of the resistors R51 to R54, the size ratio of the transistors T52 and T53, and the like are set so that the offset voltage Vof1 and the voltage VN21 are generated.

Next, the operation of the DC-DC converter 1c will be described with reference to FIG.
When the input voltage Vi increases (broken line → solid line), the off time Toff becomes longer, and the time during which the transistor T3 is turned off, that is, the charging time Tc (= Toff−Td1) of the capacitor C2 becomes longer. At this time, as the input voltage Vi increases, the offset voltage Vof1 also increases (broken line → solid line). For this reason, the voltage VN21 (= VR0−Vof1) to which the slope voltage Vs is added decreases. That is, the potential difference between the reference voltage VR0 and the reference voltage VR4 when the slope is added increases. Therefore, the amount of change in the slope voltage Vs for making the reference voltage VR0 and the reference voltage VR4 equal is increased. As a result, as shown in FIG. 15, even when the charging time Tc of the capacitor C2 becomes longer as the input voltage Vi increases, the inclination of the reference voltage VR4 can be suppressed from changing (gradually). . Thereby, the fluctuation | variation of the gain Gain of the negative feedback loop of the DC-DC converter 1c can be suppressed.

According to this embodiment described above, the same effects as those of the third embodiment can be obtained.
(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.

  In each of the above embodiments, the offset voltages Voff and Vof1 are added to the reference voltage VR0. However, the addition method is not particularly limited as long as an offset voltage is added so that a potential difference is generated between the output voltage Vo compared by the comparator 20 and the reference voltages VR1 to VR4 when the slope is added. . Below, the DC-DC converter 1d which deform | transformed the DC-DC converter 1 of 1st Embodiment is demonstrated.

  For example, as shown in FIG. 16, a DC offset may be added to the comparator 60 that compares the output voltage Vo and the reference voltage VR5. That is, the comparator 60 has an offset voltage Vof2 between two input terminals. The comparator 60 compares the output voltage Vo with the voltage VR5a (= VR0 + Vs−Vof2), which is lower than the reference voltage VR5 (= VR0 + Vs) generated by the reference voltage generation circuit 10d by the offset voltage Vof2. The comparator 60 outputs an L level signal S1a when the output voltage Vo is higher than the voltage VR5a, and outputs an H level signal S1a when the output voltage Vo is lower than the voltage VR5a. Therefore, even with such a configuration, the same effects as those of the first embodiment can be obtained. In this modification, the offset voltage Vof2 is an example of an offset, and the reference voltage VR5 is an example of a first reference voltage.

  The offset voltage Vof2 described above can be added by breaking the current balance or voltage balance from the input terminal to the output terminal of the comparator 60. Hereinafter, the specific addition method is demonstrated.

First, an internal configuration example of the comparator 60 will be described with reference to FIG.
Sources of the input transistors T61 and T62 in the differential input circuit 61 are connected to each other, and the sources are connected to the current source 62. An inverting input terminal -IN to which an output voltage Vo is supplied is connected to the gate of the input transistor T61. A non-inverting input terminal + IN to which a reference voltage VR5 is supplied is connected to the gate of the input transistor T62. The drains of these input transistors T61 and T62 are respectively connected to the drains of N channel MOS transistors T63 and T64 included in the current mirror circuit. Transistors T63 and T64 have their gates connected to the drain of transistor T63 and their sources connected to the ground.

  The connection point between the transistors T62 and T64 is connected to the gate of the N-channel MOS transistor T65. The transistor T65 has a source connected to the ground and a drain connected to the current source 63. A connection point between the transistor T65 and the current source 63 is connected to the output terminal OUT. Then, the signal S1a is output from the output terminal OUT.

  In the comparator 60 configured as described above, the element sizes of the input transistors T61 and T62 are set to different sizes. Specifically, the element size of the input transistor T61 to which the output voltage Vo is supplied to the gate is made larger than the element size of the input transistor T62 to which the reference voltage VR1 is supplied to the gate. As a result, a DC offset (offset voltage Vof2) can be added to the comparator 60. In this case, the input transistors T61 and T62 function as a second additional circuit.

  Also, as shown in FIG. 18, a resistor R61 may be connected to the source of the input transistor T61, and a resistor R62 having a higher resistance than the resistor R61 may be connected to the source of the input transistor T62. Also with this configuration, a DC offset (offset voltage Vof2) can be added to the comparator 60. Furthermore, the resistors R61 and R62 may be variable resistors, and the resistance values may be varied depending on the input voltage Vi. In this way, the offset voltage Vof2 added to the comparator 60 can be varied depending on the input voltage Vi. In this case, the resistors R61 and R62 function as a second additional circuit.

Alternatively, offset voltages Voff and Vof1 may be added to the output voltage Vo.
Further, as shown in FIG. 19, a slope may be added to the reference voltage Vr supplied from a third power source E3 different from the first power source E1. However, the reference voltage Vr is a voltage set according to the reference voltage VR0, and more specifically, is a voltage set lower than the reference voltage VR0 by a voltage corresponding to the offset voltage. Therefore, the third power supply E3 in this modification is an example of the second additional circuit, and the difference voltage between the reference voltage VR0 and the reference voltage Vr is an example of an offset.

-Addition of offset voltage Voff, Vof1, Vof2 in each said embodiment may be abbreviate | omitted.
In each of the above embodiments, a slope is added to the reference voltage VR0 side of the reference voltage VR0 and the output voltage Vo. For example, a slope may be added to the output voltage Vo side. Below, the DC-DC converter 1e which changed the control circuit 3 of 1st Embodiment is demonstrated.

  For example, as shown in FIG. 20, the reference voltage VR6 (= VR0−Voff) obtained by subtracting the offset voltage Voff from the reference voltage VR0 is supplied to the non-inverting input terminal of the comparator 20 of the control circuit 3e. The inverting input terminal of the comparator 20 is supplied with the first feedback voltage VFB generated by the feedback voltage generation circuit 10e. The comparator 20 generates an L level signal S1 when the first feedback voltage VFB is higher than the reference voltage VR6, and outputs an H level signal S1 when the first feedback voltage VFB is lower than the reference voltage VR1. Generate.

  The feedback voltage generation circuit 10e generates a first feedback voltage VFB by adding a slope corresponding to the potential difference between the output voltage Vo and the reference voltage VR0 to the output voltage Vo. Specifically, the gm amplifier 11e of the feedback voltage generation circuit 10e generates the amplifier current Ia1 so that the potential difference becomes small according to the potential difference between the output voltage Vo and the reference voltage VR0. The output terminal of the gm amplifier 11e is connected to the first terminal of the capacitor C3 and the first terminal of the switch SW3. The second terminal of the capacitor C3 and the second terminal of the switch SW3 are connected to the output terminal Po of the DC-DC converter 1d. Thus, the capacitor C3 and the switch SW3 are connected in parallel. The voltage at the first terminal of the capacitor C3 is supplied to the inverting input terminal of the comparator 20 as the first feedback voltage VFB.

  A control signal S3 is supplied from the inverting output terminal XQ of the RS-FF circuit 21 to the control terminal of the switch SW3. The switch SW3 is turned off when the control signal S3 is at the H level, and is turned on when the control signal S3 is at the L level. That is, the switch SW3 is turned on while the main-side transistor T1 is on, and is turned off when the transistor T1 is off.

  When the switch SW3 is turned on (when the transistor T1 is turned on), both terminals of the capacitor C3 are short-circuited. As a result, the voltage at the first terminal of the capacitor C3 becomes equal to the voltage at the second terminal of the capacitor C3, that is, the output voltage Vo. For this reason, the first feedback voltage VFB during the ON period of the transistor T1 has a constant level equal to the output voltage Vo.

  On the other hand, when the switch SW3 is turned off (when the transistor T1 is turned off), the electric charge stored in the capacitor C3 is discharged according to the amplifier current Ia1 generated by the gm amplifier 11e. As a result, the first feedback voltage VFB during the off period of the transistor T1 decreases from the output voltage Vo at a slope (= Ia1 / C3) corresponding to the amplifier current Ia1. In other words, during the off period of the transistor T1, a slope having a slope corresponding to the amplifier current Ia1 is added to the output voltage Vo to generate the first feedback voltage VFB.

  Even in such a configuration, the negative feedback control by the gm amplifier 11e controls the current value of the amplifier current Ia1, that is, the slope of the slope of the first feedback voltage VFB so that the output voltage Vo becomes equal to the reference voltage VR0. Therefore, the same effect as the first embodiment is obtained. In this modification, the gm amplifier 11e is an example of an amplifier, the capacitor C3 and the switch SW3 are examples of a first additional circuit, the reference voltage VR6 is an example of a first reference voltage, and the first feedback voltage VFB is the first feedback voltage. For example, the output voltage Vo is an example of the second feedback voltage.

  Further, in the DC-DC converter 1e in the above modification, an offset voltage Voff may be added to the first feedback voltage VFB. Specifically, the first feedback voltage VFB may be generated by adding a slope with a slope corresponding to the amplifier current Ia1 to the voltage obtained by adding the offset voltage Voff to the output voltage Vo. In this case, the reference voltage VR0 is supplied to the non-inverting input terminal of the comparator 20. The reference voltage VR0 at this time is an example of the first reference voltage and the second reference voltage.

  In each of the above embodiments, the output voltage Vo is supplied to the gm amplifiers 11 and 11e as an example of the second feedback voltage. However, the second feedback voltage is not particularly limited as long as it is a voltage corresponding to the output voltage Vo (for example, a voltage obtained by dividing the output voltage Vo). Further, the first feedback voltage VFB may be generated by adding the above-described slope or offset to the divided voltage of the output voltage Vo.

The delay time Td1 of the delay circuit 40 in the third embodiment may be varied depending on the input voltage Vi and the output voltage Vo.
In the delay circuit 40 in the third embodiment, the delay time Td2 may be adjusted to be shorter than the discharge time Th of the capacitor C2 according to the input voltage Vi.

The delay circuit 30 in the fourth embodiment may be omitted.
The offset voltage Vof1 generated by the offset voltage generation circuit 50 in the fourth embodiment may be varied depending on the input voltage Vi and the output voltage Vo.

  -You may make it combine said each embodiment suitably. For example, the second power source E2 of the DC-DC converter 1b of the third embodiment may be replaced with the offset voltage generation circuit 50 of the fourth embodiment. Further, the delay circuit 30 of the second embodiment and the delay circuit 40 of the third embodiment may be applied to the DC-DC converters 1d and 1e of the above modification.

  In each of the above embodiments, the control signal S3 is supplied to the switches SW1, T3, and SW3 connected in parallel with the slope-generating capacitors C2 and C3. However, the ON period or OFF period of the main-side transistor T1 The signal is not particularly limited as long as the signal corresponds to. For example, it may be a signal obtained by logically inverting the control signal S2 shown in FIG. 1, the control signals DH and DL, or the voltage at the node N1.

  In each of the above embodiments, the transistor T1 is turned off in accordance with the H level clock signal CLK rising at a predetermined cycle. For example, the transistor T1 may be turned off after a predetermined time has elapsed from the rising timing of the output signal S1 of the comparator 20 (on timing of the transistor T1). In this case, for example, instead of the oscillator 22, an H level pulse signal is output to the reset terminal R of the RS-FF circuit 21 after elapse of time depending on the input voltage Vi and the output voltage Vo from the rising timing of the output signal S 1. A timer circuit may be provided. Alternatively, a one-shot flip-flop circuit may be provided instead of the RS-FF circuit 21 and the oscillator 22.

  In each of the above embodiments, the P-channel MOS transistor T1 is disclosed as an example of the switch circuit, but an N-channel MOS transistor may be used. A bipolar transistor may be used as the switch circuit. Alternatively, a switch circuit including a plurality of transistors may be used.

In the above embodiments, the reference voltage VR0 may be generated outside the control circuits 3 and 3a to 3e.
The transistors T1 and T2 in the above embodiments may be included in the control circuits 3, 3a to 3e. Moreover, you may make it include the converter part 2 in each control circuit 3, 3a-3e.

In each of the above embodiments, the synchronous rectification type DC-DC converter is embodied, but the asynchronous rectification type DC-DC converter may be embodied.
In each of the above embodiments, the output voltage Vo and the reference voltages VR1 to VR5 are compared, and the embodiment is embodied as a DC-DC converter that sets the on-timing of the main-side transistor T1 according to the comparison result. For example, the output voltage Vo and the reference voltages VR1 to VR5 may be compared, and a DC-DC converter that sets the off timing of the main-side transistor T1 according to the comparison result may be used.

  FIG. 21 illustrates an example of an electronic device 100 including the DC-DC converter 1 (or the DC-DC converters 1a to 1e). The electronic device 100 includes a main body 110 and a power supply 130 that supplies power to the main body 110.

First, an internal configuration example of the main body 110 will be described.
A central processing unit (CPU) 111 that executes a program is connected to a memory 112 that stores a program executed by the CPU 111 or data processed by the CPU 111. In addition, a keyboard 114 </ b> A and a pointing device 114 </ b> B are connected to the CPU 111 via an interface (I / F) 113. The pointing device 114B is, for example, a flat device having a mouse, a trackball, a touch panel, or an electrostatic sensor.

  In addition, a display 116 is connected to the CPU 111 via an interface 115, and a communication unit 118 is connected via an interface 117. The display 116 is, for example, a liquid crystal display or an electroluminescence panel. The communication unit 118 is, for example, a local area network board.

  Further, an external storage device 120 is connected to the CPU 111 via an interface 119, and a removable recording medium access device 122 is connected via an interface 121. The external storage device 120 is, for example, a hard disk. Examples of the removable recording medium accessed by the access device 122 include a CD (Compact Disc), a DVD (Digital Versatile Disk), and a flash memory card.

Next, an internal configuration example of the power supply unit 130 will be described.
The DC-DC converter 1 (or DC-DC converters 1a to 1e) and the AC adapter 131 are connected to the main body 110 via the switch SW1. Power is supplied to the main body 110 from any one of the DC-DC converter 1 (or DC-DC converters 1a to 1e) and the AC adapter 131. In the example of FIG. 21, the DC-DC converter 1 (or the DC-DC converters 1 a to 1 e) converts, for example, an input voltage Vi from the battery 132 into an output voltage Vo, and supplies the output voltage Vo to the main body 110. .

  Such electronic devices include notebook personal computers, communication devices such as mobile phones, information processing devices such as personal digital assistants (PDAs), video equipment such as digital cameras and video cameras, and receivers such as television devices. Etc.

The various embodiments described above can be summarized as follows.
(Appendix 1)
A power supply control circuit,
A switching control unit configured to switch the switch circuit to which the input voltage of the power source is supplied according to a comparison result between a first feedback voltage corresponding to the output voltage of the power source and a first reference voltage;
An amplifier that generates a current according to a difference between a second feedback voltage according to the output voltage and a second reference voltage set according to a target value of the output voltage;
The first feedback voltage is generated by changing the second feedback voltage at a rate of change corresponding to the integration of the current, or the second reference voltage is changed at the rate of change to change the first reference voltage. A first additional circuit to be generated;
A control circuit comprising:
(Appendix 2)
And a timing adjustment circuit that adjusts a start timing of changing the first feedback voltage or the first reference voltage at the rate of change to a timing delayed by a predetermined time from a switching timing of the switch circuit. The control circuit according to appendix 1.
(Appendix 3)
The timing adjustment circuit generates a delay signal by giving a delay of the predetermined time to a control signal corresponding to an on period or an off period of the switch circuit;
The first additional circuit includes:
A first capacitor to which the current of the amplifier is supplied;
A first switch connected in parallel to the first capacitor and turned on / off by the delay signal, and in response to the delay signal, the first feedback voltage or the first reference voltage according to the charge of the first capacitor At the rate of change,
The control circuit according to appendix 2, wherein the predetermined time is set longer than a discharge time for discharging the charge accumulated in the first capacitor.
(Appendix 4)
4. The control circuit according to appendix 2 or 3, wherein the timing adjustment circuit adjusts the predetermined time according to the input voltage.
(Appendix 5)
The control circuit according to appendix 4, wherein the timing adjustment circuit adjusts the predetermined time so that a period during which the first feedback voltage or the first reference voltage is changed at a rate of the change is constant. .
(Appendix 6)
The timing adjustment circuit outputs a delay signal of a first level according to a timing of switching the switch circuit from the first state to the second state based on a control signal corresponding to an on period or an off period of the switch circuit. Output, delaying the switch circuit from the second state to the first state by the predetermined time to set the delayed signal to the second level,
The first additional circuit outputs the first feedback voltage or the first reference voltage at a constant level in response to the delay signal at the first level, and responds to the delay signal at the second level. The control circuit according to any one of appendices 2 to 5, wherein the first feedback voltage or the first reference voltage is changed at a rate of the change.
(Appendix 7)
The timing adjustment circuit includes:
A second capacitor to which a first current is supplied;
A second switch connected in parallel to the second capacitor and turned on / off by a control signal corresponding to an on period or an off period of the switch circuit;
A comparator that generates a delay signal obtained by delaying the control signal by the predetermined time in accordance with a comparison result between a first voltage corresponding to the input voltage and a charging voltage of the second capacitor;
The control circuit according to appendix 4 or 5, characterized by comprising:
(Appendix 8)
The first feedback voltage and the first reference voltage are set such that a potential difference is generated between the first feedback voltage and the first reference voltage when starting to change the first feedback voltage or the first reference voltage at the rate of change. The control circuit according to any one of appendices 1 to 7, further comprising a second addition circuit that adds an offset to at least one of the one reference voltage.
(Appendix 9)
The control circuit according to appendix 8, wherein the second additional circuit adjusts an offset amount of the offset according to the input voltage.
(Appendix 10)
The control circuit according to appendix 9, wherein the second additional circuit adjusts the offset amount of the offset so that the rate of change is constant.
(Appendix 11)
The second additional circuit includes:
A current source that outputs a second current according to the input voltage;
A resistor through which the second current flows,
11. The control circuit according to appendix 9 or 10, wherein the voltage of the resistor is the offset.
(Appendix 12)
The switching control unit includes a comparator that compares the first feedback voltage with the first reference voltage;
The control circuit according to any one of appendices 8 to 11, wherein the second addition circuit adds the offset to the comparator.
(Appendix 13)
An electronic device having a power supply having a control circuit and an internal circuit to which an output voltage of the power supply is supplied,
The control circuit includes:
A switching control unit configured to switch a switch circuit to which an input voltage of the power source is supplied according to a comparison result between a first feedback voltage corresponding to the output voltage and a first reference voltage;
An amplifier that generates a current according to a difference between a second feedback voltage according to the output voltage and a second reference voltage set according to a target value of the output voltage;
The first feedback voltage is generated by changing the second feedback voltage at a rate of change corresponding to the integration of the current, or the second reference voltage is changed at the rate of change to change the first reference voltage. A first additional circuit to be generated;
An electronic device comprising:
(Appendix 14)
A power supply control method for switching a switch circuit to which an input voltage of a power supply is supplied according to a comparison result between a first feedback voltage corresponding to an output voltage of the power supply and a first reference voltage,
Generating a current according to a difference between a second feedback voltage according to the output voltage and a second reference voltage set according to a target value of the output voltage;
The first feedback voltage is generated by changing the second feedback voltage at a rate of change corresponding to the integration of the current, or the second reference voltage is changed at the rate of change to change the first reference voltage. A method for controlling a power supply, characterized by comprising:

1,1a ~ 1e DC-DC converter (power supply)
3, 3a-3e Control circuit T1 transistor (switch circuit)
11, 11e Transconductance amplifier (amplifier)
20, 60 Comparator 21 RS-FF circuit 22 Oscillator 23 Drive circuit 30, 40 Delay circuit (timing adjustment circuit)
50 Offset voltage generation circuit 100 Electronic device 110 Main body (internal circuit)
C2 capacitor (first capacitor)
C3 capacitor C41 capacitor (second capacitor)
SW1, SW3 switch SW41 switch (second switch)
T3 transistor (first switch)
E1 1st power supply E2 2nd power supply E3 3rd power supply

Claims (7)

A power supply control circuit,
A switching control unit configured to switch the switch circuit to which the input voltage of the power source is supplied according to a comparison result between a first feedback voltage corresponding to the output voltage of the power source and a first reference voltage;
An amplifier for generating a current corresponding to the difference between the second feedback voltage and a second reference voltage corresponding to the output voltage,
The first feedback voltage is generated by changing the second feedback voltage at a rate of change corresponding to the integration of the current, or the second reference voltage is changed at the rate of change to change the first reference voltage. A first additional circuit to be generated;
A timing adjustment circuit that adjusts a start timing of changing the first feedback voltage or the first reference voltage at the rate of change to a timing delayed by a predetermined time from a switching timing of the switch circuit;
A control circuit comprising: The timing adjustment circuit generates a delay signal by giving a delay of the predetermined time to a control signal corresponding to an on period or an off period of the switch circuit;
The first additional circuit includes:
A first capacitor to which the current of the amplifier is supplied;
A first switch connected in parallel to the first capacitor and turned on / off by the delay signal, and in response to the delay signal, the first feedback voltage or the first reference voltage according to the charge of the first capacitor At the rate of change,
The control circuit according to claim 1 , wherein the predetermined time is set longer than a discharge time for discharging the electric charge accumulated in the first capacitor. Said first feedback voltage or the first reference voltage when the start changing at a rate of the change, that it has a second addition circuit for adding an offset to at least one of the first feedback voltage and the first reference voltage The control circuit according to claim 1 or 2 , characterized in that   A power supply control circuit,
  A switching control unit configured to switch the switch circuit to which the input voltage of the power source is supplied according to a comparison result between a first feedback voltage corresponding to the output voltage of the power source and a first reference voltage;
  An amplifier that generates a current according to a difference between a second feedback voltage according to the output voltage and a second reference voltage;
  The first feedback voltage is generated by changing the second feedback voltage at a rate of change corresponding to the integration of the current, or the second reference voltage is changed at the rate of change to change the first reference voltage. A first additional circuit to be generated;
  A second additional circuit for adding an offset to at least one of the first feedback voltage and the first reference voltage when starting to change the first feedback voltage or the first reference voltage at the rate of change;
A control circuit comprising: 5. The control circuit according to claim 3, wherein the second additional circuit adjusts an offset amount of the offset according to the input voltage. 6. An electronic device having a power supply having a control circuit and an internal circuit to which an output voltage of the power supply is supplied,
The control circuit includes:
A switching control unit configured to switch a switch circuit to which an input voltage of the power source is supplied according to a comparison result between a first feedback voltage corresponding to the output voltage and a first reference voltage;
An amplifier for generating a current corresponding to the difference between the second feedback voltage and a second reference voltage corresponding to the output voltage,
The first feedback voltage is generated by changing the second feedback voltage at a rate of change corresponding to the integration of the current, or the second reference voltage is changed at the rate of change to change the first reference voltage. A first additional circuit to be generated;
A timing adjustment circuit that adjusts a start timing of changing the first feedback voltage or the first reference voltage at the rate of change to a timing delayed by a predetermined time from a switching timing of the switch circuit;
An electronic device comprising: A power supply control method for switching a switch circuit to which an input voltage of a power supply is supplied according to a comparison result between a first feedback voltage corresponding to an output voltage of the power supply and a first reference voltage,
Generating a current according to a difference between the second feedback voltage and the second reference voltage according to the output voltage;
The first feedback voltage is generated by changing the second feedback voltage at a rate of change corresponding to the integration of the current, or the second reference voltage is changed at the rate of change to change the first reference voltage. generated,
A method of controlling a power supply , comprising adjusting a start timing of changing the first feedback voltage or the first reference voltage at the rate of change to a timing delayed by a predetermined time from a switching timing of the switch circuit .

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