JP5733766B2 - Data input / output control device and semiconductor memory device system - Google Patents

Description

The present invention relates to a data input / output control device and a semiconductor memory device system, and in particular, encodes data input from a host device into a predetermined error correction code and stores it in a nonvolatile semiconductor memory device and stores it in a semiconductor memory device. Data input / output control device for inputting error data to the input data and correcting the error using a predetermined error correction code and decoding and outputting the same to a host device, and a semiconductor memory provided with such a data input / output control device It relates to a device system.

Conventionally, this type of data input / output control device controls the flash memory in response to a request from the CPU. When the input data is written to the flash memory, the input data is sequentially read 512 bytes at a time. When an error occurs in the read data from the flash memory when data is encoded into a 522 byte error correction code and written to the flash memory and data is read from the flash memory, the error correction code is used to correct the error and read data There has been proposed a circuit in which an error correction circuit for decoding and outputting is output (see, for example, Non-Patent Document 1). In this apparatus, by mounting such an error correction circuit, when an error occurs in which data stored in the flash memory is inverted for some reason, the generated error can be corrected.

Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritomo, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, and Kazunori Ohuchi, `` A Compact On-Chip ECC for Low Cost Flash Memories '', IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.32, NO.5, MAY 1997

   However, in the above-described data input / output control device, since the error correction code is set to a predetermined length and the error correction code of the predetermined length is used to perform error correction of the data, the number of correctable bits is reduced. If there is an upper limit and an error occurs in the data stored in the flash memory that exceeds the upper limit of the correctable number of bits, such error cannot be corrected. As a method for correcting more errors, a method using an error correction code having a longer code length is also conceivable. In this case, however, the processing time required for encoding and decoding data in the error correction circuit increases. Or the power consumption of the error correction circuit increases.

   The main object of the data input / output control device and semiconductor memory device system of the present invention is to correct more errors when errors occur in data stored in the semiconductor memory device.

   The data input / output control device and the semiconductor memory device system of the present invention employ the following means in order to achieve the main object described above.

The first data input / output control device of the present invention comprises:
Data input from the host device is encoded into a predetermined error correction code and stored in a non-volatile semiconductor memory device, and the data stored in the semiconductor memory device is input and the predetermined data is input to the predetermined data. A data input / output control device for error correction using the error correction code and decoding and outputting to the host device,
An error correction information storage unit that stores an execution data length that is the length of data to be encoded into the predetermined error correction code and an execution code length that is the length of the predetermined error correction code; and the input data An encoding unit that sequentially reads the stored execution data lengths in sequence, encodes the read data into the predetermined error correction code of the execution code length, and outputs the encoded data to the semiconductor memory device; and A decoding unit that sequentially reads data in increments of the stored execution code length, corrects the read data with the predetermined error correction code, and decodes and outputs the decoded data to the host device; and the input data Are sequentially read for each of the stored execution code lengths, and the predetermined error correction code is applied to the read n pieces (n is an integer equal to or greater than 1). An error detection unit that detects the number of error data, which is the number of data in which an error has occurred among the read data, and one when the number of detected error data exceeds a predetermined upper limit error number Execution data length capable of correcting and detecting errors greater than the upper limit of the number of errors that can be corrected and detected with a predetermined error correction code of the execution code length, and storing the data length in the error correction information storage unit A data processing unit having a storage processing unit that stores the longer data length and the code length of the predetermined error correction code in the error correction information storage unit as the execution data length and the execution code length, respectively. An output circuit;
When a write request signal for requesting writing of data from the host device to the semiconductor memory device is input, the data input from the host device is input to the encoding unit of the data correction input / output circuit and the data correction The data correction input / output circuit and the semiconductor memory device are arranged so that the data output from the encoding unit of the input / output circuit is output to the semiconductor memory device and the output data is stored in the semiconductor memory device. When the read request signal for controlling and reading the data stored in the semiconductor memory device is input from the host device, the data stored in the semiconductor memory device is read and the read data Is input to the decoding unit of the data correction input / output circuit and output from the decoding unit of the data correction input / output circuit. The data correction input / output circuit and the semiconductor memory device are controlled so as to be output to the host device, and an erasure request signal for requesting erasure of data stored in the semiconductor memory device is input from the host device Sometimes the data stored in the semiconductor memory device is read out, and the data stored in the semiconductor memory device is erased after the read data is input to the error detection unit of the data correction input / output circuit. A control circuit for controlling the data correction input / output circuit and the semiconductor memory device;
It is a summary to provide.

   In the control device of the first semiconductor memory device of the present invention, when a write request signal for requesting data writing from the host device to the semiconductor memory device is input, the data input from the host device is the data correction input / output. Data correction input / output so that data input to the encoding unit of the circuit and output from the encoding unit of the data correction input / output circuit is output to the semiconductor memory device and the output data is stored in the semiconductor memory device The circuit and the semiconductor memory device are controlled. An encoding unit of a data correction input / output circuit sequentially reads input data for each execution data length stored therein, and encodes the read data into a predetermined error correction code having an execution code length. Output to. Thereby, the data encoded into the predetermined error correction code of the execution code length can be stored in the semiconductor memory device. Further, when a read request signal for requesting reading of data stored in the semiconductor memory device is input from the host device, the data stored in the semiconductor memory device is read and the read data is converted into a data correction input / output. The data correction input / output circuit and the semiconductor memory device are controlled so that the data input to the decoding error detection unit of the circuit and output from the decoding unit of the data correction input / output circuit is output to the host device. The decoding unit of the data correction input / output circuit to which data has been input sequentially reads the input data by the stored execution code length, and corrects and decodes the read data with a predetermined error correction code. Since the data is output to the host device, the error-corrected data can be output to the host device. When an erasure request signal for erasing data stored in the semiconductor memory device is input from the host device, the data stored in the semiconductor memory device is read and the read data is an error in the data correction input / output circuit. The data correction input / output circuit and the semiconductor memory device are controlled so that the data stored in the semiconductor memory device after being input to the detector is erased. The error detection unit of the data correction input / output circuit to which the data has been input sequentially reads the input data for each of the stored execution code lengths and reads the n data (n is an integer of 1 or more). On the other hand, the number of error data, which is the number of data in which an error has occurred among the data read by a predetermined error correction code, is detected. The storage processing unit of the data correction input / output circuit determines the number of detected error data in advance. If the number of errors exceeds the upper limit, the number of errors larger than the upper limit of the number of errors that can be corrected and detected with a predetermined error correction code of one execution code length can be corrected and detected, and the data length is stored in error correction information. The data length longer than the execution data length stored in the section and the code length of the predetermined error correction code are set as the execution data length and the execution code length, respectively. It is stored in the error correction information storage unit. When the number of detected error data exceeds the upper limit number of errors, the next time a write request signal is input, the encoding unit of the data correction input / output circuit converts the input data into a longer execution data length. The read data is sequentially read and the read data is encoded into a predetermined error correction code having a longer execution code length and output to the semiconductor memory device. Next, when a read request signal is input, the decoding unit of the data correction input / output circuit Can error-correct data with a predetermined error correction code having a longer execution code length. Thereby, more errors can be corrected. The “upper limit error count” includes an upper limit value of the number of errors that can be corrected with a predetermined error correction code having n execution code lengths, and a value slightly smaller than the upper limit value.

   In the first data input / output control apparatus of the present invention, the storage processing unit of the data correction input / output circuit stores the execution data stored when the detected number of errors exceeds the upper limit number of errors. It may be a processing unit that stores a data length of m times the length (m is an integer of 2 or more) in the error correction information storage unit as the execution data length.

The second data input / output control device of the present invention comprises:
Data input from the host device is encoded into a predetermined error correction code and stored in a non-volatile semiconductor memory device, and the data stored in the semiconductor memory device is input and the predetermined data is input to the predetermined data. A data input / output control device for error correction using the error correction code and decoding and outputting to the host device,
A write count circuit that counts the number of write erasures, which is the sum of the number of times data is written to the semiconductor memory device and the number of times data stored in the semiconductor memory device is erased;
An error correction information storage unit that stores an execution data length that is the length of data to be encoded into the predetermined error correction code and an execution code length that is the length of the predetermined error correction code; and the input data An encoding unit that sequentially reads the stored execution data lengths in sequence, encodes the read data into the predetermined error correction code of the execution code length, and outputs the encoded data to the semiconductor memory device; and A decoding unit that sequentially reads data in increments of the stored code length for execution, corrects the read data with the predetermined error correction code, decodes the decoded data, and outputs the decoded data to the host device; n (n Is a threshold value for determination, which is the number of write erasures estimated to cause more errors than a predetermined upper limit number of errors in the data of the execution code length of the value 1) When the counted number of write / erase times exceeds, an error larger than the upper limit of the number of errors that can be corrected and detected with a predetermined error correction code of one execution code length can be corrected and detected, and the data length is The error correction information with the data length longer than the execution data length stored in the error correction information storage unit and the code length of the predetermined error correction code as the execution data length and the execution code length, respectively. A data correction input / output circuit having a storage processing unit to be stored in the storage unit;
When a write request signal for requesting writing of data from the host device to the semiconductor memory device is input, the data input from the host device is input to the encoding unit of the data correction input / output circuit and the data correction The data correction input / output circuit and the semiconductor memory device are arranged so that the data output from the encoding unit of the input / output circuit is output to the semiconductor memory device and the output data is stored in the semiconductor memory device. When the read request signal for controlling and reading the data stored in the semiconductor memory device is input from the host device, the data stored in the semiconductor memory device is read and the read data Is input to the decoding unit of the data correction input / output circuit and output from the decoding unit of the data correction input / output circuit. The data correction input / output circuit and the semiconductor memory device are controlled so as to be output to the host device, and an erasure request signal for requesting erasure of data stored in the semiconductor memory device is input from the host device A control circuit for controlling the semiconductor memory device so that data stored in the semiconductor memory device is sometimes erased;
It is a summary to provide.

   In the second data input / output control device of the present invention, when a write request signal for requesting writing of data from the host device to the semiconductor memory device is input, the data input from the host device is a data correction input / output circuit. The data correction input / output circuit so that the data input to the encoding unit and output from the encoding unit of the data correction input / output circuit is output to the semiconductor memory device and the output data is stored in the semiconductor memory device And the semiconductor memory device. An encoding unit of a data correction input / output circuit sequentially reads input data for each execution data length stored therein, and encodes the read data into a predetermined error correction code having an execution code length. Output to. Thereby, the data encoded into the predetermined error correction code of the execution code length can be stored in the semiconductor memory device. Further, when a read request signal for requesting reading of data stored in the semiconductor memory device is input from the host device, the data stored in the semiconductor memory device is read and the read data is converted into a data correction input / output. The data correction input / output circuit and the semiconductor memory device are controlled so that the data input to the decoding unit of the circuit and output from the decoding unit of the data correction input / output circuit is output to the host device. The decoding unit of the data correction input / output circuit to which data has been input sequentially reads the input data by the stored execution code length, and corrects and decodes the read data with a predetermined error correction code. Since the data is output to the host device, the error-corrected data can be output to the host device. The storage processing unit of the data correction input / output circuit writes that it is estimated that more errors than a predetermined upper limit error number will occur in n pieces of execution code length data (n is an integer of 1 or more). When the number of write / erase counts exceeds the threshold value for determination, which is the number of erasures, errors greater than the upper limit of the number of errors that can be corrected and detected with a predetermined error correction code of one execution code length can be corrected and detected In the error correction, the data length is longer than the execution data length stored in the error correction information storage unit, and the code length of the predetermined error correction code is the execution data length and the execution code length, respectively. The information is stored in the information storage unit. As a result, when the number of write / erase times counted for the determination threshold is exceeded and the next write request signal is input, the encoding unit of the data correction input / output circuit uses the input data for a longer execution time. The data read sequentially by the data length is encoded into a predetermined error correction code having a longer execution code length and output to the semiconductor memory device. Next, when a write request signal is input, the data correction input / output circuit The decoding unit can error-correct data with a predetermined error correction code having a longer execution code length. Thereby, more errors can be corrected. The “upper limit error count” includes an upper limit value of the number of errors that can be corrected with a predetermined error correction code having n execution code lengths, and a value slightly smaller than the upper limit value.

   In such a second data input / output control device of the present invention, the storage processing unit of the data correction input / output circuit stores the stored execution execution time when the counted number of write / erase times exceeds the determination threshold value. The processing may be such that a data length m times the data length (m is an integer of 2 or more) is stored in the error correction information storage unit as the execution data length.

   In such a first or second data input / output control device of the present invention, the storage processing unit of the data correction input / output circuit consumes power in the data correction input / output circuit in the data correction input / output circuit. The execution code set such that the execution code length stored in the error correction information storage unit is shorter than the upper limit power allowable code length predetermined as the upper limit of the execution code length that is equal to or less than the allowable power limit. It may be a processing unit that stores the data length and the execution code length in the error correction information storage unit. The longer the code length for execution stored in the error correction information storage unit, the longer the power consumed by the data correction input / output circuit tends to be longer. Therefore, the error correction information storage unit stores the error correction information from the upper limit power allowable code length. By storing the execution data length and execution code length set so that the execution code length is shortened in the error correction information storage unit, the power consumed by the data correction input / output circuit is reduced to an allowable power level or less. It can be corrected.

   Further, in the first or second data input / output control device of the present invention, the storage processing unit of the data correction input / output circuit is configured to read data that the data correction input / output circuit can read from the semiconductor memory device per unit time. The amount of read speed is stored in the error correction information storage unit from a predetermined upper limit speed allowable code length as an upper limit of the execution code length that is equal to or lower than the allowable read speed allowed by the data correction input / output circuit. The execution data length and the execution code length set so as to shorten the execution code length can be stored in the error correction information storage unit. The longer the execution code length stored in the error correction information storage section, the slower the reading speed, so the execution code length stored in the error correction information storage section becomes shorter than the upper limit speed allowable code length. By storing the set execution data length and execution code length in the error correction information storage unit, error correction can be performed while suppressing the reading speed of the data correction input / output circuit from being slower than the allowable reading speed. it can.

   Further, in the first or second data input / output control device according to the present invention, the storage processing unit of the data correction input / output circuit may be configured such that an area of the data correction input / output circuit is allowed for the data correction input / output circuit. The execution data length set so that the execution code length stored in the error correction information storage unit is shorter than the upper limit area allowable code length predetermined as the upper limit of the execution code length that is equal to or smaller than the area, and It may be a processing unit that stores an execution code length in the error correction information storage unit. Since the area of the data correction input / output circuit tends to increase as the execution code length stored in the error correction information storage unit increases, the execution code stored in the error correction information storage unit from the upper limit area allowable code length By storing the execution data length and the execution code length set so as to shorten the code length in the error correction information storage unit, the area of the data correction input / output circuit can be reduced to an allowable area or less.

   In the first or second data input / output control device of the present invention, the semiconductor memory device stores a plurality of electron injection states as multi-value storage according to the amount of electrons injected into the floating gate, and the floating memory. The device includes a plurality of semiconductor memory elements whose deterioration tends to be accelerated as the amount of electrons injected into the gate increases. The data correction input / output circuit sequentially reads the input data by a first length. Of the read first length data, the number of high electron injection data for setting the semiconductor memory element to a state in which the amount of electrons injected into the floating gate is larger than a predetermined predetermined electron injection state. Less than the number of low electron injection data that makes the memory element in a state where the amount of electrons injected into the floating gate is smaller than the predetermined high electron injection state. A first flag having a second length is added to the encoding unit and output to the encoding unit. Of the read first length data, the number of the high electron injection data is the number of the low electron injection data. When the number exceeds, the high electron injection data is converted into the low electron injection data and the low electron injection data is converted into the high electron injection data, and the second data is converted into the second data. A second flag having a length of 3 is added and output to the encoding unit, and the third length obtained by adding the second length to the first length of the data output from the decoding unit When the data of the third length read sequentially and the third length of the read data includes the first flag, the data obtained by deleting the first flag from the data is output and the third length of the read data is output. The data is the second flag A data conversion unit that performs the data conversion on the first length of data from which the second flag has been deleted and outputs the data, and the control circuit is connected to the host device. When the write request signal is input, data input from the host device is input to the encoding unit via the data conversion unit of the data correction input / output circuit, and the read request signal is input from the host device. A circuit that controls the data correction input / output circuit and the semiconductor memory device so that the data output from the decoding unit of the data correction input / output circuit is output to the host device via the data conversion unit. It can also be. In this way, the ratio of the low electron injection data in the data stored in the semiconductor memory device can be made higher than that of the high electron injection data, so that the probability that an error occurs in the data stored in the semiconductor memory device is further reduced. be able to. In this case, the semiconductor memory element binary-stores a high electron injection state in which electrons are injected into the floating gate and a low electron injection state in which electrons are injected into the floating gate less than the high electron injection state. The high electron injection data is data for setting the semiconductor memory element in the high electron injection state, and the low electron injection data is data for setting the semiconductor memory element in the low electron injection state. It can also be. In this case, when the semiconductor element is an element that stores the high electron injection state and the low electron injection state as binary storage, the probability that an error occurs in the data stored in the semiconductor storage device can be further reduced. it can.

   Furthermore, in the first or second data input / output control device of the present invention, the predetermined error correction code may be a block code or a convolutional code. Here, the “block code” includes a BCH code, a Reed-Solomon code, and the like, and the “convolution code” includes an LDPC code and the like.

   In the first or second data input / output control device according to the present invention, the semiconductor memory device has erased data stored in the semiconductor memory device and the number of times data is written to the semiconductor memory device. The number of times of writing and erasing, which is the sum of the number of times, and the number of times of writing and erasing increase, so that the probability that an error occurs in stored data tends to increase. In this case, the semiconductor memory device is a NAND flash memory, a NOR flash memory, a phase change memory, a magnetoresistive memory, a ferroelectric memory, a resistance change memory, or a combination thereof. It can also be.

   Furthermore, in the first or second data input / output control device of the present invention, the semiconductor memory device is a device formed on a semiconductor chip different from the semiconductor chip on which the data input / output control device is formed. You can also. In this way, even if the semiconductor memory device is formed on a semiconductor chip different from the semiconductor chip on which the data input / output control device is formed, more errors can be corrected.

The semiconductor memory device system of the present invention is
A non-volatile semiconductor memory device;
The first or second data input / output control device according to any of the aspects of the present invention described above, that is, basically, a non-volatile semiconductor in which data input from the host device is encoded into a predetermined error correction code Data to be stored in the storage device and input to the data stored in the semiconductor storage device, and the input data is subjected to error correction using the predetermined error correction code and decoded and output to the host device An error correction information that is an input / output control device and stores an execution data length that is a length of data to be encoded into the predetermined error correction code and an execution code length that is a length of the predetermined error correction code A storage unit, and sequentially reading the input data for each of the stored execution data lengths, and reading the read data for the predetermined error correction of the execution code length An encoding unit that encodes the code and outputs the encoded data to the semiconductor storage device; and sequentially reads the input data in increments of the stored execution code length and causes the predetermined error correction code to error the read data A decoding unit that corrects and decodes and outputs the decoded data to the host device, and sequentially reads the input data by the stored execution code length, and reads the n pieces (n is an integer equal to or greater than 1) An error detection unit for detecting the number of error data, which is the number of data in which an error has occurred among the data read by the predetermined error correction code for the data, and a predetermined upper limit for the number of detected error data If the number of errors exceeds the number of errors that can be corrected and detected with the predetermined error correction code of one execution code length, the error is corrected. The length of the data that can be detected and the length of the data is longer than the execution data length stored in the error correction information storage unit, and the code length of the predetermined error correction code are the execution data length and the A data correction input / output circuit having a storage processing unit to be stored in the error correction information storage unit as an execution code length, and a write request signal for requesting data writing from the host device to the semiconductor storage device are input. Data input from the host device is input to the encoding unit of the data correction input / output circuit, and data output from the encoding unit of the data correction input / output circuit is output to the semiconductor memory device. Control the data correction input / output circuit and the semiconductor memory device so that the output data is stored in the semiconductor memory device When a read request signal for requesting reading of data stored in the semiconductor memory device is input from the host device, the data stored in the semiconductor memory device is read and the read data is The data correction input / output circuit and the semiconductor memory device are connected so that data input to the decoding unit of the data correction input / output circuit and output from the decoding unit of the data correction input / output circuit is output to the host device. And when an erase request signal for requesting erasure of data stored in the semiconductor memory device is input from the host device, the data stored in the semiconductor memory device is read and the read data is the data The data is stored so that the data stored in the semiconductor memory device is erased after being input to the error detection unit of the correction input / output circuit. A data correction input / output circuit and a control circuit for controlling the semiconductor memory device, the first data input / output control device of the present invention, or data input from a host device is encoded into a predetermined error correction code The data stored in the non-volatile semiconductor memory device and the data stored in the semiconductor memory device are input, the input data is error-corrected and decoded using the predetermined error correction code, and the host A data input / output control device for outputting to a device, wherein the number of times of writing and erasing is the sum of the number of times data is written to the semiconductor memory device and the number of times data stored in the semiconductor memory device is erased The number of times of writing that counts the data, the execution data length that is the length of the data to be encoded into the predetermined error correction code, and the predetermined error. An error correction information storage unit that stores an execution code length that is the length of the correction code, and sequentially reads the input data by the stored execution data length, and reads the read data of the execution code length An encoding unit that encodes the predetermined error correction code and outputs the encoded data to the semiconductor storage device; and sequentially reads the input data in units of the stored execution code length, and reads the predetermined data with respect to the read data More than the upper limit number of errors determined in advance for the decoding unit that performs error correction using an error correction code and decodes and outputs the decoded code to the host device, and n (n is an integer of 1 or more) execution code length When the counted number of write / erase times exceeds the threshold for determination that is the number of write / erase times estimated to cause an error, a predetermined error correction of one execution code length is performed. The length of the data that can correct and detect more errors than the upper limit of the number of errors that can be corrected and detected with the positive code, and the data length is longer than the execution data length stored in the error correction information storage unit, and A data processing input / output circuit that stores a code length of a predetermined error correction code in the error correction information storage unit as the execution data length and the execution code length, respectively, from the host device, When a write request signal for requesting writing of data to the semiconductor memory device is input, the data input from the host device is input to the encoding unit of the data correction input / output circuit and the code of the data correction input / output circuit The data output from the conversion unit is output to the semiconductor memory device and the output data is stored in the semiconductor memory device The data correction input / output circuit and the semiconductor memory device are controlled so that a read request signal for requesting reading of data stored in the semiconductor memory device is input from the host device and stored in the semiconductor memory device. The read data is read, the read data is input to the decoding unit of the data correction input / output circuit, and the data output from the decoding unit of the data correction input / output circuit is output to the host device. The semiconductor memory device is controlled when an erasure request signal for controlling the data correction input / output circuit and the semiconductor memory device and requesting erasure of data stored in the semiconductor memory device is input from the host device. And a control circuit for controlling the semiconductor memory device so that the data stored in the memory is erased. And we summarized in that comprising a force controller, a.

   Since the semiconductor memory device system of the present invention includes the data input / output control device of the present invention according to any one of the above-described aspects, the effect of the data input / output control device of the present invention, for example, more errors can be obtained. The same effects as those that can be corrected are produced.

   In such a semiconductor memory device system of the present invention, the semiconductor memory device is the sum of the number of times data is written to the semiconductor memory device and the number of times data stored in the semiconductor memory device is erased. It can also be a device that tends to increase the probability of errors occurring in stored data as the number of write / erase cycles increases. In this case, the semiconductor memory device is a NAND flash memory, a NOR flash memory, a phase change memory, a magnetoresistive memory, a ferroelectric memory, a resistance change memory, or a combination thereof. It can also be.

   In the semiconductor memory device system of the present invention, the semiconductor memory device and the data input / output control device may be formed on different semiconductor chips. In this way, more errors can be corrected when the semiconductor memory device and the data input / output control device are formed on different semiconductor chips.

1 is a configuration diagram showing an outline of a configuration of a flash memory system 10 equipped with a data input / output control apparatus as a first embodiment of the present invention. 4 is an explanatory diagram showing an example of data output from the data inversion circuit 28 with respect to data input from the data inversion circuit 28. FIG. 2 is a configuration diagram showing an outline of a configuration of an error correction circuit 30. FIG. It is explanatory drawing which shows the structure of the data output from the encoding part 34 when execution data length Sdata is 512 bytes and execution code length Scode is (51K bytes +104 bits). 4 is a flowchart showing an example of the operation of a storage processing unit 38. 4 is an explanatory diagram showing an example of a state in which a bit error has occurred in data stored in a flash memory 12. FIG. It is a block diagram which shows the outline of a structure of the flash memory system 110 by which the data input / output control apparatus as 2nd Example of this invention is mounted. 6 is an explanatory diagram illustrating an example of data output from the data inversion circuit 128 with respect to data input from the data inversion circuit 128. FIG. FIG. 2 is a configuration diagram showing an outline of a configuration of an error correction circuit 130. It is explanatory drawing which shows the structure of the data output from the encoding part 134 when execution data length Sdata is 512 bytes and execution code length Scode is (51K bytes +104 bits). 10 is a flowchart illustrating an example of the operation of a storage processing unit 138. It is explanatory drawing which shows the relationship between the number of errors Nerror, and the number of write-erase times Nwr. 4 is an explanatory diagram showing an example of a state in which a bit error has occurred in data stored in a flash memory 112. FIG.

   Next, the form for implementing this invention is demonstrated using an Example.

   FIG. 1 is a block diagram showing an outline of the configuration of a flash memory system 10 equipped with a data input / output control apparatus as a first embodiment of the present invention. The flash memory system 10 includes a flash memory 12 in which a plurality of silicon chips each having a NAND flash memory are stacked, and a memory controller 20 that controls the flash memory 12, and a host device 60 (for example, a personal computer). Or the like, and data input from the host device 60 in response to various control signals input from the host device 60 is stored in the flash memory 12 or data stored in the flash memory 12 Are output to the host device 60. Note that the flash memory 12 and the memory controller 20 are formed on different semiconductor chips.

   The flash memory 12 is configured as a NAND flash memory including a flash memory cell array (not shown) having a plurality of flash memory cells whose threshold voltage changes due to electron injection into the floating gate and extraction of electrons from the floating gate. In addition to the flash memory cell array, a row decoder, a column decoder, a sense amplifier, etc. (all not shown) are provided. In the flash memory 12, data is written or read in units of pages (in the embodiment, (512 bytes + 104 bits)), and data stored in units of blocks consisting of a plurality of pages (in the embodiment, 64 pages) is erased. To do. In the embodiment, the data stored in the flash memory cell is assumed that the state in which electrons are injected into the floating gate is “0”, and the electrons of the floating gate are extracted from the state of “0” when the electrons are extracted from the floating gate. It is assumed that the state in which the number is small is “1”.

   The memory controller 20 is configured as a logic circuit composed of a plurality of logic elements such as transistors, and outputs a host interface circuit 22 that outputs various control signals from the host device 60 and inputs / outputs data to / from the host device 60, and a flash memory. A memory interface circuit 24 that outputs various control signals to the memory 12 and inputs / outputs data to / from the flash memory 12, a buffer circuit 26 that temporarily stores data input to the host interface circuit 22, and data from the buffer circuit 26 Data inversion circuit 28 for outputting the data by inverting or non-inverting the data in accordance with the number of “1” data included in the stored data and adding a non-inverted flag or a conversion flag, and a data inverting circuit Data from 28 is BCH (Bose-Chaudfuri-Hocquenghem) code An error correction circuit 30 that encodes and outputs to the memory interface circuit 24, decodes data from the memory interface circuit 24, and outputs the decoded data to the data inversion circuit 28; and a control circuit 40 that controls the overall operation of the memory controller 20; .

   The data inverting circuit 28 reads data from the buffer circuit 26 by 4 bits, and when the number of “0” data included in the read 4-bit data is larger than the number of “1” data, the data “1” is read. Inverts to "0" and performs bit inversion to invert "0" data to "1" and adds an inversion flag of "1" indicating that bit inversion has been performed on the data after bit inversion When the number of “0” data included in the read 4-bit data output to the error correction circuit 30 is less than or equal to the number of “1” data, the bit inversion was not executed without executing the bit inversion. A non-inverted flag of “0” indicating this is added and output to the error correction circuit 30. FIG. 2 is an explanatory diagram illustrating an example of data output from the data inversion circuit 28 to the error correction circuit 30 with respect to the data input from the data inversion circuit 28. Also, the data from the error correction circuit 30 is read out 5 bits at a time, and when the read data includes an inversion flag, the inversion flag is deleted and bit inversion is performed on the remaining 4 bits of data. When the read data includes a non-inverted flag, 4-bit data from which the non-inverted flag has been deleted is output to the buffer circuit 26. By such an operation, the ratio of “1” data in the data output from the data inversion circuit 28 to the error correction circuit 30 can be increased. The reason for performing such an operation is as follows. In the flash memory cell, when electrons are injected into the floating gate, the gate insulating film deteriorates due to stress when the electrons pass through the gate insulating film of the flash memory cell. Therefore, it is considered that the more data “0” is, the higher the probability that an error occurs in the data stored in the flash memory cell. In addition, when data is held, electrons injected into the floating gate may flow out and cause an error. Therefore, it is considered that the more data “0”, the higher the probability that an error will occur in the data. Therefore, in the flash memory cell, it is considered that storing “1” data has a lower probability of causing an error by storing “0” data. Therefore, “1” in the data output from the data inversion circuit 28 is considered to be low. The percentage of “” data was increased. Such a data inverting circuit 28 can further reduce the probability that an error will occur in the data stored in the flash memory 12.

   FIG. 3 is a configuration diagram showing an outline of the configuration of the error correction circuit 30. The error correction circuit 30 is configured as a logic circuit including a plurality of logic elements such as transistors, and the execution code length Scode which is the size of the BCH code used for data encoding and decoding and the BCH of the execution code length Scode. The correction information storage unit 32 that stores the execution data length Sdata that is the size of the data to be encoded into the code, and the execution code length stored in the correction information storage unit 32 that is the data input from the data inversion circuit 28 An encoding unit 34 that encodes and outputs the BCH code of the code, and outputs the data input from the flash memory 12 using the BCH code and outputs to the data inversion circuit 28, and an error among the data input from the flash memory 12 And a correction information storage unit 32. A storage processing unit 38 for changing the stored execution code length Scode and the execution data length Sdata, and a.

   The encoding unit 34 reads the data input from the data inverting circuit 28 for each execution data length Sdata stored in the correction information storage unit 32, and reads the read execution data length Sdata data into a BCH code generator polynomial. The parity bit to be added for encoding into the BCH code of the execution code length Scode is generated by the arithmetic processing using the data, and the data with the generated parity bit added to the read data of the execution data length Sdata is a memory interface. Output to the circuit 24. FIG. 4 is an explanatory diagram showing the structure of data output from the encoding unit 34 when the execution data length Sdata is 512 bytes and the execution code length Scode is (512 bytes + 104 bits). In addition, since the calculation process at the time of encoding data using the production | generation polynomial of a BCH code | symbol is known, detailed description is abbreviate | omitted.

   The decoding error number detection unit 36 reads the data input from the flash memory 12 through the memory interface circuit 24 for each execution code length Scode stored in the correction information storage unit 32, and reads the read execution code length Scode. The bit position where an error (hereinafter referred to as “bit error”) in which the read data is different from the encoded data is detected by a syndrome calculation process using a BCH code generator polynomial for the data. The error correction is executed, the parity bit is deleted from the data subjected to the error correction, the data is decoded and output to the data inversion circuit 28. By such an operation, it is possible to perform error correction on the data input from the flash memory 12 and decode and output the data. Also, the decoding error number detection unit 36 detects n bit positions (where n is n) when detecting the bit position where the bit error has occurred using the BCH code generation polynomial for the read data of the execution code length Scode. The number of bits of data in which a bit error has occurred among the data of the execution code length Scode of an integer of 1 or more is detected as the error data number Nerror. Here, the value n, which is the number of code length codes for execution when detecting the number of error data Nerror, is set as appropriate through experiments and analysis. In addition, since the calculation process at the time of error correction by the syndrome calculation process using the generator polynomial of a BCH code is known, detailed description is abbreviate | omitted.

   FIG. 5 is a flowchart illustrating an example of the operation of the storage processing unit 38. The storage processing unit 38 includes the number of error data detected by the decoding error number detection unit 36 and the number of data errors that can be detected by the BCH code of the n execution code lengths Scode stored in the correction information storage unit 32. Is compared with the upper limit error number Nmax, which is the upper limit (step S100). Here, the upper limit error number Nmax is an upper limit of the number of errors that can be detected by n BCH codes whose data length is the execution data Sdata and whose code length is the execution code length Scode, for example, 512 bytes. Since the upper limit of the number of errors that can be detected by one BCH code is 8 bits in n BCH codes with a code length of (512 bytes + 104 bits) obtained by adding 104 bits of parity bits to the data of the upper limit number of errors Nmax The number of errors that can be detected by one BCH code is 15 for n BCH codes having a code length of (1 K bytes + 210 bits) obtained by adding 210 bits of parity bits to n × 8 bits and 1 K bytes of data. Since this is a bit, the upper limit error number Nmax is assumed to be n × 15 bits.

   When the error data number Nerror exceeds the upper limit error number Nmax (step S100), the data length twice the execution data length Sdata stored in the correction information storage unit 32 is stored as the execution data length Sdata. A code length Scref longer than the execution data length Sdata and capable of detecting more errors than the upper limit error number Nmax is stored in the correction information storage unit 32 as an execution code length Scode (step S110), and the error data number Nerror is the upper limit error number. If it is equal to or less than Nmax (step S100), the process ends without changing the execution code length Scode and the execution data length Sdata stored in the correction information storage unit 32. Thereby, when the error data number Nerror exceeds the upper limit error number Nmax, the long execution data length Sdata and the execution code length Scode are stored in the correction information storage unit 32. For example, if 512 bytes as the execution data length Sdata and (512 bytes + 104 bits) as the execution code length Scode are stored in the correction information storage unit 32 before the process of step S110 is executed, step S110 is executed. After the above process is executed, the correction information storage unit 32 stores 1K bytes as the execution data length Sdata and (1K bytes + 210 bits) as the execution code length Scode.

   Various control signals are input to the control circuit 40 from the host device via the host interface circuit 22, and various signals indicating the state of the flash memory 12 are input from the flash memory 12 via the memory interface circuit 24. Control signals for controlling the buffer circuit 26, the data inverting circuit 28, the error correction circuit 30, and the flash memory 12 are output from 40.

   In the thus configured flash memory system 10 of the embodiment, the host interface circuit 22 includes a write request signal for requesting writing of data from the host device 60 to the flash memory 12 and an address signal indicating an address for writing data to the flash memory 12. Is input to the control circuit 40 via the memory interface circuit 24 via the host interface circuit 22, the buffer circuit 26, the data inversion circuit 28, and the error correction circuit 30. The host interface circuit 22, the buffer circuit 26, the data inversion circuit 28, the error correction circuit 30, and the memory interface circuit 24 are controlled so as to be output to the flash memory 12. The data inverting circuit 28 to which data is input from the buffer circuit 26 reads the data from the buffer circuit 26 by 4 bits, and the number of “1” data included in the read 4-bit data is “0”. An inversion flag or non-inversion flag is added based on the number, and 5-bit data is input to the encoding unit 34 of the error correction circuit 30. The encoding unit 34 of the error correction circuit 30 to which data has been input sequentially reads the input data for each execution data length Sdata, encodes it into a BCH code of the execution code length Scode, and outputs it to the memory interface circuit 24. The control circuit 40 causes the flash memory 12 to be stored in the flash memory 12 in units of pages from the memory interface circuit 24 via the error correction circuit 30 as described above into the BCH code having the execution code length Scode. Control. Thereby, when the write request signal is input, the data encoded into the BCH code of the execution code length Scode can be stored in the flash memory 12.

   Further, a read request signal for requesting reading of data stored in the flash memory 12 from the host device 60 and an address signal indicating a read destination address of the flash memory 12 are input to the control circuit 40 via the host interface circuit 22. Then, the control circuit 40 controls the flash memory 12 so that data is read from the flash memory 12 in units of pages. Then, the control circuit 40 allows the data read from the flash memory 12 to be output from the host interface circuit 22 to the host device 60 via the memory interface circuit 24, the error correction circuit 30, the data inversion circuit 28, and the buffer circuit 26. The interface circuit 22, buffer circuit 26, data inversion circuit 28, error correction circuit 30, and memory interface circuit 24 are controlled. The decoding error number detection unit 36 of the error correction circuit 30 to which data is input reads the input data for each execution code length Scode, and there is data in which a bit error has occurred among the data read using the BCH code. For example, the data of execution data length Sdata decoded after error correction is input to the data inversion circuit 28. If no bit error occurs in the read data, the data of execution data length Sdata obtained by decoding the read data is input. The data is input to the data inversion circuit 28. The data inverting circuit 28 to which the data is input reads the data 5 bits at a time, and when the read data includes the inverted bit, the bit inversion is executed and the 4-bit data in which the inverted bit is deleted is input to the buffer circuit 26. When the read data includes non-inverted bits, 4-bit data from which the non-inverted bits are deleted is output to the buffer circuit 26. As a result, when a read request signal is input, if a bit error occurs in the data stored in the flash memory 12, the error can be corrected and output to the host device 60. The probability of a bit error occurring in the read data can be reduced, and the reliability of the flash memory system 10 can be improved.

   When an erasure request signal for requesting erasure of data stored in the flash memory 12 from the host device 60 and a block information signal indicating information on a block to be erased are input to the control circuit 40 via the host interface circuit 22 The control circuit 40 first controls the flash memory 12 so that data is read from the area of the flash memory 12 corresponding to the block to be erased. Then, the error correction circuit 30 and the memory interface circuit 24 are controlled so that the data read from the flash memory 12 is input to the decoding error number detection unit 36 of the error correction circuit 30 via the memory interface circuit 24, and then the flash memory The flash memory 12 is controlled so that the data stored in the 12 blocks to be erased is erased. The decoding error number detection unit 36 of the error correction circuit 30 to which data has been input generates BCH codes for the n pieces of execution code length Scode that have been read by reading the input data for each execution code length Scode. Using the polynomial, the number of error data Nerror, which is the number of bits of data in which an error has occurred, among the data of the execution code length Scode is detected and output to the storage processing unit 38. The storage processing unit 38 compares the error data number Nerror and the upper limit error number Nmax. When the error data number Nerer exceeds the upper limit error number Nmax, the execution data length Sdata stored in the correction information storage unit 32 is stored. Is stored as the execution data length Sdata, and the code length capable of detecting more errors than the value near the upper limit of the number of errors detectable with the execution data length Sdata is corrected as the execution code length Scode. The information is stored in the information storage unit 32. Next, the reason for performing such processing will be described.

   FIG. 6 is an explanatory diagram showing an example of a state in which a bit error has occurred in the data stored in the flash memory 12. Here, for the sake of explanation, it is assumed that the number of error data Nerror is detected for one piece of code of execution code length Scode. In the figure, the “x” mark indicates the position of data where a bit error has occurred. Here, for the sake of explanation, 512 bytes as the execution data length Sdata and (512 bytes + 104 bits) as the execution code length Scode are stored in the correction information storage unit 32 of the error correction circuit 30 first. A 9-bit bit error occurs in the data of the execution code length Scode (512 bytes + 104 bits) read out from the memory 12, and the data of the execution code length Scode (512 bytes + 104 bits) read out from the flash memory 12 next. Assume that a 2-bit bit error has occurred. When the erasure request signal is input, data of the execution code length Scode (512 bytes + 104 bits) is input to the decoding error number detection unit 36 of the error correction circuit 30. In this BCH code, correction is possible up to a bit error of 8 bits (the upper limit error number Nmax is 8), but a 9-bit bit error has occurred in the first read data, so the code length is (512 bytes). With the (+104 bit) BCH code, the error correction circuit 30 cannot perform error correction. In the error correction circuit 30 of the embodiment, when the detected error data number Nerror exceeds the upper limit error number Nmax, the correction information storage unit 32 stores 1K bytes as the execution data length Sdata and (1K as the execution code length Scode). (Byte + 210 bits) is stored, the next time a write request signal is input, a BCH code having a code length of 1K bytes and a parity bit of 210 bits (1K bytes + 210 bits) is stored in the flash memory 12. When the data is stored and read from the flash memory 12, the data is read as a BCH code having a code length of (1K bytes + 210 bits). At this time, as shown in the figure, an 11-bit bit error has occurred in the read data, but a bit error of up to 15 bits can be corrected with a BCH code having a code length of (1 Kbyte + 210 bits). , You will be able to correct these errors. In this way, when the detected error data number Nerror exceeds the upper limit error number Nmax, the execution data length Sdata and the execution code length Scode stored in the correction information storage unit 32 are made longer. More errors can be corrected.

   According to the flash memory system 10 of the first embodiment described above, when an erase request signal is input from the host device 60, the data stored in the flash memory 12 is read and the read data is stored in the error correction circuit 30. The memory interface circuit 24, the error correction circuit 30, and the flash memory 12 are controlled so that the data stored in the flash memory 12 after being input to the decoding error number detection unit 36 is erased. The decoding error number detection unit 36 of the error correction circuit 30 to which the data has been input detects the error data number Nerror, and the storage processing unit 38 of the error correction circuit 30 determines that the detected error data number Ner has the upper limit error number Nmax. When the number exceeds the upper limit error number Nmax, the data length becomes longer than the execution data length Sdata stored in the correction information storage unit 32 and the code length of the BCH code. Since the execution data length Sdata and the execution code length Scode are stored in the correction information storage unit 32, the next time a write request signal is input, the encoding unit 34 of the error correction circuit 30 further receives the input data. Long execution data length Sdata is read sequentially and the read data is used for longer execution When a read request signal is input next after being encoded and output into a BCH code with a code length Scode, the decoding error number detection unit 36 of the error correction circuit 30 outputs data with a BCH code with a longer execution code length Scod. Error correction can be performed. Thereby, more errors can be corrected. The data inverting circuit 28 reads data from the buffer circuit 26 bit by bit, and when the number of “0” data included in the read 4-bit data is larger than the number of “1” data, the data inverting circuit 28 is “1”. Inverts data to “0” and performs bit inversion to invert “0” data to “1”, adds an inversion flag of “1” and outputs it to the error correction circuit 30, and reads the read 4-bit When the number of “0” data included in the data is less than or equal to the number of “1” data, a bit inversion is not performed and a “0” non-inversion flag is added to indicate that the bit inversion has not been performed. To the error correction circuit 30. Thereby, the probability that an error will occur in the data stored in the flash memory 12 can be further reduced.

   In the flash memory system 10 of the first embodiment, the memory controller 20 controls a NAND flash memory including a flash memory cell array having a plurality of flash memory cells. However, as the memory controlled by the memory controller 20, the NAND The present invention is not limited to the type flash memory, and a NOR type flash memory may be controlled. The memory controlled by the memory controller 20 is not limited to such a flash memory, and may be any nonvolatile memory, for example, a phase for storing data by changing the crystal structure of the material. A magnetoresistive memory that stores data using a change memory or an electron spin as a memory element, and stores positive / negative spontaneous polarization corresponding to 1 and 0 using a hysteresis (history phenomenon) of a ferroelectric substance. Non-volatile memory that tends to increase the probability that errors will occur in the stored data, such as ferroelectric memory, resistance change memory that stores data using changes in electrical resistance due to voltage application, etc. There may be.

   FIG. 7 is a block diagram showing an outline of the configuration of the flash memory system 110 on which the data input / output control apparatus according to the second embodiment of the present invention is mounted. The flash memory system 110 includes a flash memory 112 in which a plurality of silicon chips each having a NAND flash memory are stacked, and a memory controller 120 that controls the flash memory 112. A host device 160 (for example, a CPU ( Data input from the host device 160 in accordance with various control signals input from the Centoral Processing Unit), etc., and the data stored in the flash memory 112 is output to the host device 160. To do. It is assumed that the flash memory 112 and the memory controller 120 are formed on individual semiconductor chips.

   The flash memory 112 is configured as a NAND flash memory including a flash memory cell array (not shown) having a plurality of flash memory cells whose threshold voltage changes by electron injection into or extraction from the floating gate. In addition to the flash memory cell array, a row decoder, a column decoder, a sense amplifier, etc. (all not shown) are provided. In the flash memory 112, data is written or read in page units (in the embodiment, (512 bytes + 104 bits)), and data stored in block units (64 pages in the embodiment) consisting of a plurality of pages is erased. To do. In the embodiment, the data stored in the flash memory cell is assumed to be “0” when electrons are injected into the floating gate, and “1” when electrons are extracted from the floating gate. .

   The memory controller 120 is configured as a logic circuit composed of a plurality of logic elements such as transistors. The memory controller 120 outputs various control signals from the host device 160 and inputs / outputs data to / from the host device 160, and a flash memory. A memory interface circuit 124 that outputs various control signals to the memory 112 and inputs / outputs data to / from the flash memory 112, a buffer circuit 126 that temporarily stores data input to the host interface circuit 122, and data from the buffer circuit 126 Data inversion circuit 128 that inverts or non-inverts data according to the number of “1” data contained in the stored data and adds a non-inversion flag or conversion flag and outputs the data, and flash memory 112 Write data to The data from the write / erase number counting circuit 129 that counts the number of times and the data from the data inversion circuit 128 are encoded with a BCH (Bose-Chaudfuri-Hocquenghem) code and output to the memory interface circuit 124 or the data from the memory interface circuit 124 is decoded. Then, an error correction circuit 130 that outputs to the data inversion circuit 128 and a control circuit 140 that controls the overall operation of the memory controller 120 are provided.

   The data inversion circuit 128 reads data from the buffer circuit 126 four bits at a time. When the number of “0” data included in the read 4-bit data is larger than the number of “1” data, the data “1” is read. Inverts to "0" and performs bit inversion to invert "0" data to "1" and adds an inversion flag of "1" indicating that bit inversion has been performed on the data after bit inversion When the number of “0” data included in the read 4-bit data output to the error correction circuit 130 is equal to or less than the number of “1” data, the bit inversion was not executed without executing the bit inversion. A non-inversion flag of “0” indicating this is added and output to the error correction circuit 130. FIG. 8 is an explanatory diagram showing an example of data output from the data inversion circuit 128 to the error correction circuit 130 with respect to the data input from the data inversion circuit 128. Also, the data from the error correction circuit 130 is read 5 bits at a time, and when the read data includes an inversion flag, the inversion flag is deleted and bit inversion is performed on the remaining 4 bits of data. When the read data includes a non-inverted flag, 4-bit data from which the non-inverted flag is deleted is output to the buffer circuit 126. With this operation, the ratio of “1” data in the data output from the data inversion circuit 128 to the error correction circuit 130 can be increased. The reason for performing such an operation is as follows. In the flash memory cell, when electrons are injected into the floating gate, the gate insulating film deteriorates due to stress when the electrons pass through the gate insulating film of the flash memory cell. Therefore, it is considered that the more data “0” is, the higher the probability that an error occurs in the data stored in the flash memory cell. In addition, when data is held, electrons injected into the floating gate may flow out and cause an error. Therefore, it is considered that the more data “0”, the higher the probability that an error will occur in the data. Therefore, in the flash memory cell, it is considered that storing “1” data has a lower probability of causing an error by storing “0” data. Therefore, “1” in the data output from the data inversion circuit 128 is considered to be low. The percentage of “” data was increased. Such a data inversion circuit 128 can further reduce the probability that an error will occur in the data stored in the flash memory 112.

   The write / erase count circuit 129 counts the write / erase number Nwr, which is the sum of the number of times data is written to the flash memory 112 for each page and the number of times data is erased, and outputs the count to the error correction circuit 130. Here, it is assumed that the information of the page in which the data of the flash memory 12 is written and the information of the block from which the data is erased are input from the control circuit 40.

   FIG. 9 is a configuration diagram showing an outline of the configuration of the error correction circuit 130. The error correction circuit 130 is configured as a logic circuit including a plurality of logic elements such as transistors, and the execution code length Scode which is the size of the BCH code used for data encoding and decoding and the BCH of the execution code length Scode. The correction information storage unit 132 that stores the execution data length Sdata that is the size of the data to be encoded into the code, and the execution code length that is stored in the correction information storage unit 132 with the data input from the data inversion circuit 128 An encoding unit 134 that encodes and outputs a BCH code of the code, a decoding unit 136 that decodes data input from the flash memory 112 using the BCH code and outputs the decoded data to the data inversion circuit 128, and an error correction circuit 130 The execution information stored in the correction information storage unit 132 based on the number of write times Nwr A storage processing unit 138 for changing the issue length Scode and the execution data length Sdata, and a.

   The encoding unit 134 reads the data input from the data inverting circuit 128 for each execution data length Sdata stored in the correction information storage unit 132, and reads the read execution data length Sdata data into a BCH code generator polynomial. The parity bit to be added for encoding into the BCH code of the execution code length Scode is generated by the arithmetic processing using the data, and the data with the generated parity bit added to the read data of the execution data length Sdata is a memory interface. Output to the circuit 124. FIG. 10 is an explanatory diagram showing the structure of data output from the encoding unit 134 when the execution data length Sdata is 512 bytes and the execution code length Scode is (512 bytes + 104 bits). In addition, since the calculation process at the time of encoding data using the production | generation polynomial of a BCH code | symbol is known, detailed description is abbreviate | omitted.

   The decoding unit 136 reads the data input from the flash memory 112 via the memory interface circuit 124 for each execution code length Scode stored in the correction information storage unit 132, and reads the data of the read execution code length Scode. The error calculation is performed by detecting the bit position where an error (hereinafter referred to as “bit error”) in which the read data is different from the encoded data is detected by the syndrome calculation process using the BCH code generator polynomial. Then, the parity bit is deleted from the data that has been subjected to error correction, and the data is decoded and output to the data inversion circuit 128. By such an operation, it is possible to perform error correction on the data input from the flash memory 112, decode it, and output it. In addition, since the calculation process at the time of error correction by the syndrome calculation process using the generator polynomial of a BCH code is known, detailed description is abbreviate | omitted.

   FIG. 11 is a flowchart illustrating an example of the operation of the storage processing unit 138. The storage processing unit 138 compares the write / erase number Nwr input from the write / erase number counting circuit 129 with the determination threshold value Nref (step S200). The determination threshold Nref is the number of errors Nerror, which is the number of bit errors occurring in the BCH code data of the execution code length Scode (n is an integer of 1 or more) stored in the flash memory 12, and the write erasure The upper limit of the number of data errors that can be detected by a BCH code of n execution code lengths Scode stored in the correction information storage unit 132 by previously obtaining a relationship with the number of times Nwr as a map by experiment, analysis, or the like The upper limit error number Nmax is set as the error number Error, and is set as the write / erase number Nwr corresponding to the error number Error. FIG. 12 is an explanatory diagram showing the relationship between the number of errors Nerror and the number of write / erase times Nwr. The number of errors Nero and the number of write / erase times Nwr are as shown in the figure because in the flash memory 12, generally, the larger the number of write / erase times Nwr to the flash memory cell, the more the gate insulating film of the flash memory cell deteriorates. This is because the number of errors Nerror increases as the number of write / erase times Nwr to the flash memory cell increases. The upper limit error number Nmax is determined based on the execution code length Scode, and is 1 for n BCH codes having a code length of (512 bytes + 104 bits) obtained by adding 104 parity bits to 512-byte data. Since the upper limit of the number of errors that can be detected by the BCH code is 8 bits, the upper limit error number Nmax is n × 8 bits, and the code length obtained by adding 210-bit parity bits to 1-Kbyte data is (1 Kbyte + 210 bits) Since the upper limit of the number of errors that can be detected by one BCH code is 15 bits in the n BCH codes, the upper limit error number Nmax is assumed to be n × 15 bits.

   When the write / erase count Nwr exceeds the determination threshold Nref (step S200), a data length twice the execution data length Sdata stored in the correction information storage unit 132 is stored as the execution data length Sdata. A code length Scref longer than the execution data length Sdata and capable of detecting more errors than the upper limit error number Nmax is stored in the correction information storage unit 132 as an execution code length Scode (step S210), and the number of write erasures Nwr is a determination threshold value. When it is equal to or smaller than Nref (step S200), the process is terminated without changing the execution code length Scode and the execution data length Sdata stored in the correction information storage unit 132. Thereby, when the error data number Nerror exceeds the upper limit error number Nmax, the long execution data length Sdata and the execution code length Scode are stored in the correction information storage unit 132. For example, when the correction information storage unit 132 stores 512 bytes as the execution data length Sdata and (512 bytes + 104 bits) as the execution code length Scode before the process of step S210 is executed, step S210 is performed. After executing the above process, the correction information storage unit 132 stores 1K bytes as the execution data length Sdata and (1K bytes + 210 bits) as the execution code length Scode.

   Various control signals are input to the control circuit 140 from the host device via the host interface circuit 122 and various signals indicating the state of the flash memory 112 are input from the flash memory 112 via the memory interface circuit 124. From 140, information on the page in which the data of the flash memory 12 is written, information on the block from which the data has been erased, and control signals for controlling the buffer circuit 126, the data inversion circuit 128, the error correction circuit 130, and the flash memory 112 are provided. It is output.

   In the flash memory system 110 of the embodiment thus configured, the host interface circuit 122 includes a write request signal for requesting data writing from the host device 160 to the flash memory 112 and an address signal indicating an address for writing data to the flash memory 112. Is input to the control circuit 140 via the memory interface circuit 124 via the host interface circuit 122, the buffer circuit 126, the data inversion circuit 128, and the error correction circuit 130. The host interface circuit 122, the buffer circuit 126, the data inversion circuit 128, the error correction circuit 130, and the memory interface circuit 124 are controlled so as to be output to the flash memory 112. The data inversion circuit 128 to which data is input from the buffer circuit 126 reads the data from the buffer circuit 126 by 4 bits, and the number of “1” data included in the read 4-bit data is “0”. An inversion flag or non-inversion flag is added based on the number, and 5-bit data is input to the encoding unit 134 of the error correction circuit 130. The encoding unit 134 of the error correction circuit 130 to which data is input sequentially reads the input data for each execution data length Sdata, encodes it into a BCH code having the execution code length Scode, and outputs the BCH code to the memory interface circuit 124. In this way, the control circuit 140 stores the flash memory 112 so that the data encoded into the BCH code of the execution code length Scode from the memory interface circuit 124 via the error correction circuit 130 is stored in the flash memory 112 in units of pages. Control. Thereby, when the write request signal is input, the data encoded into the BCH code of the execution code length Scode can be stored in the flash memory 112.

   Further, a read request signal for requesting reading of data stored in the flash memory 112 from the host device 160 and an address signal indicating a read destination address of the flash memory 112 are input to the control circuit 140 via the host interface circuit 122. Then, the control circuit 140 controls the flash memory 112 so that data is read from the flash memory 112 in units of pages. Then, the control circuit 140 allows the data read from the flash memory 112 to be output from the host interface circuit 122 to the host device 160 via the memory interface circuit 124, the error correction circuit 130, the data inversion circuit 128, and the buffer circuit 126. It controls the interface circuit 122, the buffer circuit 126, the data inversion circuit 128, the error correction circuit 130, and the memory interface circuit 124. The decoding unit 136 of the error correction circuit 130 to which data has been input reads the input data for each execution code length Scode, and corrects errors if there is data in which a bit error occurs among the data read using the BCH code. The data of the execution data length Sdata decoded after executing the above is input to the data inversion circuit 128. If no bit error occurs in the read data, the data of the execution data length Sdata obtained by decoding the read data is input to the data inversion circuit. Input to 128. The data inversion circuit 128 to which data is input reads the data bit by bit, and when the read data includes the inversion bit, the bit inversion is executed and the 4-bit data in which the inversion bit is deleted is input to the buffer circuit 126. When the read and read data includes non-inverted bits, 4-bit data from which the non-inverted bits are deleted is output to the buffer circuit 126. As a result, when a read request signal is input, if a bit error occurs in the data stored in the flash memory 112, the error can be corrected and output to the host device 160. The probability that a bit error will occur in the read data can be reduced, and the reliability of the flash memory system 110 can be improved.

   Further, an erase request signal for requesting erasure of data stored in the flash memory 112 from the host device 160 and a block information signal indicating information on a block to be erased are input to the control circuit 140 via the host interface circuit 122. When this happens, the control circuit 140 controls the flash memory 112 so that data is read from the area of the flash memory 112 corresponding to the block to be erased.

   In the flash memory system 110 configured as described above, when the write / erase number Nwr counted by the write / erase number counting circuit 129 exceeds the determination threshold value Nref, the storage processing unit 138 of the error correction circuit 130 stores the correction information storage unit 132. The data length twice the stored execution data length Sdata is stored as the execution data length Sdata, and the execution code length Scode stored longer than the previously stored execution data length Sdata is stored. A code length capable of detecting more errors than a value near the upper limit of the number of errors detectable with the BCH code is stored in the correction information storage unit 132 as an execution code length Scode. FIG. 13 is an explanatory diagram showing an example of a state in which a bit error has occurred in the data stored in the flash memory 112. Here, for the sake of explanation, it is assumed that the number of error data Nerror is detected for one piece of code of execution code length Scode. In the figure, the “x” mark indicates the position of data where a bit error has occurred. Here, for explanation, 512 bytes as the execution data length Sdata and (512 bytes + 104 bits) as the execution code length Scode are first stored in the correction information storage unit 132 of the error correction circuit 130. A 9-bit bit error occurs in the data of the execution code length Scode (512 bytes + 104 bits) read from the memory 112, and the data of the execution code length Scode (512 bytes + 104 bits) read from the flash memory 112 is then generated. Assume that a 2-bit bit error has occurred. When a read request signal is input, first, data of an execution code length Scode (512 bytes + 104 bits) is input to the decoding unit 136 of the error correction circuit 130. In this BCH code, correction is possible up to a bit error of 8 bits (the upper limit error number Nmax is 8), but a 9-bit bit error has occurred in the first read data, so the code length is (512 bytes). With the (+104 bit) BCH code, the error correction circuit 130 cannot perform error correction. In the error correction circuit 130 according to the embodiment, when the write / erase number Nwr counted by the write / erase number counting circuit 129 exceeds the determination threshold Nref, the correction information storage unit 132 stores 1 Kbyte as the execution data length Sdata, and the execution code. Since (1K bytes + 210 bits) is stored as the length Scode, the next time a write request signal is input, a BCH code having a code length of 1K bytes and a parity bit of 210 bits (1K bytes + 210 bits) is used. Is stored in the flash memory 112, and when data is read from the flash memory 112, the data is read as a BCH code having a code length of (1K bytes + 210 bits). At this time, as shown in the figure, an 11-bit bit error has occurred in the read data, but a bit error of up to 15 bits can be corrected with a BCH code having a code length of (1 Kbyte + 210 bits). , You will be able to correct these errors. As described above, when the write / erase number Nwr counted by the write / erase number counting circuit 129 exceeds the determination threshold Nref, the execution data length Sdata and the execution code length Scode stored in the correction information storage unit 132 are By making the length longer, more errors can be corrected.

   According to the flash memory system 110 of the second embodiment described above, when the write / erase number Nwr counted by the write / erase number counting circuit 129 exceeds the determination threshold Nref, the storage processing unit 138 of the error correction circuit 130 The length of the data that can detect an error larger than the upper limit error number Nmax and the data length is longer than the execution data length Sdata stored in the correction information storage unit 132 and the code length of the BCH code are respectively executed data. Since the correction information storage unit 132 stores the length Sdata and the execution code length Scode, when the next write request signal is input, the encoding unit 134 of the error correction circuit 130 uses the input data for longer execution. Data length Sdata is read sequentially and the read data is for longer execution When a read request signal is input next after being encoded into a BCH code with a code length Scode and output, the decoding unit 136 of the error correction circuit 130 performs error correction on the data with a BCH code with a longer execution code length Scod. be able to. Thereby, more errors can be corrected. The data inversion circuit 128 reads out data from the buffer circuit 126 bit by bit, and when the number of “0” data included in the read 4-bit data is larger than the number of “1” data, the data inversion circuit 128 is “1”. Inverts data to “0” and performs bit inversion to invert “0” data to “1” and adds an inversion flag of “1” to the error correction circuit 130 to output the read 4-bit When the number of “0” data included in the data is less than or equal to the number of “1” data, a bit inversion is not performed and a “0” non-inversion flag is added to indicate that the bit inversion has not been performed. To the error correction circuit 130. Thereby, the probability that an error will occur in the data stored in the flash memory 112 can be further reduced.

   In the flash memory system 110 of the second embodiment, the memory controller 20 controls a NAND flash memory including a flash memory cell array having a plurality of flash memory cells. However, as the memory controlled by the memory controller 20, the NAND The present invention is not limited to the type flash memory, and a NOR type flash memory may be controlled. Further, the memory controlled by the memory controller 20 is not limited to such a flash memory, and any non-volatile memory that tends to increase the probability that an error occurs in the stored data depending on the number of write / erase times. However, for example, a phase change memory that stores data by changing the crystal structure of the material, a magnetoresistive memory that stores data using the spin of electrons as a memory element, and hysteresis (history phenomenon) of ferroelectrics It may be a ferroelectric memory that stores data by using positive and negative spontaneous polarizations corresponding to 1 and 0, or a resistance change memory that stores data by using a change in electrical resistance caused by application of a voltage. .

In the flash memory systems 10 and 110 of the first and second embodiments, the upper limit error number Nmax can be detected by n BCH codes whose data length is the execution data Sdata and whose code length is the execution code length Scode. Although the upper limit of the number of errors is assumed, it may be a value slightly smaller than the upper limit of the number of errors. For example, in the case of n BCH codes having a code length of (512 bytes + 104 bits) obtained by adding 104 parity bits to 512-byte data, the upper limit of the number of errors that can be detected by one BCH code is 8 bits. Therefore, it is desirable that the upper limit error number Nmax is smaller than n × 8 bits by several bits to 10 and several bits, and the code length obtained by adding 210-bit parity bits to 1-Kbyte data is (1 Kbyte + 210 bits). Since the upper limit of the number of errors that can be detected by one BCH code is 15 bits in each BCH code, it is desirable that the upper limit error number Nmax is smaller than n × 15 bits by several bits to 10 or more bits.

   In the flash memory systems 10 and 110 of the first and second embodiments, the data length and BCH code that are longer than the execution data length Sdata stored in the correction information storage units 32 and 132 in the storage processing units 38 and 138 Are stored in the correction information storage units 32 and 132 as the execution data length Sdata and the execution code length Scode, respectively, so that the code length is less than the upper limit execution code length Scmax that is the upper limit of the execution code length The data length Sdata and the execution code length Scode may be determined and stored in the correction information storage units 32 and 132. In this case, the upper limit execution code length Scmax is set to the execution code length Scode, the host interface circuit 22, the buffer circuit 26, and the data inversion circuit in which the power consumption of the error correction circuit 30 is less than the allowable power allowed by the error correction circuit 30. 28, the error correction circuit 30, and the memory interface circuit 24, the power consumption of the execution code length Scode in which the power consumption of the circuit combined with these is less than the allowable power allowed for the circuit combining them, and the power consumption of the memory controller 20 It may be set to an execution code length Scode that is equal to or less than an allowable allowable power. This setting is made because the power consumption of the error correction circuit 30 increases as the execution code length Scode becomes longer. Therefore, the power consumption of the error correction circuit 30, the host interface circuit 22, the buffer circuit 26, the data inversion circuit 28, This is based on the fact that the power consumption of the circuit combining the error correction circuit 30 and the memory interface circuit 24 and the power consumption of the memory controller 20 tend to increase. In this way, the power consumption of the error controller 30, the host interface circuit 22, the buffer circuit 26, the data inversion circuit 28, the error correction circuit 30, and the memory interface circuit 24, and the power consumption of the memory controller 20 are allowed. Exceeding power can be suppressed. Further, the upper limit execution code length Scmax is set such that the read speed, which is the amount of data by which the memory interface circuit 24 can read data from the flash memory 12 per unit time, is less than or equal to the allowable read speed allowed by the memory interface circuit 24. The code length Scode may be set. This setting is based on the tendency that the reading speed in the memory interface circuit 24 tends to be slower as the execution code length Scode becomes longer. In this way, it is possible to suppress the reading speed of data from the flash memory 12 from being lower than the allowable reading speed. Further, the upper limit execution code length Scmax is set so that the execution code length Scode, the host interface circuit 22, the buffer circuit 26, the data inversion circuit 28, and the like are such that the area of the error correction circuit 30 is less than or equal to the allowable area allowed by the error correction circuit 30 The code length Scode for execution in which the area of the circuit combining the error correction circuit 30 and the memory interface circuit 24 is less than or equal to the allowable area allowed for the circuit combining them, and the area where the memory controller 20 is allowed to be allowed by the memory controller It may be set to an execution code length Scode that is equal to or smaller than the area. The reason for this setting is that the area of the error correction circuit 30 increases as the execution code length Scode becomes longer. Therefore, the area of the error correction circuit 30, the host interface circuit 22, the buffer circuit 26, the data inverting circuit 28, and the error correction are corrected. This is because the area of the circuit combining the circuit 30 and the memory interface circuit 24 and the area of the memory controller 20 tend to increase. In this way, the error correction circuit 30, the host interface circuit 22, the buffer circuit 26, the data inversion circuit 28, the error correction circuit 30, and the memory interface circuit 24 are combined. Can be suppressed. Furthermore, the upper limit execution code length Scmax may be set in consideration of a plurality of the above-described circuit power consumption and reading speed and circuit area.

   In the flash memory systems 10 and 110 of the first and second embodiments, the execution data stored in the correction information storage unit 132 when the write / erase count Nwr exceeds the determination threshold Nref in the storage processing units 38 and 138. Although the data length twice the length Sdata is stored in the correction information storage unit 132 as the execution data length Sdata, a data length longer than the execution data length Sdata is stored in the correction information storage unit 132 as the execution data length Sdata. Therefore, for example, the correction information storage unit 132 has a data length that is m times the execution data length Sdata (m is an integer of 3 or more) stored in the correction information storage unit 132 as the execution data length Sdata. It may be memorized.

   In the flash memory systems 10 and 110 of the first and second embodiments, the data inversion circuits 28 and 128 read out data from the buffer circuits 26 and 126 bit by bit, and the “1” included in the read 4-bit data. Although a 1-bit inversion flag or non-inversion flag is added based on the number of data of “0”, the size of the data to be read from the buffer circuits 26 and 126, the inversion flag and the non-inversion flag (bits) The data from the error correction circuit 130 is not limited to the data obtained by deleting the inversion flag and non-inversion flag in consideration of the size of the added inversion flag and non-inversion flag. What is necessary is just to output to 126.

   In the flash memory systems 10 and 110 of the first and second embodiments, the BCH code is used when encoding data, but the code for performing such error correction is limited to the BCH code. Instead, a block code such as a Reed-Solomon code or a convolutional code such as an LDPC code may be used.

   In the flash memory systems 10 and 110 of the first and second embodiments, the memory controller 20 includes the data inversion circuits 28 and 128. However, the memory controller 20 does not include the data inversion circuits 28 and 128. For example, data may be input / output between the buffer circuits 26 and 126 and the error correction circuits 30 and 130.

   In the flash memory systems 10 and 110 of the first and second embodiments, the flash memory cell stores the state in which electrons are injected into the floating gate as “0” data, and the electrons are extracted from the floating gate to “0”. It is assumed that the binary storage element stores the state in which the number of electrons in the floating gate is less than that in the “state” as “1” data. For example, the amount of electrons injected into the floating gate is controlled in four stages. It is also possible to use a multi-value storage element having more than two values, such as one capable of storing four values “00”, “01”, “10”, and “11”.

   In the flash memory systems 10 and 110 of the first and second embodiments, the flash memories 12 and 112 and the memory controllers 20 and 120 are formed on separate semiconductor chips, but on the same semiconductor chip. It may be formed.

   As mentioned above, although the form for implementing this invention was demonstrated using the Example, this invention is not limited at all to such an Example, In the range which does not deviate from the summary of this invention, it is with various forms. Of course, it can be implemented.

   In addition, this invention is the result of the research subject "Dependable Wireless Solid State Drive" of the Strategic Creation Research Promotion Project of the Japan Science and Technology Agency in 2009.

   The present invention can be used in the manufacturing industry of data input / output control devices and semiconductor memory device systems.

10,110 Flash memory system, 12,112 Flash memory, 20,120 Memory controller, 22,122 Host interface circuit, 24,124 Memory interface circuit, 26,126 Buffer circuit, 28,128 Data inversion circuit, 30,130 Error Correction circuit, 32, 132 Correction information storage unit, 34, 134 Encoding unit, 36 Decoding error number detection unit, 38, 138, Storage processing unit, 40, 140 Control circuit, 60, 160 Host device, 129 Count of write / erase times Circuit, 136 Decoding unit.

Claims (12)

Data input from the host device is encoded into a predetermined error correction code and stored in a non-volatile semiconductor memory device, and the data stored in the semiconductor memory device is input and the predetermined data is input to the predetermined data. A data input / output control device for error correction using the error correction code and decoding and outputting to the host device,
A write count circuit that counts the number of write / erase times, which is the sum of the number of times data is written to the semiconductor memory device and the number of times data stored in the semiconductor memory device is erased, and the predetermined error An error correction information storage unit that stores an execution data length that is the length of data to be encoded into a correction code and an execution code length that is the length of the predetermined error correction code; and the input data that is stored An encoding unit that sequentially reads each of the execution data lengths, encodes the read data into the predetermined error correction code of the execution code length, and outputs the encoded data to the semiconductor memory device; and stores the input data in the storage The read execution code lengths are sequentially read, and the read data is error-corrected and decoded by the predetermined error correction code to decode the host. A decoding unit for outputting the device, as a write erase count corresponding to the upper limit number of errors is an upper limit of a detectable number of errors in said predetermined error correction code execution code length stored in the error-correction information storage unit When the counted number of write / erase times exceeds the threshold for determination, it is possible to correct and detect errors larger than the upper limit of the number of errors that can be corrected and detected with a predetermined error correction code of one execution code length. The data length that is longer than the execution data length stored in the error correction information storage unit and the code length longer than the execution code length stored in the error correction information storage unit are A data correction input / output circuit having an execution data length and a storage processing unit to be stored in the error correction information storage unit as the execution code length;
When a write request signal for requesting writing of data from the host device to the semiconductor memory device is input, the data input from the host device is input to the encoding unit of the data correction input / output circuit and the data correction The data correction input / output circuit and the semiconductor memory device are arranged so that the data output from the encoding unit of the input / output circuit is output to the semiconductor memory device and the output data is stored in the semiconductor memory device. When the read request signal for controlling and reading the data stored in the semiconductor memory device is input from the host device, the data stored in the semiconductor memory device is read and the read data Is input to the decoding unit of the data correction input / output circuit and output from the decoding unit of the data correction input / output circuit. The data correction input / output circuit and the semiconductor memory device are controlled so as to be output to the host device, and an erasure request signal for requesting erasure of data stored in the semiconductor memory device is input from the host device A control circuit for controlling the semiconductor memory device so that data stored in the semiconductor memory device is sometimes erased;
A data input / output control device comprising: The data input / output control device according to claim 1,
The storage processing unit of the data correction input / output circuit is m times the stored execution data length (m is an integer of 2 or more) when the counted number of write / erase times exceeds the determination threshold. A data input / output control device, which is a processing unit that stores a data length in the error correction information storage unit as the execution data length. The data input / output control device according to claim 1 or 2,
The storage processing unit of the data correction input / output circuit is preliminarily set as an upper limit of the code length for execution at which the power consumed by the data correction input / output circuit is less than or equal to the allowable power allowed to be consumed by the data correction input / output circuit. The execution data length and the execution code length set so that the execution code length stored in the error correction information storage unit is shorter than a predetermined upper limit power allowable code length are stored in the error correction information storage unit A data input / output control device that is a processing unit. A data input / output control device according to any one of claims 1 to 3,
The storage processing unit of the data correction input / output circuit is configured to permit reading, which is a data rate that the data correction input / output circuit can read from the semiconductor memory device per unit time. The execution data length set so that the execution code length stored in the error correction information storage unit is shorter than an upper limit speed allowable code length predetermined as an upper limit of the execution code length that is equal to or lower than the speed, and the A data input / output control device, which is a processing unit that stores an execution code length in the error correction information storage unit. A data input / output control device according to any one of claims 1 to 4,
The storage processing unit of the data correction input / output circuit has an upper limit area predetermined as an upper limit of the code length for execution in which the area of the data correction input / output circuit is equal to or less than an allowable area allowed for the data correction input / output circuit. processing and stores the allowable code the error-correction information storing the execution code length the execution data length and the execution code length stored is set to be shorter section than length before disappeared error correction information storage unit section Is a data I / O controller. A data input / output control device according to any one of claims 1 to 5,
The semiconductor memory device stores a plurality of electron injection states as a multi-value memory in accordance with the amount of electrons injected into the floating gate, and a semiconductor whose deterioration tends to be accelerated as the amount of electrons injected into the floating gate increases. A device having a plurality of storage elements,
The data correction input / output circuit is
The input data is sequentially read by a first length, and the semiconductor memory element of the read first length data is injected into the floating gate from a predetermined electron injection state. When the number of high electron injection data to make the quantity large is less than or equal to the number of low electron injection data to make the semiconductor memory element have a smaller quantity of electrons injected into the floating gate than the predetermined high electron injection state A first flag of a second length is added and output to the encoding unit, and the number of high electron injection data among the read first length data is the number of low electron injection data. If it exceeds, the high electron injection data is converted into the low electron injection data, and the data conversion is performed by converting the low electron injection data into the high electron injection data. The second flag having the second length is added to the subsequent data and output to the encoding unit, and the data output from the decoding unit is set to the first length and the second length is set to the second length. When the added third length is sequentially read and the read third length data includes the first flag, the data obtained by deleting the first flag from the data is output and the reading is performed. However, when the third length data includes the second flag, a data conversion unit that performs the data conversion on the first length data from which the second flag is deleted, and outputs the data.
A circuit having
The control circuit, when the write request signal is input from the host device, data input from the host device is input to the encoding unit through the data conversion unit of the data correction input / output circuit, When the read request signal is input from the host device, the data correction input / output circuit and the data correction input / output circuit are output so that the data output from the decoding unit of the data correction input / output circuit is output to the host device via the data conversion unit. A data input / output control device which is a circuit for controlling a semiconductor memory device. The data input / output control device according to claim 6,
The semiconductor memory element stores, as binary storage, a high electron injection state in which electrons are injected into the floating gate and a low electron injection state in which electrons are injected into the floating gate less than the high electron injection state. And
The data input / output control device, wherein the high electron injection data is data for setting the semiconductor memory element in the high electron injection state, and the low electron injection data is data for setting the semiconductor memory element in the low electron injection state. A data input / output control device according to any one of claims 1 to 7,
The data input / output control apparatus, wherein the predetermined error correction code is a block code or a convolutional code. A data input / output control device according to any one of claims 1 to 8,
The semiconductor memory device stores the larger the number of times of writing and erasing, which is the sum of the number of times data is written to the semiconductor memory device and the number of times data stored in the semiconductor memory device is erased. A data I / O controller that tends to increase the probability of data errors. The data input / output control device according to claim 9, wherein
The semiconductor memory device is a NAND flash memory, a NOR flash memory, a phase change memory, a magnetoresistive memory, a ferroelectric memory, a resistance change memory, or a combination of these data input / output control device . A data input / output control device according to any one of claims 1 to 10,
The semiconductor memory device is a device formed on a semiconductor chip different from the semiconductor chip on which the data input / output control device is formed. A non-volatile semiconductor memory device;
A data input / output control device according to any one of claims 1 to 8,
A semiconductor memory device system.

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