JP5166074B2 - Semiconductor memory device, control method thereof, and error correction system - Google Patents

Abstract

A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).

Description

  The present invention relates to a semiconductor memory device, a control method thereof, and an error correction system, and more specifically, a semiconductor memory device including an error correction circuit for correcting an error of a semiconductor memory that stores information in a nonvolatile manner, a control method thereof, and It relates to an error correction system.

  In recent years, semiconductor devices such as flash memories that store information in accordance with the amount of charge held are widely known. In addition, a multi-level memory technology for storing information of 2 bits or more by setting a plurality of charge amount thresholds has been developed.

  In such a semiconductor memory device, since charges are discharged as time elapses, an error occurs when information is read if the charges are discharged beyond the threshold. In particular, in a multi-level memory element, since the threshold interval is generally narrow, there is a high possibility that an error will occur.

  In a storage device using the semiconductor memory element as described above, an error correction mechanism for correctly restoring erroneous information may be provided (for example, see Patent Document 1).

In general, a correction mechanism with high error correction capability is required to correct errors even when there are many errors in the data consisting of multiple bits due to the fact that time has passed since the recording of information. is there. A correction mechanism having high error correction capability has a large circuit scale, high power consumption, and requires time for processing. Usually, a correction mechanism having a high error correction capability is provided in order to ensure that correct information can be restored even after a long time has elapsed since the information was stored. A high-performance error correction mechanism is applied uniformly regardless of the length of time elapsed since the information was stored.

For this reason, such a high-performance error correction mechanism is also used when reading information for which only a short time has elapsed since storage. As a result, a high-performance error correction mechanism is uselessly used in spite of reading information that does not include so many errors. This means
The power consumption of the storage device is wasted.

Furthermore, in general, in order to increase the error correction capability, it is required to increase the information to be corrected. For example, instead of generating an error correction code for 512-byte data, an error correction code is generated using, for example, 4 kbytes of data obtained by concatenating a plurality of 512-byte data as one unit. By doing so, the error correction capability can be enhanced. However, this method leads to the fact that, for example, 4 kbytes of data must be read although 512 bytes of data are to be read. This also forces the storage device to consume useless power.

JP 2007-87464 A

An object of the present invention is to provide a semiconductor memory device capable of reducing power consumption and circuit scale without impairing error correction capability, a control method thereof, and an error correction system.

  In order to solve the above-described problems and achieve the object, the present invention provides temporary storage means capable of storing a plurality of data blocks composed of a plurality of data in a matrix, and detecting an error for each data block. Error detection code generation means for generating a first error correction code generation means for generating a first error correction code for correcting the error for each first unit data composed of the data block Second error correction code generation means for generating a second error correction code for correcting the error for each second unit data composed of the plurality of data blocks arranged in the column direction, and the row direction Third error correction code generating means for generating a third error correction code for correcting an error for each third unit data composed of a plurality of the data blocks arranged in a block, and the data block Click, characterized by comprising a nonvolatile semiconductor memory capable of storing the generated error detection code and the first to third error correction code.

  The present invention also includes a step of storing a plurality of data blocks made up of a plurality of data in a temporary storage means in a matrix, and an error detection code for generating an error detection code for detecting the error for each data block A generation step, a first error correction code generation step for generating a first error correction code for correcting the error for each first unit data configured by the data block, and a plurality of units arranged in the column direction A second error correction code generating step for generating a second error correction code for correcting the error for each second unit data composed of the data block, and a plurality of the data blocks arranged in a row direction. A third error correction code generating step for generating a third error correction code for correcting the error for each configured third unit data; the data block; and the generated error detection code. And characterized in that it comprises a a step of storing the first to third error correction code to the nonvolatile semiconductor memory.

According to another aspect of the present invention, there is provided an error correction system including a host device and a semiconductor memory device that reads / writes data to / from a non-volatile memory in accordance with an instruction from the host device. Temporary storage means for dividing data transferred from the apparatus into data blocks composed of a plurality of data and storing them in a matrix, and an error detection code for detecting the error for each data block is generated Error detection code generation means, first error correction code generation means for generating a first error correction code for correcting the error for each first unit data composed of the data block, and arrayed in the column direction A second error correction code for generating a second error correction code for correcting the error for each second unit data composed of a plurality of data blocks Generating means, and third error correction code generating means for generating a third error correction code for correcting the error for each third unit data composed of a plurality of the data blocks arranged in the row direction; A non-volatile semiconductor memory storing a previous data block, the generated error detection code and the first to third error correction codes, and a first error using the corresponding first error correction code for each data block First error correction means for performing correction;
A first error detecting means for detecting an error in the first error-corrected block using the corresponding error detection code; and an error in the first error-corrected block detected by the first error detecting means. Second error correction means for correcting an error using the corresponding second correction code, and second error detection means for detecting an error in the second error-corrected block using the corresponding error detection code And transmission means for transmitting the second error corrected data and the detection result of the second error detection means to a host device, wherein the host device is transferred from the semiconductor memory device. And a third error correction means for correcting an error of the second error corrected block detected by the two error detection means using the corresponding third correction code.

According to the present invention, it is possible to provide a semiconductor memory device capable of reducing power consumption and circuit scale without impairing error correction capability, a control method thereof, and an error correction system.

  Hereinafter, the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. In addition, constituent elements in the following embodiments include those that can be easily assumed by those skilled in the art or that are substantially the same.

(Embodiment 1)
In the present invention, when error correction coding / decoding is applied to a memory having defective bits such as a flash memory, power consumption and circuit scale are reduced by performing three types of correction coding with different error correction capabilities. Can do.

[Configuration of SSD]
FIG. 1 is a block diagram illustrating a configuration example of an SSD (Solid State Drive) 100. The SSD 100 is connected to a host device (host) 1 such as a personal computer or a CPU core via a memory connection interface such as an ATA interface (ATA I / F) 2 and functions as an external memory of the host device 1. Further, the SSD 100 can transmit / receive data to / from the debugging device 200 via the communication interface 3 such as an RS232C interface (RS232C I / F). The SSD 100 includes a NAND flash memory (hereinafter abbreviated as a NAND memory) 10 as a non-volatile memory, a drive control circuit 4 as a controller, a DRAM 20 as a volatile memory, a power supply circuit 5, an LED 6 for displaying a status, and the like. It has.

  The power supply circuit 5 generates a plurality of different internal DC power supply voltages from an external DC power supply supplied from the power supply circuit on the host device 1 side, and supplies these internal DC power supply voltages to each circuit in the SSD 100. The power supply circuit 5 detects the rise or fall of the external power supply, generates a power-on reset signal or a power-off reset signal, and supplies it to the drive control circuit 4.

  In this case, the NAND memory 10 includes four parallel operation elements 10a to 10d that perform four parallel operations, and one parallel operation element includes two NAND memory packages. Each NAND memory package includes a plurality of stacked NAND memory chips (for example, 1 chip = 2 GB). In the case of FIG. 1, each NAND memory package is constituted by four stacked NAND memory chips, and the NAND memory 10 has a capacity of 64 GB. When each NAND memory package is constituted by eight stacked NAND memory chips, the NAND memory 10 has a capacity of 128 GB.

  The DRAM 20 functions as a data transfer cache and work area memory between the host device 1 and the NAND memory 10.

  The drive control circuit 4 controls data transfer between the host device 1 and the NAND memory 10 via the DRAM 20 and controls each component in the SSD 100. In addition, the drive control circuit 4 supplies a status display signal to the status display LED 6 and receives a power on / off reset signal from the power supply circuit 5 to receive a reset signal and a clock signal in its own circuit and in the SSD 100. It also has a function of supplying each part.

  Each NAND memory chip is configured by arranging a plurality of blocks which are data erasing units. FIG. 2 is a circuit diagram showing a configuration example of one block included in the NAND memory chip. Each block includes (m + 1) NAND strings arranged in order along the X direction (m is an integer of 0 or more). The select transistors ST1 included in each of (m + 1) NAND strings have drains connected to the bit lines BL0 to BLm and gates commonly connected to the select gate line SGD. In addition, the selection transistor ST2 has a source commonly connected to the source line SL and a gate commonly connected to the selection gate line SGS.

  Each memory cell transistor MT is composed of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a stacked gate structure formed on a semiconductor substrate. The stacked gate structure includes a charge storage layer (floating gate electrode) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a control gate electrode formed on the charge storage layer with an inter-gate insulating film interposed therebetween. It is out. In the memory cell transistor MT, the threshold voltage changes according to the number of electrons stored in the floating gate electrode, and data is stored according to the difference in threshold voltage. The memory cell transistor MT may be configured to store 1 bit, or may be configured to store multiple values (data of 2 bits or more).

  In each NAND string, (n + 1) memory cell transistors MT are arranged such that their current paths are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. That is, the plurality of memory cell transistors MT are connected in series in the Y direction so that adjacent ones share a diffusion region (source region or drain region).

  The control gate electrodes are connected to the word lines WL0 to WLn in order from the memory cell transistor MT located closest to the drain side. Therefore, the drain of the memory cell transistor MT connected to the word line WL0 is connected to the source of the selection transistor ST1, and the source of the memory cell transistor MT connected to the word line WLn is connected to the drain of the selection transistor ST2.

  The word lines WL0 to WLn connect the control gate electrodes of the memory cell transistors MT in common between the NAND strings in the block. That is, the control gate electrodes of the memory cell transistors MT in the same row in the block are connected to the same word line WL. The (m + 1) memory cell transistors MT connected to the same word line WL are handled as one page, and data writing and data reading are performed for each page.

  The bit lines BL0 to BLm connect the drains of the selection transistors ST1 in common between the blocks. That is, NAND strings in the same column in a plurality of blocks are connected to the same bit line BL.

As shown in FIG. 1, in the NAND memory 10, four parallel operation elements (memory packages) 10a to 10d are connected in parallel to the drive control circuit 4 through four channels (4ch) each having 8 bits. The following three types of access modes are provided depending on the combination of whether the four parallel operation elements 10a to 10d are operated independently, in parallel, or whether the double speed mode of the NAND memory 10 is used.
(1) 8-bit normal mode In this mode, only 1 channel is operated and reading / writing is performed in 8-bit units. One unit of transfer size is a page size (4 kB).
(2) 32-bit normal mode In this mode, 4 channels are operated in parallel, and reading and writing are performed in units of 32 bits. One unit of the transfer size is page size × 4 (16 kB).
(3) 32-bit double speed mode In this mode, 4 channels are operated in parallel, and reading / writing is performed using the double speed mode of the NAND memory 10. One unit of the transfer size is page size × 4 × 2 (32 kB).

  In the 32-bit normal mode or the 32-bit double speed mode that operates in parallel with 4 channels, 4 or 8 blocks that operate in parallel serve as erase units as the NAND memory 10, and 4 or 8 pages that operate in parallel operate as write units as the NAND memory 10. This is a read unit.

  The drive control circuit 4 includes a controller 41, an ECC (Error Correcting Code) circuit 42, and a NAND I / F 43.

  The controller 41 transmits / receives data to / from the host device 1 via the ATA interface 2 and controls access to the DRAM 20.

  The NAND I / F 43 performs interface processing with each of the NAND packages 10 a to 10 d of the NAND memory 10.

  The ECC circuit 42 generates an error detection code and an error correction code for the data to be written to the NAND memory 10. The ECC circuit 42 performs error detection and error correction on the data read from the NAND memory 10.

  An outline of the operation of the SSD 100 having the above configuration will be described. When data (write data) for requesting writing to the SSD 100 is supplied from the host device 1, the controller 41 temporarily stores the write data in the DRAM 20. The write data stored in the DRAM 20 is supplied by the controller 41 to the ECC circuit 42 every predetermined unit. The ECC circuit 42 generates an error correction code and an error detection code for the write data. The NAND I / F 43 writes the write data with the error correction code and the error detection code added to the NAND memory 10.

  In addition, when a data read request is input from the host device 1 to the SSD 100, the NAND I / F 43 receives the data requested to be read (read data) and the error correction code and error detection code added thereto. Read and supply to the ECC circuit 42. The ECC circuit 42 detects and corrects errors in read data. The data after error correction is stored in the DRAM 20 by the controller 41 and then transferred to the host device 1.

[ECC circuit]
Hereinafter, a basic operation procedure of the ECC circuit 42 will be described. The ECC circuit 42 according to the embodiment of the present invention reduces power consumption and circuit scale by performing three types of correction coding with different error correction capabilities on data to be written to the NAND memory 10. The first error correction code is for performing error correction on a data block D basis. The second error correction code is for performing error correction in units of columns composed of a plurality of data blocks D. The third error correction code is for performing error correction in units of rows composed of a plurality of data blocks D. The error correction capability is in the order of first error correction code <second error correction code <third error correction code.

  FIG. 3 is a schematic diagram for explaining the outline of the error correction principle of the ECC circuit 42. The figure shows data read from the NAND memory 10, and data blocks D composed of a plurality of data are arranged in a matrix. The hatched portion indicates an error data block including error data. First, error correction (first error correction) is performed for each data block D (A). Next, error correction (first second error correction) in units of columns is performed on the data block D in which the error could not be corrected (B). Further, error correction (first third error correction) in units of rows is performed on the data block D that could not be corrected (C). Again, error correction (second second error correction) in units of columns is performed on the data block D in which the error could not be corrected (D). Further, error correction (second third error correction) in units of rows is performed on the data block D in which the error could not be corrected (E). As a result, error-free data is decoded (F).

  Thus, in this embodiment, first, error correction (first error correction) is performed in units of data blocks. If there is a data block that could not be corrected, error correction in units of columns (second error correction) and error correction in units of rows (third error correction) are alternately performed until there is no error. Iteratively execute and decode error-free data.

[Configuration of ECC circuit coding system]
FIG. 4 is a block diagram showing a main part related to the encoding system of the ECC circuit 42. FIG. 5 is a diagram showing an example of a format when data transferred from the host device 10 is stored in the DRAM 20. FIG. 6 is a diagram illustrating an example of a format of data transferred to the NAND memory 10.

  As shown in FIG. 4, the ECC circuit 42 includes error detection code generation units 50-1 to 50-8 (error detection code generation means), first ECC generation units 51-1 to 5-8 (first error correction code generation means), and The second ECC generation unit 52 (second error correction code generation unit) and the third ECC generation units 53-1 to 5-8 (third error correction code generation unit).

  Error detection code generation units 50-1 to 50-8 (error detection code generation means) generate an error detection code for detecting the error for each data block D of the write data. The size of the data block D is, for example, 512 bytes.

  As the error detection code, CRC (Cyclic redundancy checksum) 32, CRC16, or the like can be used. In the present embodiment, CRC 32 is used, and the size of CRC 32 (hereinafter referred to as “CRC”) is 4 bytes. As the error detection code generation units 50-1 to 50-8, generally known ones can be used, and detailed description thereof is omitted here.

  The first ECC generation units 51-1 to 5-8 (first error correction code generation means) perform a first error for correcting the error for each first unit data composed of the data block D and its error detection code. A correction code is generated.

  As the first error correction code, an error correction code that can correct an error of 1 bit or a plurality of bits can be used. For example, a Hamming code or a BCH code may be used. Can do. In this embodiment, a Hamming code is used as the first error correction code, and the size of the Hamming code is 4 bytes. As the first ECC generation units 51-1 to 51-8, generally known ones can be used, and detailed description thereof is omitted here.

  The second ECC generation unit 52 (second error correction code generation means) generates a second error correction code for each second unit data UDa composed of a plurality of first unit data arranged in the column direction. The number of write data as a unit for generating the second error correction code is determined according to the error correction capability desired to be achieved and the error correction code employed.

  As the second error correction code, one having higher error correction capability than that of the first error correction code is used, and an error correction code capable of correcting a multi-bit error is used. Specifically, a BCH code, an LDPC code (Low density parity check code), or the like can be used. In the present embodiment, a BCH code is generated for each second unit data UDa composed of eight first unit data in the column direction, and the size of the BCH code is 24 bytes. The second ECC generation unit 52 can use a generally known one, and a detailed description thereof will be omitted here.

  The third ECC generators 53-1 to 5-8 (third error correction code generator) correct the error for each of the third unit data UDb composed of a plurality of data blocks D arranged in the row direction. The third error correction code is generated. The number of data blocks D as a unit for generating the third error correction code is determined according to the error correction capability desired to be achieved and the error correction code employed.

  As the third error correction code, for example, a code that enables error correction with higher capability than error correction using a second error correction code that performs error correction in units of a plurality of bits is used. Specifically, an RS code (Reed-solomon code) or the like can be used as the third error correction code. In the present embodiment, an RS code is generated for each third unit data UDb including 1024 first unit data D, and the size of the RS code is set to 512 bytes, which is the same as that of the data block D. Then, the third ECC generation units 53-1 to 53-8 generate, for example, four RS codes for one third unit data UDb. Accordingly, it is possible to correct errors in four write data among 1024 data blocks D constituting one third unit data UDb. The third ECC generation unit 53 can use a generally known one, and a detailed description thereof is omitted here.

  When the controller 41 receives the write data D (1, 1) to D (8, 1024) from the host device 1, the controller 41 stores eight pieces of processing units of the first ECC generation unit 51 in the DRAM 20, as shown in FIG. The data blocks D (1, p) to D (8, p) are sequentially stored in the column direction, and 1024 first unit data D (q, 1) to D (q which are processing units of the third ECC generation unit 53 are stored. , 1024) and sequentially transferred to the ECC circuit 42 in units of columns. p is an arbitrary number from 1 to 1024, and q is an arbitrary number from 1 to 8.

  The error detection code generation unit 50 corresponds to the eight data blocks D (1, p) to D (8, p) arranged in the column direction, and the eight error detection code generation units 50-1 to 50-50. -8. The eight error detection code generation units 50-1 to 50-8 generate eight CRCs 32 for the eight data blocks D (1, p) to D (8, p). Each of the eight CRCs 32 is used to detect errors in the eight data blocks D (1, p) to D (8, p) corresponding thereto. The eight CRCs 32 are output to the first ECC generators 51-1 to 51-8 and the second ECC generator 52. Note that the error detection code generation units 50-1 to 50-8 also generate CRC 32 for the eight RS (1, r) to RS (8, r) arranged in the column direction. r is an arbitrary number from 1 to 4.

  The first ECC generation unit 51 corresponds to the eight data blocks D (1, p) to D (8, p) arranged in the column direction, and the eight first ECC generation units 51-1 to 51-8. It has. The eight first ECC generation units 51-1 to 51-8 are respectively provided for each first unit data, that is, eight data blocks D (1, p) to D (8, p) and eight CRC ( 1, p) to CRC (8, p), respectively, generate Hamming codes. Each of the eight Hamming codes is used for first error correction of the eight unit data D (1, p) to D (8, p) corresponding thereto. The eight Hamming codes are output to the second ECC generation unit 52. Each of the first ECC generation units 51-1 to 51-8 also applies a Hamming code to each of the eight RS (1, r) to RS (8, r) and the corresponding CRC 32 arranged in the column direction. Generate. r is an arbitrary number from 1 to 4.

  The second ECC generation unit 52 includes eight first unit data arranged in the column direction, that is, data blocks D (1, p) to D (8, p), and eight CRC (1) corresponding thereto. , P) to CRC (8, p), one BCH code is generated for each second unit data UDa. This BCH code is used to correct errors in the second unit data UDa (excluding ECC1 (1, p) to ECC1 (8, p)). In the present embodiment, this corresponds to the size of the data composed of the second unit data UDa and the BCH code, and the size of one page (the minimum access unit of the NAND memory 10).

  The third ECC generation unit 53 generates one RS code for each third unit data UDb including 1024 data blocks D (q, 1) to D (q, 1024) arranged in the row direction. The third ECC generation unit 53 includes eight third ECC generation units 53-1 to 53-8 corresponding to the write data rows stored in the DRAM 20. The third ECC generation unit 53-1 includes a buffer for storing the third unit data UDb. Four RS (1, 1) to RS (1, 4) are generated for the third unit data UDb1 including data D (1, 1) to D (1, 1024). The same applies to the third ECC generation units 53-2 to 53-8 respectively corresponding to the 2nd to 8th rows.

  The data block D, CRC, Hamming code, BCH code, and RS code are transferred from the NAND IF 43 to the NAND memory 12 for each page shown in FIG. The NAND memory 10 stores these data in page order. For example, when one memory block BLK is composed of 1028 pages, the data shown in FIG. 6 is stored in one memory block BLK in the NAND memory 10 (in the case of 8-bit normal mode). In the 32-bit mode (32-bit normal mode, 32-bit double speed mode), data is written in parallel to each Ch memory chip.

[Data writing operation of encoding system of ECC circuit]
Next, the error detection code generation operation and the error correction code generation operation of the ECC circuit 42 in the data write operation will be described with reference to FIGS.

  First, in FIG. 5, the controller 41 sequentially stores the data to be written to the NAND memory 10 in the DRAM 20 for each of the eight data blocks D (1, q) to D (8, 1) in the column direction. And data blocks D (1, 1) to D (8, 1024) are stored, and the data stored in the DRAM 20 is sequentially stored in units of columns in the data blocks D (1, q) to D (8, 1). Are output to the error detection code generators 50-1 to 50-1, the first ECC generators 51-1 to 8, the second ECC generator 52, and the third ECC generators 53-1 to 53-8.

  Subsequently, as illustrated in FIG. 7, the error detection code generation units 50-1 to 50-8 perform the eight data blocks D (1, 1) to D (8, 1) transferred. Eight error detection codes CRC (1, 1) to CRC (8, 1) are generated. The first ECC generators 51-1 to 51-8 respectively include eight write data D (1,1) to D (8,1) and eight CRC (1,1) to CRC (8, From 1), Hamming codes ECC1 (1, 1) to ECC1 (8, 1) are generated.

  Subsequently, as shown in FIG. 8, eight data blocks D (1,1) to D (8,1) and corresponding eight error detection codes CRC (1,1) to CRC (8,1). The second unit data UDa1 configured by is output to the second ECC generation unit 52. The second ECC generation unit 52 uses the second unit data UDa1 to generate a BCH code ECC2 for correcting an error in the second unit data UDa1. The BCH code ECC2 is connected to the back of the second unit data UDa1 to form page 1 (Page1). This page 1 is stored in the NAND memory 10.

For page 2 to page 1024, the data shown in FIG. 6 is generated by the generation operation similar to the above. Then, page 2 to page 1024 are stored in the NAND memory 10.

Further, as shown in FIG. 9, the third ECC generators 53-1 to 53-8 buffer the first unit data D (1, q) to D (8, q), which are sequentially transferred in units of columns, respectively. And using the third unit data UDb1, UDb2,... UDb8, four RS (p, 1) to R
S (p, 4) is generated respectively. Specifically, the third ECC generation unit 53-1 generates four RS (1, 1) to RS (1, 4) using the third unit data UDb1. The RS generation operation by the third ECC generation units 53-2 to 53-8 is the same as that of the RS generation unit 53-1. In the present embodiment, the third ECC generators 53-1 to 53-8 perform correction code generation operations in parallel. In this way, the processing time can be shortened by operating the third ECC generation units 53-1 to 53-8 in parallel.

  When an RS code is used, normally, two error position information and two error correction information are obtained using four redundant codes, so that two errors can be corrected. However, in this embodiment, in order to characterize the error position of the data block D, a separate CRC is used. Therefore, in this embodiment, it is possible to correct four errors using four redundant codes. That is, it is possible to correct four errors out of 1024 data blocks D (1,1) to D (1,1024).

Subsequently, similarly to the case of the data block D, the error code generation units 50-1 to 50-8 perform CRC (1, 1025) to (8, 8) for each RS (1, 1) to RS (8, 4). 1028) respectively. Further, the first ECC code generation units 51-1 to 51-8 perform a Hamming code (RS) for each of RS (1,1) to RS (8,4) and corresponding CRC (1,1025) to (8,1028). 1,1025) to (8,1028) are generated. Further, the second ECC correction unit 52
For RS (1, 1) to RS (8, 4) and corresponding CRC (1, 1025) to (8, 1028), a BCH code ECC2 is generated, and this BCH code ECC2 is connected to the back of these. Thus, the page 1025 is configured. This page 1025 is transferred to and stored in the NAND memory 10. For page 1026 to page 1028, the data shown in FIG. 6 is generated by the same generation operation as described above. Then, the pages 1026 to 1028 are transferred to and stored in the NAND memory 10.
[Configuration of ECC Circuit Decoding System]

  FIG. 10 is a block diagram showing a main part related to the decoding system of the ECC circuit 42. FIGS. 11 to 19 are diagrams for explaining the data reading of the ECC circuit 42. As shown in FIG. 10, the ECC circuit 42 includes an error detection unit 60, first ECC correction units 61-1 to 61-8, a second ECC correction unit 62, and third ECC correction units 63-1 to 61-8. It has. In the same figure, illustration of the controller 41 and the NAND I / F 43 is omitted for easy explanation.

  When a data read request is input from the host device 1, the SSD 100 reads out block data (data shown in FIG. 6) stored in one memory block BLK in the NAND memory 10 by the NAND I / F 43. (In the case of 8-bit normal mode), the data is stored in the DRAM 20 by the controller 41. The DRAM 20 stores the block data shown in FIG. In the 32-bit mode (32-bit normal mode, 32-bit double speed mode), data is read in parallel from each Ch memory chip.

  The first ECC correction unit 61 applies the eight data blocks D (1, p) to D (8, p) and the corresponding CRC (1, p) to CRC (8, p) arranged in the column direction. In other words, eight first ECC correction units 61-1 to 61-8 are provided corresponding to the number of rows.

  The first ECC correction units 61-1 to 61-8 include eight data blocks D (1, p) to D (8, p) and CRC (1, p) to CRC (8, p) arranged in the column direction. ), The first error correction is performed using the Hamming codes ECC1 (1, p) to ECC1 (8, p), respectively, and the first error corrected data DC1-1 among the data stored in the DRAM 20 is obtained. Update data corresponding to ~ DC1-8. Similarly, the first error correction is performed on RS (1, 1) to RS (8, 4) and corresponding CRC (1, 1025) to (8, 1028). As the first ECC correction units 61-1 to 61-8, generally known ones can be used, and detailed description thereof is omitted here.

  The error detection unit 60 corresponds to the eight data blocks D (1, p) to D (8, p) and the CRC (1, p) to CRC (8, p) arranged in the column direction, That is, eight error detection units 60-1 to 60-8 are provided corresponding to the number of rows.

  The error detection units 60-1 to 60-8 respectively generate eight CRC (1, p) to CRC (CRC) generated for the eight data blocks D (1, p) to D (8, p). 8, p) is used to detect errors in the first unit data D (1, p) to D (8, p). As the error detection units 60-1 to 60-8, generally known ones can be used, and detailed description thereof is omitted here.

  The second ECC correction unit 62 uses the BCH code ECC2 generated for each page, and the eight CRC (1, p) corresponding to the eight first unit data D (1, p) to D (8, p). p) to second error correction in the second unit data composed of CRC (8, p), and the data corresponding to the second error corrected data DC2 among the data stored in the DRAM 20 is updated. To do. Similarly, the second error correction is performed for pages 1025 to 1024.

  The third ECC correction unit 63 corresponds to the eight first ECC correction units 63-1 to 63-63 corresponding to the eight first unit data D (1, p) to D (8, p) arranged in the column direction. -8. The third ECC correction unit 63-1 uses 1024 read data D (1, 1) to D (1) arranged in the row direction using four RS (1, 1) to RS (1, 4). , 1024), the third error correction in the third unit data UDb1 is performed. Similarly, the third ECC correction units 63-2 to 63-8 perform third error correction in the third unit data UDb1 to UDb8. As the third ECC correction units 63-1 to 63-8, generally known ones can be used, and detailed description thereof is omitted here.

  In this embodiment, all four Reed-Solomon codes RS (1, 1) to RS (1, 4) are used for error correction. Therefore, the third ECC correction unit 63-1 can restore four read data out of the 1024 read data D (1,1) to D (1,1024). The same applies to the third ECC correction units 63-2 to 63-8 corresponding to 2 to 8 rows, respectively. The third error corrected data DC3 corrected by the third ECC correction units 63-1 to 63-8 is transferred to the DRAM 20, and data corresponding to the third error corrected data DC3 is stored among the data stored in the DRAM 20. Updated.

  Of the data blocks D (1,1) to D (8,1024) corrected by the first ECC correction units 61-1 to 61-8, the second ECC correction unit 62, and the third ECC correction units 63-1 to 61-8. Data is transferred to the host device by the controller 41.

[Data read operation of decoding system of ECC circuit]
Next, the error detection operation and error correction operation of the ECC circuit 42 in the data read operation will be described with reference to FIGS.

  Prior to the error correction operation, block data (data shown in FIG. 6) stored in one memory block BLK in the NAND memory 10 is transferred to the DRAM 20 (in the case of the 8-bit normal mode). The DRAM 20 stores the block data shown in FIG.

  Data of page 1 to page 1028 is sequentially transferred to first ECC correction units 61-1 to 61-8 in page units (excluding BCH code ECC2), and each data block D (1, 1) of each page. ~ D (8,1024) and its CRC (1,1) ~ CRC (8,1024, RS (1,1) ~ RS (8,4) and its CRC (1,1025) ~ CRC (8,1028) On the other hand, the first error correction is performed using the Hamming codes ECC1 (1, 1) to ECC1 (8, 1028), respectively, and the first error corrected data DC1-1 to DC8 are stored in the DRAM 20.

  Subsequently, an error detection operation is performed by the error detection units 60-1 to 60-8. That is, each of the error detection units 60-1 to 60-8 includes the first error corrected first unit data D (1,1) to D (8,1024) and its CRC (1, 1) to CRC (8,1024), and the first error corrected RS (1,1) to RS (8,4) and its CRC (1,1025) to CRC (8,1028) are transferred from the DRAM 20 Is done.

  The error detection units 60-1 to 60-8 are, in page units, data blocks D (1, 1) to D (8, 1024) after the first error correction and RS (1, 1, after the first error correction, respectively. Errors in 1) to RS (8, 4) are detected using CRC (1, 1) to CRC (8, 1028), respectively. Then, each of the error detection units 60-1 to 60-8 generates, in page units, first error information S1 to S8 indicating which read data block D and RS code RS have an error as a result of error detection. . Each of the first error information S1 to S8 is transferred to the second ECC correction unit 62. Note that the data block D that is found to have an error in the error detection units 60-1 to 60-8 is not the first error corrected data DC1-1 to DC8, but the data block D before correction is replaced with the second ECC correction unit 62. Forward to. This is because the data block D in which an error was found in the error detection units 60-1 to 60-8 was uncorrectable, that is, the error exceeded the correction capability of the first ECC correction units 61-1 to 61-8. This is because error correction by the first ECC correction units 61-1 to 61-8 results in further errors being added. Accordingly, the data before correction has fewer errors than the data with further errors added, and the data before correction is sent to the second ECC correction unit 62. The same applies to RS (1, 1) to RS (8, 4).

  FIG. 11 is a diagram for explaining error detection after the first error correction, and FIG. 12 is a diagram illustrating an example of the first error information S1 to S8. In FIG. 11 and FIG. 12, for the first unit data having no error in the error detection after the first error correction, the first error information S = 0, the first unit in which the error is detected by the error detection after the first error correction For data, the first error information S = 1. In the examples shown in FIGS. 11 and 12, it is indicated that the first unit data 1, 4, and 5 have an error. The first unit data having this error is the second error correction target.

  Second unit data UDa1 to UDa1028 and first error information S1 to S8 after the first error correction are transferred to the second ECC correction unit 62 in units of pages. The second ECC correction unit 62 uses the BHC code ECC2 included in the second unit data UDa, refers to the first error information S1 to S8, and performs the first operation on the first unit data to be subjected to the second error correction. 2 Perform error correction. The second error corrected data DC2 corrected by the second ECC correction unit 62 is transferred to the DRAM 20 and updates the data corresponding to the second error corrected data DC2 among the data stored in the DRAM 20.

  Subsequently, an error detection operation is performed by the error detection units 60-1 to 60-8. That is, each of the error detection units 60-1 to 60-8 includes, in page units, the second error-corrected data blocks D (1,1) to D (8,1024) of each page and their CRCs. (1,1) to CRC (8,1024), the second error corrected RS (1,1) to RS (8,4) and its CRC (1,1025) to CRC (8,1028) are DRAM 20 Is transferred from.

  The error detection units 60-1 to 60-8 respectively receive the second error-corrected data blocks D (1,1) to D (8,1024) and the second error-corrected RS (1,1) to RS. Errors in (8, 4) are detected using CRC (1, 1) to CRC (8, 1028), respectively. Then, each of the error detection units 60-1 to 60-8 generates, as a result of error detection, second error information S1 to S8 indicating which first unit data and the RS code RS have an error in units of pages. . The second error information S1 to S8 are sent to the third ECC correction units 63-1 to 63-8, respectively. As in the case of the first error correction, the data block D that the error detection units 60-1 to 60-8 have found to have an error is not the second error-corrected data DC2 but the data block D before correction. Are transferred to the third ECC correction units 63-1 to 63-8. This is because the data block D in which an error was found in the error detection units 60-1 to 60-8 could not be corrected, that is, the error exceeded the correction capability of the second ECC correction units 62-1 to 62-8. This is because the error correction in the second ECC correction units 62-1 to 62-8 adds a further error as a result. Accordingly, since the data before the correction has fewer errors than the data to which the error is added, the data before the correction is sent to the third ECC correction units 63-1 to 63-8. The same applies to RS (1, 1) to RS (8, 4). In the present embodiment, the error detection units 60-1 to 60-8 perform error detection operations in parallel. Thus, the processing time can be shortened by operating the error detection units 60-1 to 60-8 in parallel.

  FIG. 13 is a diagram for explaining error detection after the second error correction, and FIG. 14 is a diagram illustrating an example of the second error information S1 to S8 after the second error correction. In FIG. 13 and FIG. 14, for the first unit data having no error in error detection after the second error correction, the second error information S = 0, and the block in which an error is detected in the error detection after the second error correction Is second error information S = 1. In the examples shown in FIGS. 13 and 14, it is indicated that there is an error in the first unit data 5. The first unit data having this error becomes the third error correction target.

  FIG. 15 is a diagram illustrating an example of block data after the first error correction by the second ECC correction unit 62. The hatched lines indicate data in which errors are detected by the error detection units 60-1 to 60-8 because they cannot be corrected even by the first error correction by the second ECC correction unit 62.

  If there is no error in all the read data as a result of the first error correction by the second ECC correction unit 62, the error correction operation ends here. That is, error correction by a third ECC correction unit 63 described later is not performed. For example, the third ECC correction unit 63 stops the error correction operation by stopping the supply of power from the power supply circuit 5 or stopping the supply of a clock signal from a clock circuit (not shown). As a result, the data read time when there are few errors can be shortened. Further, since the error correction operation by the third ECC correction unit 63 is not performed, power consumption can be reduced.

  Subsequently, the first error correction operation by the third ECC correction unit 63 is performed. That is, the third unit data UDb1 composed of 1024 data blocks D (1,1) to D (1,1024) arranged in the row direction, and four RSs (1,1, 1) to RS (1, 4) are sent from the DRAM 20 to the third ECC correction unit 63-1. The third ECC correction unit 63-1 corrects errors in the data blocks D (1, 1) to D (1, 1024) using RS (1, 1) to RS (1, 4). The same applies to the third ECC correction units 63-2 to 63-8 corresponding to 2 to 8 rows, respectively.

  In the present embodiment, the third ECC correction units 63-1 to 63-8 perform correction operations in parallel. Thus, the processing time can be shortened by operating the third ECC correction units 63-1 to 63-8 in parallel. The third error corrected data DC3 corrected by the third ECC correction units 63-1 to 63-8 is sent to the DRAM 20. The DRAM 20 updates the data corresponding to the third error corrected data DC3 among the stored data.

  FIG. 16 is a diagram illustrating an example of block data after the first third error correction by the third ECC correction unit 63. As shown in FIG. 16, the errors in the read data D (1, 2) and (1, 6) are corrected by the third ECC correction unit 63-1. In addition, errors in the read data D (8, 1) and (8, 1022) are corrected by the third ECC correction unit 63-8.

  As described above, prior to error correction by the third ECC correction unit 63, the error detection unit 60 is used to specify the position of read data in which an error exists. Therefore, the third ECC correction unit 63 may perform error correction only on read data in which an error is detected. Thereby, the correction time by the 3rd ECC correction | amendment part 63 can be shortened, and power consumption can be reduced.

  Subsequently, a second second error correction by the second ECC correction unit 62 is performed on the pages 1 to 1028. This second error correction operation is the same as the first error correction by the second ECC correction unit 62 described above. FIG. 17 is a diagram illustrating an example of block data after the second second error correction by the second ECC correction unit 62. As shown in FIG. 17, errors in the read data D (2, 1), (3, 2), and (2, 1022) are corrected by the second ECC correction unit 62.

  Subsequently, the error detection units 60-1 to 60-8 detect errors in all the data blocks D and RS codes. This detection operation is the same as the first error detection operation by the error detection units 60-1 to 60-8 described above. Subsequently, second third error correction is performed on the third unit data UDb1 to UDb8 by the third ECC correction units 63-1 to 63-8, respectively. This third error correction operation is the same as the first error correction by the third ECC correction units 63-1 to 63-8.

  FIG. 18 is a diagram illustrating an example of block data after the second third error correction by the third ECC correction unit 63. As shown in FIG. 18, the error in the data block D (2, 5) is corrected by the third ECC correction unit 63-2. Further, errors in the data blocks D (3, 4), (3, 7), and (3, 1023) are corrected by the third ECC correction unit 63-3. As a result, all the errors in the data blocks D (1, 1) to D (8, 1024) are corrected.

  Thereafter, the data blocks D (1, 1) to D (8, 1024) in which all errors are corrected are output from the DRAM 20 to the host device 1.

  FIG. 19 is a diagram showing the relationship between the elapsed time since data was written to the NAND memory 10 and the required correction capability. As shown in FIG. 19, when the elapsed time becomes longer, the number of errors in the data written to the NAND memory 10 increases. Therefore, the error correction capability is changed as the number of errors increases. Then, the error correction capabilities of the first error correction unit 61 to the third error correction unit 63 are determined so that excessive or insufficient error correction capability is not used. Specifically, while the elapsed time is short, error correction can be performed only by the first error correction unit 61, and the first error after the elapsed time exceeds a predetermined time (the time when the number of errors rapidly increases). The error correction capability of the first error correction unit 61 to the third error correction unit 63 is determined so that the error can be corrected by the correction unit 61, the second error correction unit 62, and the third error correction unit 63.

  As described above, according to the present embodiment, first, the first error correction is performed on the read data using the first error correction code (hamming code), and the first error correction result is converted to the second error correction result. The second error correction can be further performed using the correction code (BHC code), and the second error correction result can be further corrected using the third error correction code (RS code). Therefore, even when the correction capabilities of the first error correction code to the third error correction code are lowered, the desired correction capability can be ensured and the circuit scale can be reduced.

  In addition, a first error correction code (Hamming code) having a small error correction capability, a second error correction code (BCH code) having a medium error correction capability, and a third error correction capability having a high error correction capability. By multiplying the error correction code (RS code) in triple, the frequency of decoding of a high degree of error correction can be greatly reduced, and as a result, sufficient processing can be performed by software without having hardware. Thus, the circuit scale can be reduced.

If there is no error in all read data as a result of the first error correction by the first ECC correction unit 61, the error correction by the second ECC correction unit 62 and the third ECC correction unit 63 is not performed. As a result, the data read time when there are few errors can be shortened. That is, it is possible to reduce both the data read time when there are few errors and the high correction capability when there are many errors. Furthermore, the power consumption can be reduced by stopping the operations of the second ECC correction unit 62 and the third ECC correction unit 63.

In addition, an error in the data in the column direction is corrected using the second error correction code (BCH code),
An error in the data in the row direction is corrected using a third error correction code (RS code). Therefore, error correction over all pages in the memory block of the NAND flash memory 1 is possible. In addition, for semiconductor memories in which the error occurrence probability differs greatly due to the position of stored data, an area having a high error occurrence probability can be corrected many times, and thus this embodiment is particularly It is valid.

  In addition, since the position of data in which an error exists can be specified using the error detection unit 60, the second ECC correction unit 62 and the third error correction unit 63 may perform error correction of read data in which an error is detected. Thereby, the processing time by the 2nd ECC correction part 62 and the 3rd error correction part 63 can be shortened.

  Further, since the position of data in which an error exists can be detected by an error detection code (CRC), the third error correction unit 33 does not need to perform error detection. Thereby, all RS codes (in this embodiment, four RS codes) can be used for error correction.

(Embodiment 2)
The SSD according to the second embodiment will be described with reference to FIGS. In the second embodiment, the first and second error corrections are performed by the SSD 100, and the third error correction having high error correction capability is performed by the host device 1 instead of the SSD 100. Most errors can be corrected by the first and second error correction, and the third error correction is extremely low in use frequency and takes a long processing time. Therefore, the load on the SSD 100 is reduced.

  FIG. 20 is a schematic diagram for explaining the error correction principle of the second embodiment. FIG. 21 is a diagram illustrating configurations of the SSD 100 and the host device 100 according to the second embodiment. In the second embodiment, in FIG. 20, the first error correction (A) and the second error correction (B) are performed by the SSD 100, and the processing after the third error correction (C) is performed by the host device 1.

  As shown in FIG. 21, the host device 1 performs error detection unit 101 that detects an error in each data block D using CRC, and second error correction that uses a BCH code (second error correction code). A second ECC unit 102 and a third ECC unit 103 that performs third error correction using an RS code (third error correction code). The error detection unit 101, the second ECC unit 102, and the third ECC unit 103 can be realized by causing the CPU of the host device 1 to execute software.

  The SSD 100 includes data after the second error correction {blocks D (1,1) to D (8,1024) and their CRC (1,1) to CRC (8,1024), and RS (1,1) to RS. (8, 4), its CRC (1, 1025) to CRC (8, 1028), ECC 1), and the second error information are transferred to the host device 1.

  The host device 1 performs the third error correction on the data after the second error correction received from the SSD using the second error correction information, confirms the result by CRC, and detects an error. If so, the second error correction is performed again, and the second and third error corrections are alternately repeated until the error disappears (the processes in FIGS. 15 to 19 are performed).

  FIG. 22 is a block diagram of a main part related to the decoding system of the ECC circuit 42 according to the second embodiment. As shown in FIG. 22, in the decoding system of the ECC circuit 42 according to the second embodiment, it is not necessary to mount the third ECC decoding unit, so that the circuit scale can be reduced.

  According to the second embodiment, since the third error correction is performed by the host device 1, it is not necessary to perform the third error correction by the SSD 100, and the load and circuit scale of the SSD 100 can be reduced.

  In the above embodiment, the present invention is applied to an SSD having a NAND memory. However, the present invention may be applied to an SSD having another flash EEPROM such as a NOR type.

It is a block diagram which shows the structural example of SSD (Solid State Drive). It is a circuit diagram which shows the structural example of one block contained in a NAND memory chip. It is a schematic diagram for demonstrating the outline of the error correction principle of an ECC circuit. It is a block diagram which shows the principal part regarding the encoding system of an ECC circuit. It is a figure which shows an example of the format of the data stored in DRAM. It is a figure which shows the format of the data transferred to NAND memory. It is a figure explaining the error detection code generation operation and error correction code generation operation of an ECC circuit. FIG. 8 is a diagram illustrating an error detection code generation operation and an error correction code generation operation following FIG. 7. FIG. 9 is a diagram for explaining an error detection code generation operation and an error correction code generation operation following FIG. 8. It is a block diagram which shows the principal part regarding the decoding system of an ECC circuit. It is a figure for demonstrating the error detection after a 1st error correction. It is a figure which shows an example of 1st error information. It is a figure for demonstrating the error detection after a 2nd error correction. It is a figure which shows an example of 2nd error information. It is a figure which shows the block data after the 1st error correction by the 2nd ECC correction part. It is a figure which shows the block data after the 1st error correction by the 3rd ECC correction part. It is a figure which shows the block data after the 2nd error correction by the 2nd ECC correction part. It is a figure which shows the block data after the 2nd error correction by the 3rd ECC correction part. It is a figure which shows the relationship between the elapsed time from writing, and required correction capability. 6 is a schematic diagram for explaining an error correction principle of Embodiment 2. FIG. FIG. 3 is a diagram illustrating configurations of an SSD and a host device according to a second embodiment. FIG. 3 is a block diagram showing a main part related to a decoding system of an ECC circuit according to a second embodiment;

Explanation of symbols

100 SSD
1 Host device 2 ATA interface (ATA I / F)
3 Host device (host)
4 Drive control circuit 5 Power supply circuit 6 LED
10 NAND memory 20 DRAM
41 Controller 42 ECC circuit 43 NAND I / F
DESCRIPTION OF SYMBOLS 50 Error detection code production | generation part 51 1st ECC production | generation part 52 2nd ECC production | generation part 53 3rd ECC production | generation part 60 Error detection part 61 1st ECC correction part 62 2nd ECC correction part 63 3rd ECC correction part 101 Error detection part 102 2nd ECC part 103 1st 3ECC Department

Claims (13)

Temporary storage means capable of storing a plurality of data blocks composed of a plurality of data in a matrix,
Error detection code generating means for generating an error detection code for detecting the error for each data block;
First error correction code generation means for generating a first error correction code for correcting an error for each first unit data composed of the data block;
Second error correction code generation means for generating a second error correction code for correcting the error for each second unit data composed of a plurality of the data blocks arranged in the column direction;
Third error correction code generation means for generating a third error correction code for correcting the error for each third unit data composed of a plurality of the data blocks arranged in a row direction;
A nonvolatile semiconductor memory capable of storing the data block, the generated error detection code and the first to third error correction codes;
A semiconductor memory device comprising: First error correction means for performing first error correction using the corresponding first error correction code for each data block;
First error detection means for detecting an error in the first error-corrected block using the corresponding error detection code;
Second error correction means for correcting an error of the first error-corrected block detected by the first error detection means using the corresponding second correction code;
Second error detection means for detecting an error in the second error-corrected block using the corresponding error detection code;
Third error correction means for correcting an error of the second error corrected block detected by the second error detection means using the corresponding third correction code;
The semiconductor memory device according to claim 1, further comprising:   3. The semiconductor memory device according to claim 1, wherein the error correction capability is higher in the order of third error correction> second error correction> first error correction.   3. The semiconductor memory device according to claim 2, wherein the second error correction unit and the third error correction unit repeat the respective correction operations alternately.   The semiconductor memory device according to claim 1, wherein the error detection code generation unit generates an error detection code for detecting an error of the third error correction code.   6. The semiconductor memory device according to claim 1, wherein the first unit data includes an error detection code corresponding to the data block.   7. The semiconductor memory according to claim 1, wherein the second unit data includes an error detection code corresponding to each of a plurality of data blocks constituting the second unit data. apparatus.   The second error code generation means generates a second error correction code for correcting an error for each of the plurality of third error detection codes arranged in a column direction. The semiconductor memory device according to claim 7. The first error detecting means generates first error information for specifying a data block in which an error is detected;
The second error correction means performs a second error correction based on the first error information,
The second error detecting means generates second error information for specifying a data block in which an error is detected;
The semiconductor memory device according to claim 2, wherein the third error correction unit performs third error correction based on the second error information.   The semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory is a NAND flash memory. Storing a plurality of data blocks composed of a plurality of data in a temporary storage means in a matrix;
An error detection code generation step for generating an error detection code for detecting the error for each data block;
A first error correction code generation step for generating a first error correction code for correcting the error for each first unit data composed of the data block;
A second error correction code generating step for generating a second error correction code for correcting the error for each second unit data composed of a plurality of the data blocks arranged in a column direction;
A third error correction code generating step for generating a third error correction code for correcting the error for each third unit data composed of a plurality of the data blocks arranged in the row direction;
Storing the previous data block, the generated error detection code and the first to third error correction codes in a nonvolatile semiconductor memory;
A method for controlling a semiconductor memory device, comprising: A first error correction step for performing a first error correction using the corresponding first error correction code for each data block;
A first error detection step of detecting an error in the first error-corrected block using the corresponding error detection code;
A second error correction step of correcting an error of the first error-corrected block detected in the first error detection step using the corresponding second correction code;
A second error detection step of detecting an error in the second error-corrected block using the corresponding error detection code;
A third error correction step of correcting an error of the second error corrected block detected by the second error detection means using the corresponding third correction code;
The method of controlling a semiconductor memory device according to claim 11 , comprising: In an error correction system including a host device and a semiconductor memory device that reads / writes data to / from a nonvolatile memory according to an instruction from the host device,
The semiconductor memory device
Temporary storage means for dividing the data transferred from the host device into data blocks composed of a plurality of data and storing them in a matrix;
Error detection code generating means for generating an error detection code for detecting the error for each data block;
First error correction code generation means for generating a first error correction code for correcting an error for each first unit data composed of the data block;
Second error correction code generation means for generating a second error correction code for correcting the error for each second unit data composed of a plurality of the data blocks arranged in the column direction;
Third error correction code generation means for generating a third error correction code for correcting the error for each third unit data composed of a plurality of the data blocks arranged in a row direction;
A non-volatile semiconductor memory storing a previous data block, the generated error detection code and the first to third error correction codes;
First error correction means for performing first error correction using the corresponding first error correction code for each data block;
First error detection means for detecting an error in the first error-corrected block using the corresponding error detection code;
Second error correction means for correcting an error of the first error-corrected block detected by the first error detection means using the corresponding second correction code;
Second error detection means for detecting an error in the second error-corrected block using the corresponding error detection code;
Transmitting means for transmitting the second error corrected data and the detection result of the second error detecting means to a host device;
With
The host device is
Third error correction means for correcting an error in the second error corrected block detected by the second error detection means transferred from the semiconductor memory device using the corresponding third correction code An error correction system characterized by comprising:

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