JPH11143787A - Recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve the low error-correction-incapability of a file system without increasing the scale of an encoding/decoding circuit in a memory chip. SOLUTION: An outside encoding/decoding circuit 105 outside a memory chip 102 generates an outside coded matrix by encoding each column of an information data matrix, and adding a redundant bit to each column. On the other hand, an inside encoding/decoding circuit 104 inside the memory chip 102 generates a product coded matrix by encoding the line direction of the outside coded matrix, and adding the redundant bit to each line, and stores it in a memory 103. When the memory chip 104 is used as a single body, the inside encoding/decoding circuit 104 generates the inside coded matrix by encoding the line direction of the information data matrix, and adding the redundant bit to each line, and stores it in the memory 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory chip and a technique for detecting / correcting errors in a recording / reproducing apparatus using the memory chip.

[0002]

2. Description of the Related Art When data is read from a recording medium and transferred, an error may occur in the data due to various factors. These factors can be roughly classified into an error caused by a memory element storing data and an error occurring on a transmission path during data transmission. In a nonvolatile semiconductor memory, particularly a flash memory, the former predominates, and particularly, a memory retention error becomes a problem.

Hereinafter, a description will be given of a retention error.

First, the structure of a flash memory device is shown in FIG.
It is shown in FIG.

In a flash memory device, data is written by injecting charges into a floating gate or extracting charges from the floating gate. Data reading is performed by applying a voltage to the control gate while a constant voltage is applied between the source and the drain, and converting the flowing drain current into a voltage value. Here, the threshold value Vth of the control gate voltage for the current to flow between the drain and the source changes depending on the presence or absence of the charge in the floating gate as shown in FIG. Therefore, in the flash memory element, the data value is read by judging the difference of Vth from the drain current. Here, the retention error refers to an error that occurs when electric charges drop out of the floating gate due to aging, and after a certain period of time, the data reading error rate of the memory element rapidly increases.

Therefore, conventionally, as described in Japanese Patent Application Laid-Open No. 3-5995, a file system using a flash memory includes a flash memory chip in order to highly reliably read data from the memory. Equipped with an encoding / decoding circuit, after adding redundant data for data error detection and error correction, convert the data to error correction code (ECC) and record it, At the time of reading, a method of detecting / correcting a data error using the read ECC is used.

Here, such a system is used.
ECC mainly uses organization codes. This is an ECC in which an information data section and a redundant data section are configured separately. According to the systematic code, an ECC can be configured by adding a redundant data portion to an information data portion, and thus the information portion can be taken in a code word as it is. ECCs, which are systematic codes, include a Hamming code, a BCH code, a Reed-Solomon code, and the like, depending on differences in error correction capability and error correction units. Reed-Solomon codes are often used in file systems that collectively process relatively large (several hundred bytes or more) data.
This is because in such a file system, the minimum unit of data handling is often bytes (8 bits),
Since data errors also have many burst errors, Reed-Solomon codes in which the minimum unit of error correction is a symbol (multiple bits) have better code efficiency than BCH codes in which the minimum unit of error correction is 1 bit. It is.

On the other hand, conventional recording / reproducing media having a relatively high data error rate (about 10 −3), such as a once-writable compact disc (CD-R) and a digital audio tape (R-DAT), have been conventionally used. Rather, a product code having a strong error correction capability for random errors and burst errors is used. This is an ECC that handles information data in a matrix unit and encodes the data in the row direction and the column direction. The feature of the product code is that the ECC in the row direction and the column direction perform decoding in cooperation. There are various known product code decoding methods, each having a difference in the maximum error correction capability, the amount of calculation required for decoding, and the like.

In the above-mentioned recording / reproducing media such as CD-R and R-DAT, a method in which a Reed-Solomon code is product-coded as described in JP-A-63-298776 is mainly used. I have.

[0010]

In a conventional flash memory, one bit corresponds to one memory element. For this reason, Vth to be distinguished from the drain current at the time of reading is two per element, and a sufficient interval between Vth can be obtained. However, in recent years, a demand for a large capacity and low cost of a file system using a flash memory has necessitated that two or more bits correspond to one element. This indicates that Vth to be distinguished from the drain current at the time of reading becomes four or more per element. For this reason, the interval between the respective Vths becomes narrow, and the data read error from the memory element necessarily increases.

In this case, it is required to use a stronger ECC for the encoding / decoding circuit in the memory chip in order to satisfy the required bit error uncorrectable rate by the memory chip alone.

However, in this case, the encoding / decoding circuit becomes more complicated and the decoding time becomes longer. In addition, due to the large scale of the encoding / decoding circuit of the memory chip,
As the proportion of the coding / decoding circuit in the memory chip increases and the memory mounting area decreases, the merit of increasing the memory capacity by multi-level recording cannot be used.

In addition, the uncorrectable bit error rate required when used as a file system is generally lower than the uncorrectable bit error rate required for a single memory chip.

Therefore, the code /
It is also conceivable that an encoding / decoding circuit is further provided outside the decoding circuit to lower the error uncorrectable rate as a file system.

However, if an encoding / decoding circuit for performing encoding / decoding independently from the encoding / decoding circuit in the memory chip is provided outside the memory chip, redundant data required for ECC increases, and The storage efficiency of information data is extremely low.

Therefore, the present invention can be applied to a recording / reproducing apparatus used as a file system or the like without increasing the scale of an encoding / decoding circuit in a memory chip.
An object of the present invention is to provide a memory chip and a recording / reproducing apparatus which can satisfy an error correction rate required as a recording / reproducing apparatus.

[0017]

To achieve the above object,
The present invention is a recording / reproducing apparatus using a memory chip having a built-in memory, wherein the storage / reproducing apparatus performs error correction coding of information data to be stored outside the memory chip, and generates a first error correction code. An outer code / decoding circuit for generating the first error correction code generated by the outer code / decoding circuit.
Inner error code for generating the error correction code of
/ Internal decoding circuit, the inner code / decoding circuit performs error correction using the second error correction code read from the memory, decodes the first error correction code,
The decoding circuit provides error correction using the first error correction code decoded by the inner code / decoding circuit, and decodes the information data.

According to the present storage reproducing apparatus, the inner code / decoding circuit inside the memory chip and the inner code / decoding circuit outside the memory chip are used.
A decoding circuit performs error correction coding and decoding, respectively. That is,
Since error correction processing is performed twice, a strong error correction capability of data read from the memory chip can be exhibited.
In this case, the size of the inner encoding / decoding circuit in the memory chip can be reduced as compared with the case where the error rejection rate of the present storage / reproduction device is achieved.

Further, according to such sharing of error correction between the inside and outside of the memory chip, even when the memory chip is used in a system having no outer code / decode circuit, the error caused by the inner code / decode circuit inside the memory chip can be obtained. The memory chip can be configured to secure a data error rate similar to the conventional data error rate by the correction processing.

The outer code / decoding circuit converts the information data to be stored into a matrix, performs error correction coding on each column / row of the matrix, and generates a first error correction code having a plurality of columns / rows. The inner code / decoding circuit, the first error correction code of a plurality of columns / rows generated by the outer code / decoding circuit, error correction coding of each row / column of a matrix arranged in the row / column direction, If a plurality of rows / columns of the first error correction code are generated, and the plurality of rows / columns of the first error correction codes form a product code of the information data, a code / decode in the memory chip may be performed. In addition to the circuit, a code /
As compared with the case where the decoding circuit is provided outside, less redundant data is required to achieve the same error-impossible rate. Therefore, the storage efficiency of the information data in the memory chip can be improved.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a recording / reproducing apparatus according to the present invention will be described below, taking as an example the application to a recording / reproducing apparatus used as a file system using a flash memory as a recording medium.

FIG. 1 shows a configuration of a file system according to the present embodiment.

In FIG. 1, a memory 103 is a recording medium for recording or reproducing data, and a memory chip 102 is a chip including the memory 103 and an inner encoding / decoding circuit 104. The outer code / decode circuit 105 is a circuit that is provided in the interface LSI 106 and performs outer code generation, outer code detection, and data correction. Interface LSI 106 is a flash memory
This is an LSI that controls the interface with the system bus 109 in the file system 101 using the file system 103.

More specifically, the file system according to the present embodiment can be configured as shown in FIG. 2, for example.

In FIG. 2, the flash memory 502
1 corresponds to the memory chip 102 in FIG.
And the inner encoding / decoding circuit 104 in FIG.
ECC circuit equivalent to. Interface LSI
503 is a file system using the flash memory 502
The LSI 501 controls the interface with the system bus 506 at 501, and corresponds to the interface LSI 106 of FIG. Figure 1 shows the ECC circuit 5031 in the interface LSI 503.
Corresponds to the outer code / decoding circuit 105.

The microcomputer 504 interprets the command transmitted through the system bus, and reads and writes data (Read / Write,
A central processing unit (CPU 5041) for controlling data R / W to the DRAM 505, a ROM 5042, and a RAM 5043 are provided, and play a role of a controller of the file system 501. The DRAM 505 is an auxiliary memory serving as a data buffer when passing data from the flash memory 502 to the ECC circuit 5031 in the interface LSI 503.

These units are connected by a control signal line, an address bus, and a data bus.

Here, the interface LSI 503 shown in FIG.
Is configured, for example, as shown in FIG.

In FIG. 3, a system interface unit 601 controls commands and data transmitted and received through a system bus. The microcomputer interface unit 602 controls commands and data transmitted to and received from the microcomputer 504. The DRAM control unit 603 controls data transmitted to and received from the DRAM 505. The flash memory control unit 604 controls commands transmitted to the flash memory 502 and data transmitted to and received from the flash memory 502. ECC control unit
In accordance with an instruction from the microcomputer 504, the data 605 transfers data input through the system bus 506 and data from the flash memory 502 to the ECC circuit 5031 and controls ECC correction means such as ECC generation, ECC detection and data correction.

Hereinafter, data error detection and correction processing performed in such a file system will be described.

First, before describing a specific operation, a product code used in the present embodiment will be described.

In this embodiment, the outer code / decode circuit 105 and the inner code / decode circuit 104 cooperate to perform a product code. When storing the information data, follow the format shown in FIG.
The outer code / decoding circuit 105 encodes the information data to form an outer code C
1 is generated, the inner code / decoding circuit 104 codes the outer code, generates an inner code C2, and stores it in the memory 103.

In this embodiment, the R / W of the information data is 1
The recording / reproduction data area is performed in 512-byte units. Further, in the product coding, a plurality of recording / reproducing data areas may be collectively coded, but in the present embodiment, the product coding is performed for each recording / reproducing data area. ECC used for product code
Uses a Reed-Solomon code for both the inner code C2 and the outer code C1. The correction capability of the inner code C2 is one symbol. The correction capability of the outer code C1 is two symbols, and erasure correction is performed based on the erasure flag signal from the inner code / decoding circuit 104. The erasure correction is a well-known correction method that uses an erasure flag signal to improve the error correction capability as compared with the case where error correction is performed using only the outer code C1. For erasure correction, for example,
8 of "Digital Video Recording Technology" published by Nikkan Kogyo Shimbun
It is described in pages 9 to 122 and in coding theory published by Kyoritsu Shuppan.

Assuming that the error correction capability when only the outer code C1 is used is t2 symbols, the correction capability of the erasure correction is 2 × t2 symbols at the maximum. In this embodiment, since t2 is 2, the correction capability is 4 symbols at the maximum.

There are various methods for decoding such a product code. In this embodiment, the inner code / decoding circuit is used first.
After decoding the inner code C2 in 104, the outer code C1 is decoded in the outer code / decoding circuit 105. In the product code, the closer the information data is to the square matrix data, the better the encoding efficiency is. Therefore, the information data is handled as 16-byte × 32-byte matrix data. The outer code C1 is obtained by encoding the column data of the 32-byte information data shown in FIG.
2 is 16-byte information data or outer code / decoding circuit 1
05 is obtained by encoding the row data of the redundant symbol added.

The amount of information encoded by the inner code is 16 per line.
× 8 = 128 bits, the amount of information to be encoded by the outer code is 32 × 8 = 256 bits per column. Also, the symbol length of the Reed-Solomon code is more convenient in handling data when one byte corresponds to one symbol. Therefore, in this embodiment, the number of bits of one symbol is eight, and the length of the redundant symbol is 16 A Reed-Solomon code of 32 symbols and an outer code is used.

Equation 1 shows conditions for the maximum codeword length and the maximum information amount in the Reed-Solomon code.

[0038]

(Equation 1)

T is the symbol correction capability. A Galois field is a set that contains Reed-Solomon codewords.
Corresponds to the number of bits per symbol. As m increases, the maximum codeword length and the maximum information amount increase. However, since the number of bits included per symbol increases, if the error rate per bit is the same, the number of redundant bits increases even if the correction capability t is the same. Here, assuming that the code word of the Reed-Solomon code is W, the code polynomial C (x) is
It is defined as a polynomial having each component of the codeword W as a coefficient.

In the case of the present embodiment, the minimum value of m that satisfies the condition of the symbol length is 8. At this time, the maximum codeword length is 2
Raised to the power of 8-1 = 255 symbols, the maximum amount of information is 2 raised to the power of 3-3 bytes = 253 bytes = 2024 when one symbol is corrected
When correcting bits and 2 symbols, 2 8 −5 = 251 bytes = 2008 bits, which satisfies the condition. Therefore, a set of code words of the Reed-Solomon code uses a Galois field of 2 to the power of 8 for both the inner code and the outer code. The redundant symbol length is the inner code,
2 symbols = 2 bytes, and outer symbols = 4 symbols = 4 bytes.

Hereinafter, such a product code is generated and stored in the memory 1.
A specific operation to be recorded at 05 will be described.

FIG. 5 shows a procedure of a recording process to the memory 105.

Information data is input via the system bus 109 via the system bus 109 in one recording / reproducing data area, ie, every 512 bytes, in the order of rows in FIG.

The outer code / decode circuit 105 in the interface LSI 106 converts the information data into 16-byte × 32-byte matrix data. However, when the information data is actually recorded in the memory 103, the information data is recorded as 512-byte column data. Therefore, the conversion to the matrix data is not always necessary, and the data may be handled as one-dimensional array data. In this case, the recording process to the memory may be started from step 701. In the following description, the information data is treated as one-dimensional array data,
The case where processing is performed from 1 is taken as an example.

The outer code / decoding circuit 105 encodes the matrix data or the one-dimensional array data into the outer code C1 as shown in step 701. Further, as shown in step 702, the configuration of the outer coded one-dimensional array data is converted and input to the inner coding circuit 104. FIG. 6 shows the processing of converting the 512-byte one-dimensional array data into the outer code C1 in step 701 and the processing of converting the configuration of the outer-coded one-dimensional array data in step 702.

First, in the process of converting the 512-byte one-dimensional array data into the outer code C1, the interface L
The outer code / decoding circuit 105 in the SI 106 temporarily stores the 512-byte information data in the internal memory in order, and then skips the data address by 15 bytes from the first address of the internal memory, and stores the information data in one byte. Read each. This is repeated 32 times to generate 32-byte column data (a). This operation is performed 16 times, that is, for each column of the 16-byte row data, while first increasing the address from which the information data is read, thereby generating 16 column data.

Each of the column data is subjected to Reed-Solomon encoding, and the information data portion is encoded into an outer code C1. Since the correction capability of the outer code / decoding circuit 105 is 2 symbols, the required redundant symbol length is 4 symbols. The number of redundant bytes is
4 × 8 ÷ 8 = 4 bytes. Therefore, the redundant data portion R1 of the outer code C1 has an information amount of 4 × 16 = 64 bytes.

Next, a process of converting the configuration of the outer-coded one-dimensional array data will be described. The inner encoding / decoding circuit 104 encodes the data in the row direction in FIG.
The redundant portion R1 of the outer code consisting of 16 rows × 4 columns is converted into 16 bytes (16 rows × 1 column) × 4 rows of data.

This conversion is performed by sequentially storing the redundant portion R1 of the outer code C1 generated for each column in the internal memory,
From the first address of the internal memory where the redundant data portion R1 is stored, the redundant data portion R1 is repeatedly read 16 times by 1 byte while skipping the data address by 3 bytes, thereby generating 16-byte row data ( b). This operation is repeated four times while increasing the address from which the first redundant byte is read out by one, and four row data obtained four times are sequentially added after the information data portion in FIG. The information data part of 32 lines generated in this way,
The one-dimensional array of the subsequent four rows of redundant data portion R1 is output to inner code / decoding circuit 104 as outer code C1.

Returning to FIG. 5, in the next step 703, the inner code / decoding circuit 104 in the memory chip 102 converts the input outer code C1 into an inner code C2. Further, as shown in step 704, the configuration of the inner-coded one-dimensional array data is converted and recorded in the memory 103.

In step 703, the outer code C1 is converted into the inner code C2, and in step 704,
FIG. 7 shows a process of converting the configuration of the inner-coded one-dimensional array data.

First, in the process of converting the outer code C1 to the inner code C2, the inner code / decoding circuit 104, as shown in FIG. 7, the information data portion of 512 bytes + the redundant data portion R1 of the outer code C1 of 64 bytes, That is, (32 + 4) × 16
The byte one-dimensional array data is temporarily recorded in a memory inside the inner code / decoding circuit 104, and then converted to an inner code C2.

The one-dimensional array data is input in the order of the rows in FIG. 4 in the order of the information data section and the redundant data section R1 (a). The inner encoding / decoding circuit 104 first performs Reed-Solomon encoding on the information data portion for every 16 bytes, and encodes it into an inner code C2. Next, the redundant data portion R1 of the outer code C1 is Reed-Solomon encoded every 16 bytes, and is encoded into the inner code C2.

Here, since the correction capability of the inner code / decode circuit 104 is one symbol, the required redundant symbol length is two symbols. The number of redundant bytes is 2 × 8/8 = 2 bytes. Therefore, the redundant data portion R2 of the inner code C2 is 2 × (3
2 + 4) = 72 bytes of information amount.

The information data thus product-coded is recorded in the memory 103 as one-dimensional array data in step 704 of FIG.

FIG. 8 shows a data storage format of the product code recorded in the memory 103.

One row of the memory 103 has a 512-byte information data part, a 64-byte redundant code part R1 of an outer code C1 + a redundant data part R2 + R of a 72-byte inner code C2.
/ W is composed of a management data section in which access data relating to / W is recorded.

When a flash memory is used, one-dimensional array data composed of an information data section and a management data section is collectively recorded because partial R / W of one row is difficult due to its structure. The information data and the management data section are managed separately by physical or logical partitions.

As shown in FIG. 7, the management data portion is such that the inner code / decoding circuit 104 is arranged after the outer code C 1 (a) sent from the outer code / decoding circuit 105 as shown in FIG.
A redundant portion R2 of the inner code C2 generated for each row is added, and access data is further added. However, this order may be arbitrary.

Next, the process of decoding the product code recorded in the memory 105 in this manner will be described.

FIG. 9 shows a processing procedure of this processing.

As shown in step 801, the memory 103
As shown in FIG. 10 (a), the product code read from the internal code / decoding circuit 104 is supplied to the inner code / decode circuit 104 with the outer code C1 (512-byte information data portion + 64-byte redundant data portion R1 of the outer code C1) +72. The data is input as one-dimensional array data including a redundant data portion R2 of an inner code C2 of bytes.

The inner encoding / decoding circuit 104 temporarily stores the one-dimensional array data in an internal memory as shown in step 802, and then generates 36 rows of 18-byte inner code C2. This is performed by repeating the process of reading 2 bytes from the internal memory and adding it to the information data or the redundant data portion R1 (FIG. 10B) 36 times.

Next, when the inner code C2 is generated, step 8
From step 03, in step 806, decoding processing is performed using the inner code C2. In FIG. 8, there are two steps surrounded by a dotted line, and the upper one corresponds to the decoding process of the inner code C2.

In the decoding process of the inner code C2, first, as shown in step 803, the syndrome S (x) for each row, that is, 36 18-byte inner codes C2
, And error correction and detection of the row data in FIG.

The syndrome S (x) is a pattern indicating the state of an error that has occurred in a codeword. This pattern is determined only by errors occurring in the code word regardless of the recording code word. Equation 2 defines the syndrome. Assuming that the read codeword is R (x), when the error sequence E (x) = 0, it indicates that there is no error in the read data. Then R
Since (x) = C (x), from the definition of Equation 2, S
(X) = 0. When the error sequence E (x) is non-zero, it indicates that an error has occurred in the read data. Then S
(X) becomes non-zero and becomes a simultaneous equation as defined by Expression 2.

[0067]

(Equation 2)

In the case of the Reed-Solomon code, since the error correction unit is a symbol (a plurality of bits), S (x) includes information on the position of the error symbol and the large error (corresponding to the bit error position in the symbol). . At this time, S (x)
Is represented by an error position and an error magnitude as defined by Expression 3.

[0069]

(Equation 3)

If the number of errors in the N data is within the correction capability t, the code error can be corrected by finding the error position and error magnitude from S (x) shown in Expression 3. If the number of errors exceeds the correction capability, the solution of the simultaneous equations of Equation 3 is out of the range or indeterminate, and error correction cannot be performed. In this case, error detection may be possible depending on the error pattern. However, depending on the type of error, an erroneous codeword may be estimated (erroneous correction). Inner code C of this embodiment
In the case of 2, the error correction capability t is 1.

When the calculation of the syndrome S (x) is completed, it is next determined whether or not to perform error correction / detection based on the value of S (x) as shown in step 804.

If S (x) = 0, it indicates that there is no error in the row of the inner code C2, so that the inner code / decoding circuit 104 calculates two bytes of the inner code C2 from the row of the inner code. , And outputs the 16-byte inner code C2 to the outer code / decoding circuit 105 without correcting it.

On the other hand, if S (x) is non-zero, it indicates that an error has occurred in its inner code C2.
At 05, whether the codeword is correctable is calculated using the syndrome. If the syndrome pattern calculated from the inner code C2 matches a syndrome pattern group of a specific code word, error correction is performed in step 806, and the 2-byte redundant data of the inner code C2 from the row of the inner code C2 The section R2 is removed, and the corrected 16-byte inner code C2 is output to the outer code / decoding circuit 105. If they do not match, it is assumed that an error exceeding the correction capability of the inner code C2 has occurred, and only error detection processing is performed. From the inner code row, the 2-byte redundant data portion R of the inner code C2 is read.
2 is removed and the 16-byte inner code C2 is output to the outer code / decoding circuit 105 without correction.

At this time, in order to reduce the erroneous correction of the outer code C1 caused by the erroneous correction in the inner code C2 at the time of error correction by the outer code C1, an error of more than the maximum correction capability occurred at the time of decoding the inner code C2. In this case, that is, in the case of this embodiment, when S (x) is non-zero, the inner code / decoding circuit 104
In step 807, erasure flag information is added to all the symbols in the row on which error correction / detection or only error detection has been performed, and the result is output to the outer code / decoding circuit 105.

Now, assume that the row indicated by the shaded triangle on the right side of the product code configuration diagram shown in FIG. 11 indicates the row in which an error exceeding the correction capability of the inner code C2 has occurred. 1,
Lines 2 and 6 indicate that a random error has occurred. The fourth line indicates that a burst error has occurred. In this case, erasure flag information is added to all 16-byte data corresponding to the first, second, fourth, and sixth rows. The erasure flag information is output to the outer code / decoding circuit 105 so that the byte to be added can be identified separately from the inner code decoded data.

Next, in step 808, the outer code C1 decoded by the inner code C2 in the outer code / decoding circuit 105 is arranged in columns every 36 bytes.
From step 9 to step 814, decoding processing is performed using the outer code C1. In FIG. 8, there are two steps surrounded by a dotted line, and the lower one corresponds to the decoding process of the outer code C1.

First, step 808 will be described.

The outer code / decode circuit 105 has an outer code C1
Is input as one-dimensional array data in a form in which a redundant data portion R1 is added after the information data portion as shown in FIG. 12A.

The outer code / decoding circuit 105 temporarily stores this one-dimensional array data in an internal memory, and repeats the process of reading one byte while skipping the data address by 15 bytes 36 times, 36 times, to obtain the 36 byte outer code C1. The process of generating column data is repeated 16 times while sequentially advancing the start address at which reading is started by one byte at a time.
An outer code C1 of six columns is generated.

Next, the outer code / decoding circuit 105
The syndrome S (x) is determined for each column of 1 in step 810. When S (x) = 0, it indicates that there is no error in the read one-dimensional array data, so the outer code / decoding circuit 105 determines from the sequence of the outer code
The redundant data portion R1 is removed, and the 32-byte information data portion is output without correction.

On the other hand, if S (x) is not equal to 0, then 1 is composed of the information data section + the redundant data section R1 of the outer code C1.
In step 811, the total number of bytes to which the erasure flag has been added in the 36 bytes of the column is set to Er (x).
Determine the value of r (x).

If Er (x) = 0, normal decoding using only the outer code C1 is performed in step 813 without performing correction using the erasure flag.

On the other hand, if Er (x) is non-zero, in step 812 error correction / error correction is performed according to the number of Er (x).
Perform detection. That is, if Er (x)> 4, it indicates that an error that exceeds the correction capability of the outer code C1 has occurred.
As shown in step 814, error correction is disabled. However, the syndrome S calculated from the erasure flag
When the simultaneous equations in (x) are all 0, the redundant data portion R1 is removed from the sequence of the outer code as an exception without error, and the 32-byte information data is output without correction.

When Er (x) ≦ 4, error correction becomes possible.

The error correction in the erasure correction when Er (x) ≦ 4 is performed as follows. For example, the seventh column in FIG. 10, that is, the column indicated by a white triangle at the bottom, has two or less erasure flags in the column data. In this case, even if erasure correction is used, there are only two error correction capabilities. Therefore, error correction by Reed-Solomon decoding is performed as usual using the outer code C2, the redundant data portion R1 is removed from the column of the outer code, and corrected 32-byte information data is output.

Next, for example, the eighth column, that is, the column indicated by a gray triangle at the bottom, has three erasure flags in the column data. When t2 is 2, the number of simultaneous equations of the obtained syndrome S (x) is four from the condition of Expression 2. Therefore, three equations regarding the magnitude of the error are obtained from the syndrome, and one discriminant regarding the presence or absence of an error other than the error position obtained from the erasure flag is obtained. Therefore,
If there is no error other than the error position obtained from the erasure flag, error correction is performed, the redundant data portion R1 is removed from the outer code sequence, corrected 32-byte information data is output, and the error obtained from the erasure flag is output. If there is an error other than the position, only error detection is performed, the redundant data portion R1 is removed from the column of the outer code, and the 32-byte information data is output without correction.

The sixth column, that is, the column indicated by a black triangle indicates a case where there are four erasure flags in the column data. The syndrome gives four equations for the magnitude of the error. The outer code / decode circuit 105 removes the redundant data portion R1 from the column of the outer code,
Output byte information data.

However, in this case, since the correction is performed by using the maximum correction capability, a discriminant for the presence or absence of an error other than the error position obtained from the erasure flag cannot be obtained, and the error position obtained from the erasure flag cannot be obtained. If there is an error other than the above, correct it incorrectly. Therefore, in order to perform highly reliable error correction according to the specifications required by the file system, m-out-of-n is not performed without performing maximum correction.
Erasure correction (n> m) may be performed. This is to verify whether or not the erasure flag is correct, and to correct the error only when the number of true error symbols is n or less, even if n erasure flags are detected. For example, 3-out-of-4 erasure correction is performed. In the case of the sixth column, only error detection is performed, the redundant data portion R1 is removed from the column of the outer code, and 32 bytes of information are removed. The data may be output without correction.

Here, the information data portion is the system bus 10
9 is output.

The file system according to the present embodiment has been described.

In the following, the memory chip 102 is designated by an outer code /
A case in which error correction / detection is used alone without being combined with the decoding circuit 105 will be described.

FIG. 13 shows the structure of the memory chip 102. The memory 103 is a recording medium for recording or reproducing data, and the memory chip 102 is a memory 1
03 and the inner code / decoding circuit 104. The inner encoding / decoding circuit 104 is the same circuit as the inner encoding / decoding circuit in FIG.

FIG. 14 shows a procedure of a recording process in the memory 103 in this case.

When using the memory chip 102 alone,
The information data input through the system bus 109 is 1
The data is input to the inner encoding / decoding circuit 104 as one-dimensional array data every recording / reproducing data area, that is, every 512 bytes.

The inner code / decoding circuit 104 in the memory chip 102 first converts the matrix data or the one-dimensional array of information data into the inner code C1 in step 1601. That is, as shown in FIG. 15A, the inner encoding / decoding circuit 104 once records the 512-byte information data in the internal memory,
6-byte row data is generated and encoded into the inner code C2.
In the case of one-symbol correction, the required redundant symbol length is two symbols. Therefore, the number of redundant bytes is 2 ×
8 ÷ 8 = 2 bytes. Therefore, the information amount of the redundant data portion R2 of the inner code C2 for one recording / reproducing data area is 2 ×
32 = 64 bytes.

Next, the inner code / decoding circuit 104 converts the data structure in step 1602. That is, as shown in FIG. 15B, the inner code C2 is converted into a one-dimensional array in which the redundant data portion R2 of each row and the access data are added after the information data portion of each row.

The information data encoded in this way is shown in FIG.
In step 1603, the data is recorded in the memory 103 as one-dimensional array data.

Next, the inner code C2 recorded in the memory 103
Will be described.

FIG. 17 shows the processing procedure of this processing.

First, in step 1701, the inner code C2 for one row is read from the memory 103 to the inner code circuit / decode circuit 104. As shown in FIG. 18, the inner encoding / decoding circuit 104 receives the input 512-byte information data +
From the one-dimensional array data a including the 64-byte inner code redundant data R2, 32 rows of the 18-byte inner code C2 are generated.

This is because once the one-dimensional array data is recorded in the internal memory, every time the 16-byte information data is read, two bytes are read from the head of the redundant data portion R2 of the inner code C2, and the 16-byte information data is read. The process of adding (b)
This is performed by repeating 32 times.

Next, when the inner code C2 is generated, step 1
From step 703 to step 1706, a decoding process is performed using the inner code C2. In FIG. 17, a step group surrounded by a dotted line corresponds to the decoding process of the inner code C2.

In the decoding process of the inner code C2, first, as shown in step 1703, the generated inner code C2
Is calculated for each row of. Next, as shown in step 1704, it is determined whether to perform error correction / detection based on the value of S (x).

In step 1704, S (x) = 0
Indicates that there is no error in the read row,
The inner encoding / decoding circuit 104 determines that the redundant data R2
And outputs the 16-byte information data portion without correction.

On the other hand, if S (x) is non-zero, it indicates that an error has occurred in that row.
As shown at 705, it is determined whether the codeword is correctable using the syndrome. If the syndrome pattern calculated from the inner code C2 matches the syndrome pattern group of a specific codeword, the process proceeds to step 17.
At 06, error correction is performed, the redundant data portion R2 is removed from the row, and a corrected 16-byte information data portion is output. If they do not match, it is considered that an error exceeding the correction capability of the inner code C2 has occurred. Only the error detection processing is performed, the redundant data portion R2 is removed from the row, and the 16-byte information data portion is output without correction. At this time, as in the case described above, the erasure flag information is output as an uncorrectable signal.

The case where the memory chip 102 is used without being combined with the outer code / decoding circuit 105 has been described above.

As understood from the above description, according to the present embodiment, when the memory chip is used as a storage medium of the file system 101 provided with the outer code / decoding circuit, a strong error correction capability is exhibited. As a result, sufficient error correction capability can be provided even when the data read error rate increases due to the multi-value storage of the memory element of the memory 103.

Further, even when the memory chip 102 is used in a system having no outer code / decoding circuit, it is possible to secure a data error rate similar to the conventional data error rate.

In the present embodiment, since the information data portion and the management data portion are recorded separately, the encoding method adopted by the inner code / decoding circuit and the outer code / decoding circuit can be prepared according to the application. Can be changed. Further, as compared with a case where a strong error correction code is encoded / decoded only by the outer code / decoding circuit, there is an advantage in decoding time and memory use efficiency.

In the present embodiment, the method of using the inner code / outer code processed inside / outside the memory chip is performed by changing the method correction capability of the error correction code used for the product code. This is a method capable of satisfying various required specifications required for the memory chip 102.

The file system according to the present embodiment can be applied to a digital camera, a storage device for a portable information terminal device, and the like. In this case, the memory chip 102 constitutes a removable storage medium detachable for a digital camera or a portable information terminal device, for example, a flash memory card which is a card-type storage medium containing a flash memory. The decoding circuit is provided on the digital camera or the portable information terminal device body side.

[0112]

As described above, according to the present invention, recording / reproducing can be performed even when used in a recording / reproducing apparatus used as a file system or the like without increasing the size of the encoding / decoding circuit in the memory chip. It is possible to provide a memory chip and a recording / reproducing device which can satisfy an error correction unrequired rate required as a device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a file system.

FIG. 2 is a block diagram illustrating a specific configuration example of a file system.

FIG. 3 is a block diagram illustrating a configuration of an interface LSI.

FIG. 4 is a diagram showing a configuration of a product code in the file system.

FIG. 5 is a flowchart showing an encoding process in the file system.

FIG. 6 is a diagram showing a state of encoding to an outer code in a file system.

FIG. 7 is a diagram showing a state of encoding for generating an inner code in the file system.

FIG. 8 is a diagram showing a storage format on a memory in the file system.

FIG. 9 is a flowchart showing a decryption process in the file system.

FIG. 10 is a diagram showing a state of conversion to an inner code at the time of decoding in the file system.

FIG. 11 is a diagram showing an erasure flag and an erasure correction target in the file system.

FIG. 12 is a diagram showing a state of conversion to an outer code at the time of decoding in the file system.

FIG. 13 is a block diagram illustrating a configuration of a memory chip.

FIG. 14 is a flowchart showing an encoding process when a single memory chip is used.

FIG. 15 is a diagram showing a state of encoding to an inner code when a single memory chip is used.

FIG. 16 is a diagram showing a storage format on a memory when a single memory chip is used.

FIG. 17 is a flowchart showing a decoding process when a single memory chip is used.

FIG. 18 is a diagram showing a state of conversion to an inner code when a memory chip is used alone.

FIG. 19 is a diagram showing a configuration of a flash memory device.

FIG. 20 is a diagram showing a relationship between a floating gate charge, a drain current, and a control voltage of a flash memory device.

[Explanation of symbols]

 101 File System 102 Memory Chip 103 Memory 104 Inner Code / Decode Circuit 105 Outer Code / Decode Circuit 106 Interface LSI 109 System Bus 501 File System 502 Flash Memory 506 System Bus 504 Microcomputer 5031 ECC Circuit

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Hiroaki Kotani 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Atsushi Nozoe 2326, Imai, Ome-shi, Tokyo Hitachi, Ltd.Device Development Center (72) Inventor Shigemasa Shiota 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Yukari Katayama 1099 Ozenji Temple, Aso-ku, Kawasaki-shi, Kanagawa Hitachi Systems, Ltd. Inside the development laboratory

Claims (10)

[Claims] 1. A recording / reproducing apparatus using a memory chip having a built-in memory, wherein the storage / reproducing apparatus performs error correction encoding of information data to be stored outside the memory chip, and a first error correction code. An outer code / decoding circuit that generates the first error correction code generated by the outer code / decoding circuit is further subjected to error correction coding to generate a second error correction code, and the memory chip An inner code / decoding circuit that stores therein, the inner code / decoding circuit performs error correction using a second error correction code read from the memory, and decodes the first error correction code. The storage / reproducing apparatus, wherein the outer code / decoding circuit performs error correction using the first error correction code decoded by the inner code / decoding circuit, and decodes the information data. 2. The storage / reproducing apparatus according to claim 1, wherein the inner code / decoding circuit has means for outputting position information indicating a position of an error for which error correction could not be performed; A decoding circuit, in addition to the first error correction code decoded by the inner code / decoding circuit, performs an error correction using position information output from the inner code / decoding circuit; . 3. The storage / playback apparatus according to claim 1, wherein said inner code / decoding circuit determines an error correction or error detection position according to a correction capability of said second error correction code. Means for outputting position information indicating, the outer code / decoding circuit, in addition to the first error correction code decoded by the inner code / decoding circuit, the position information output from the inner code / decoding circuit A storage / reproducing apparatus, which performs error correction using a program. 4. The storage reproducing apparatus according to claim 1, wherein the outer code / decoding circuit treats the information data to be stored as a matrix, and performs error correction coding on each column / row of the matrix. Generating a first error correction code of a plurality of columns / rows, the inner code / decoding circuit outputs the first error correction code of a plurality of columns / rows generated by the outer code / decoding circuit in the row / column direction. Each row / column of the arranged matrix is error-correction coded, and multiple rows /
Generate a first error correction code for the column, and
Wherein the error correction code forms a product code of the information data. 5. The storage / reproducing apparatus according to claim 1, wherein at least one of the first error correction code and the second error correction code is a Reed-Solomon code. Storage and playback device. 6. An error correction method in a recording / reproducing apparatus using a memory chip having a built-in memory, wherein the storage / reproducing apparatus performs error correction coding on information data to be stored outside the memory chip, and In the memory chip, the first error correction code generated by the outer code / decoding circuit is further subjected to error correction coding to generate a second error correction code, and stored in the memory. In the memory chip, error correction is performed using the second error correction code read from the memory, and the first error correction code is decoded. An error correction method comprising: performing error correction using a first error correction code decoded by the inner code / decoding circuit; and decoding the information data. 7. A first error correction code read from said memory, wherein said first error correction code is generated by error correction encoding data to be written to a memory supplied from outside and generating said first error correction code. A method of using a memory chip incorporating a first encoding / decoding circuit that decodes the data and outputs the decoded data to the outside, wherein the information data requested to be written is error-corrected and encoded. 2
Use the memory chip in a storage device including a second encoding / decoding circuit that generates an error correction code, performs error correction using the first error correction code, and decodes read-requested information data. In this case, as the data to be written into the memory, the second error correction code is supplied in the second encoding / decoding circuit and a second error correction code is supplied, and the data decoded and output by the first encoding / decoding circuit is output. Is supplied to a second code decoding circuit as a first error correction code to be subjected to the error correction, and in a storage / reproduction device not provided with the second coding / decoding circuit, the memory device uses the memory chip. When writing, the information data requested to be written is
A method of using a memory chip, wherein the data is supplied as data to be written to the memory to the code decoding circuit, and the data decoded and output by the first coding / decoding circuit is used as the read-requested information data. 8. A first error correction code read from the memory, wherein the data to be written to the memory and an externally supplied memory are error correction encoded, a first error correction code is generated and stored in the memory. A first encoding / decoding circuit that performs error correction using the above, decodes the data, and outputs the data to the outside, and the inner encoding / decoding circuit externally outputs position information indicating the position of the error for which error correction could not be performed. And a means for outputting to the memory chip. 9. A first error correction code read from the memory, wherein the data to be written to the externally supplied memory is error correction encoded, a first error correction code is generated and stored in the memory. A first encoding / decoding circuit that decodes the data and outputs the data to the outside, and wherein the inner encoding / decoding circuit performs error correction or Means for outputting, to the outside, position information indicating the position of an error for which an error has been detected. 10. A controller for controlling writing and reading of a memory chip for outputting position information indicating an error position included in read data, wherein the controller corrects an error correction code for the information data to be stored and converts the error correction code into an error correction code. Generated and supplied as write data to the memory chip, perform error correction using the first error correction code read from the memory chip, and the position information output from the memory chip, the information data A controller comprising an encoding / decoding circuit for decoding.