JP5693961B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5693961B2 JP5693961B2 JP2010529764A JP2010529764A JP5693961B2 JP 5693961 B2 JP5693961 B2 JP 5693961B2 JP 2010529764 A JP2010529764 A JP 2010529764A JP 2010529764 A JP2010529764 A JP 2010529764A JP 5693961 B2 JP5693961 B2 JP 5693961B2
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- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Description
[本発明の第1の実施の形態に係る半導体装置の構造]
始めに、本発明の第1の実施の形態に係る半導体装置の構造について説明する。図3は、本発明の第1の実施の形態に係る半導体装置を例示する断面図である。図3を参照するに、本発明の第1の実施の形態に係る半導体装置10は、半導体基板11c、半導体基板21c、半導体基板31c、半導体基板41c、半導体基板51c、半導体基板61c、半導体基板71cが積層された構造を有する。半導体装置10は、例えばCMOS・LSI、メモリーデバイス、センサーデバイス、MEMS等である。
続いて、本発明の第1の実施の形態に係る半導体装置の製造工程について説明をする。図4A〜図4Tは、本発明の第1の実施の形態に係る半導体装置の製造工程を例示する図である。図4A〜図4Tにおいて、図3に示す半導体装置10と同一構成部分には同一符号を付し、その説明を省略する場合がある。
半導体基板11の直径φ1は、例えば6インチ(約150mm)、8インチ(約200mm)、12インチ(約300mm)等である。半導体基板11の厚さT1は、例えば0.625mm(φ1=6インチの場合)、0.725mm(φ1=8インチの場合)、0.775mm(φ1=12インチの場合)等である。本実施の形態では、半導体基板11として、8インチ(約200mm)のシリコンウェハを用いた場合を例にとり、以下の説明を行う。
第1の実施の形態では、半導体基板21の面21bに、半導体基板21の外縁部(複数の半導体チップ形成領域Aを除く部分)のみを残し、中心部近傍(複数の半導体チップ形成領域Aを含む部分)を薄型化するように凹部21xを形成することにより、凹部21xを形成した後の半導体基板21cが十分な剛性を維持する例を示した。しかしながら、凹部21xを形成せずに半導体基板21の面21b側全体を薄型化しても構わない。この場合には、以下のような製造工程とすることができる。
[本発明の第2の実施の形態に係る半導体装置の構造]
始めに、本発明の第2の実施の形態に係る半導体装置の構造について説明する。図6は、本発明の第2の実施の形態に係る半導体装置を例示する断面図である。同図中、図3と同一構成部分には同一符号を付し、その説明は省略する場合がある。本発明の第2の実施の形態に係る半導体装置10Aは、隣接する半導体基板の金属パッド同士を接続するビアホール及び金属層が、1個から4個に変更された点を除いて、本発明の第1の実施の形態に係る半導体装置10と同様に構成される。
続いて、本発明の第2の実施の形態に係る半導体装置の製造工程について説明をする。図7A〜図7Fは、本発明の第2の実施の形態に係る半導体装置の製造工程を例示する図である。図7A〜図7Fにおいて、図6に示す半導体装置10Aと同一構成部分には同一符号を付し、その説明を省略する場合がある。又、本発明の第1の実施の形態に係る半導体装置の製造工程と類似する部分に関しては、説明を省略する場合がある。
[本発明の第3の実施の形態に係る半導体装置の構造]
始めに、本発明の第3の実施の形態に係る半導体装置の構造について説明する。図8は、本発明の第3の実施の形態に係る半導体装置を例示する断面図である。同図中、図6と同一構成部分には同一符号を付し、その説明は省略する場合がある。本発明の第3の実施の形態に係る半導体装置10Bは、本発明の第2の実施の形態に係る半導体装置10Aでは4個のビアホール及び金属層に対して1個設けられていた金属パッドを、1個のビアホール及び金属層に対して1個設けるようにした点を除いて、本発明の第2の実施の形態に係る半導体装置10Aと同様に構成される。
続いて、本発明の第3の実施の形態に係る半導体装置の製造工程について説明をする。図9A〜図9Fは、本発明の第3の実施の形態に係る半導体装置の製造工程を例示する図である。図9A〜図9Fにおいて、図8に示す半導体装置10Bと同一構成部分には同一符号を付し、その説明を省略する場合がある。又、本発明の第1の実施の形態又は第2の実施の形態に係る半導体装置の製造工程と類似する部分に関しては、説明を省略する場合がある。
[本発明の第4の実施の形態に係る半導体装置の構造]
始めに、本発明の第4の実施の形態に係る半導体装置の構造について説明する。図10は、本発明の第4の実施の形態に係る半導体装置を例示する断面図である。同図中、図8と同一構成部分には同一符号を付し、その説明は省略する場合がある。本発明の第4の実施の形態に係る半導体装置10Cは、本発明の第3の実施の形態に係る半導体装置10Bでは全ての半導体基板の全てのビアホールに対応する位置に設けられていた金属パッドを、一部設けないようにし、金属パッドが設けられた半導体基板同士をビアホール及び金属層で直接接続している点を除いて、本発明の第3の実施の形態に係る半導体装置10Bと同様に構成される。
続いて、本発明の第4の実施の形態に係る半導体装置の製造工程について説明をする。図11A〜図11Hは、本発明の第4の実施の形態に係る半導体装置の製造工程を例示する図である。図11A〜図11Hにおいて、図10に示す半導体装置10Cと同一構成部分には同一符号を付し、その説明を省略する場合がある。又、本発明の第1の実施の形態から第3の実施の形態に係る半導体装置の製造工程と類似する部分に関しては、説明を省略する場合がある。
第1〜第4の実施の形態では、半導体チップを有する複数の半導体基板を積層し、異なる層の半導体基板を構成する半導体チップ同士を信号伝達可能に接続する半導体装置の製造方法を例示した。しかしながら、積層する基板は全て半導体チップを有する半導体基板でなくてもよく、半導体チップを有しない構造層を一部に含んでいても構わない。そこで、第5の実施の形態では、半導体チップを有しない構造層を含む半導体装置の製造方法を例示する。ここで、構造層とは、シリコン基板、金属層、絶縁層等を含む半導体チップを有しない全ての層を指すものとする。
始めに、本発明の第5の実施の形態に係る半導体装置の構造について説明する。図12は、本発明の第5の実施の形態に係る半導体装置を例示する断面図である。同図中、図3と同一構成部分には同一符号を付し、その説明は省略する場合がある。本発明の第5の実施の形態に係る半導体装置10Dは、図3に示す本発明の第1の実施の形態に係る半導体装置10の樹脂層66と半導体基板71cとの間に構造層81及び樹脂層86を設けた点を除いて、半導体装置10と同様に構成される。
続いて、本発明の第5の実施の形態に係る半導体装置の製造工程について説明をする。
第1〜第4の実施の形態では、半導体チップを有する複数の半導体基板を積層し、異なる層の半導体基板を構成する半導体チップ同士を信号伝達可能に接続する半導体装置の製造方法(WOW)を例示した。又、第5の実施の形態では、半導体チップを有しない構造層を含む半導体装置の製造方法を例示した。第6の実施の形態では、WOWに周知の半導体装置の工程(所謂前工程や後工程)も含めた半導体装置全体の製造工程について例示する。
11,11c,21c,31c,41c,51c,61c,71c 半導体基板
11a,11b,16a,21a,21b 面
11x 外縁部
12,22 基板本体
13,23 半導体集積回路
14,24,28 絶縁層
15,15a,15b,25,25a,25b,35,35a,35b,45,45a,45b,55,55a,55b、65,65a,65b,75,75a,75b 電極パッド
16,26,36,46,56,66,76,86 樹脂層
21x 凹部
21y,21z,31y,31z,41y,41z,51y,51z,61y,61z,71y,71z ビアホール
27,37 レジスト膜
29,38,38a,39,39a,38b,48,48a,58,58a,68,68a,78,78a,88,88a 金属層
27x,27y,27z,37x,37y,76x 開口部
81 構造層
81c シリコン基板
81d 絶縁膜
81x 溝
91 外部接続端子
96 接着層
97 支持体
A 半導体チップ形成領域
B スクライブ領域
C 切断位置
D1、D2 深さ
H1 高さ
T1〜T3 厚さ
φ1〜φ7 直径
Claims (16)
- 主面側に半導体集積回路を有する複数の半導体チップが形成された半導体基板を、全ての前記半導体基板の主面が同一方向を向くように積層し、異なる層の前記半導体基板を構成する前記半導体チップ同士を信号伝達可能に接続し、その後前記半導体チップ部分を個片化する半導体装置の製造方法であって、
第1の半導体基板及び第2の半導体基板を準備する第1工程と、
前記第2の半導体基板を薄型化する第2工程と、
薄型化された前記第2の半導体基板の主面と反対側の面を、絶縁層を介して前記第1の半導体基板の主面に固着する第3工程と、
薄型化された前記第2の半導体基板に、前記第2の半導体基板の主面から主面と反対側の面に貫通するビアホールを、前記第2の半導体基板の主面側から前記反対側の面に向かって形成する第4工程と、
前記ビアホールを介して、前記第1の半導体基板の前記半導体チップと前記第2の半導体基板の前記半導体チップとの間の信号伝達を可能にする接続部を形成する第5工程と、を有することを特徴とする半導体装置の製造方法。 - 更に、他の半導体基板を準備し、前記他の半導体基板に前記第2工程から前記第5工程と同様の工程を繰り返し、前記第2の半導体基板上に他の半導体基板を積層する第6工程を有することを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第2工程では、前記第2の半導体基板の所定の領域のみを薄型化することを特徴とする請求項1記載の半導体装置の製造方法。
- 前記所定の領域は、外縁部を除く領域であることを特徴とする請求項3記載の半導体装置の製造方法。
- 前記第3工程より前に、前記第1の半導体基板の外縁部を除去する工程を有することを特徴とする請求項4記載の半導体装置の製造方法。
- 前記第3工程より後に、前記第2の半導体基板の外縁部を除去する工程を有することを特徴とする請求項5記載の半導体装置の製造方法。
- 前記半導体基板は、平面視略円形形状であることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記接続部は、前記半導体チップ同士を電気信号により接続することを特徴とする請求項1記載の半導体装置の製造方法。
- 前記接続部は、前記半導体チップ同士を光信号により接続することを特徴とする請求項1記載の半導体装置の製造方法。
- 積層された前記半導体基板の一部に、前記半導体基板と絶縁された、半導体チップを有しない構造層を含むことを特徴とする請求項1記載の半導体装置の製造方法。
- 前記構造層は、基板、金属層又は絶縁層であることを特徴とする請求項10記載の半導体装置の製造方法。
- 前記構造層は、前記半導体基板を冷却する機能を有することを特徴とする請求項10記載の半導体装置の製造方法。
- 前記構造層はMEMSを有することを特徴とする請求項10記載の半導体装置の製造方法。
- 前記第2工程において薄型化された部分の前記半導体基板の厚さは、前記半導体基板の有するデバイスの素子分離深さの5倍以上であることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第2工程において薄型化された部分の前記半導体基板の厚さは1μm以上であることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第4工程において形成されたビアホールのアスペクト比は、0.5以上5以下であることを特徴とする請求項1記載の半導体装置の製造方法。
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EP2325882A4 (en) | 2017-01-04 |
EP2325882A1 (en) | 2011-05-25 |
KR20110059854A (ko) | 2011-06-07 |
CN102160177A (zh) | 2011-08-17 |
JP2015073128A (ja) | 2015-04-16 |
TW201025505A (en) | 2010-07-01 |
US8415202B2 (en) | 2013-04-09 |
TWI470739B (zh) | 2015-01-21 |
KR101615990B1 (ko) | 2016-04-28 |
US20110165730A1 (en) | 2011-07-07 |
CN102160177B (zh) | 2015-01-21 |
WO2010032729A1 (ja) | 2010-03-25 |
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