JPS6453440A - Three-dimensional semiconductor integrated circuit device - Google Patents

Three-dimensional semiconductor integrated circuit device

Info

Publication number
JPS6453440A
JPS6453440A JP20931787A JP20931787A JPS6453440A JP S6453440 A JPS6453440 A JP S6453440A JP 20931787 A JP20931787 A JP 20931787A JP 20931787 A JP20931787 A JP 20931787A JP S6453440 A JPS6453440 A JP S6453440A
Authority
JP
Japan
Prior art keywords
chips
sheets
maintenance
connector
exchange
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20931787A
Other languages
Japanese (ja)
Inventor
Moritoshi Yasunaga
Minoru Yamada
Kenichi Mizuishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP20931787A priority Critical patent/JPS6453440A/en
Publication of JPS6453440A publication Critical patent/JPS6453440A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To reduce time for inserting and pulling-out a chip at the time of maintenance and exchange accompanying an increase in the number of sheets of longitudinally stacked chips by a method wherein connection chips provided with a connector, which is easily detachable and is electrically connected, are provided. CONSTITUTION:A plurality of sheets of chips or wafers 1 are stacked longitudinally to each other, are connected electrically to each other at surfaces A and moreover, are fixed mechanically to each other. Chip groups 3, each consisting of a plurality of sheets of the chips, are connected to each other at surfaces B through con nection chips 2 having a connector, which is an easily detachable electrical connecting means. For example, in the case where 100 sheets of the chips 1 are stacked longitudinally, if 20 sheets of the chips 1 are collected into one chip group 3, the total is constituted of 5 maintenance and exchange units and the time needed for maintenance and exchange can be reduced. The connector structures appear only at 4 places among 100 sheets if the chips 1 and the effect to inflict on the high-speed operating efficiency of a whole device is little.
JP20931787A 1987-08-25 1987-08-25 Three-dimensional semiconductor integrated circuit device Pending JPS6453440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20931787A JPS6453440A (en) 1987-08-25 1987-08-25 Three-dimensional semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20931787A JPS6453440A (en) 1987-08-25 1987-08-25 Three-dimensional semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6453440A true JPS6453440A (en) 1989-03-01

Family

ID=16570949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20931787A Pending JPS6453440A (en) 1987-08-25 1987-08-25 Three-dimensional semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6453440A (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426566A (en) * 1991-09-30 1995-06-20 International Business Machines Corporation Multichip integrated circuit packages and systems
US5502667A (en) * 1993-09-13 1996-03-26 International Business Machines Corporation Integrated multichip memory module structure
US5561622A (en) * 1993-09-13 1996-10-01 International Business Machines Corporation Integrated memory cube structure
US5783870A (en) * 1995-03-16 1998-07-21 National Semiconductor Corporation Method for connecting packages of a stacked ball grid array structure
JP2004152810A (en) * 2002-10-28 2004-05-27 Sharp Corp Semiconductor device and laminated semiconductor device
JP2004152812A (en) * 2002-10-28 2004-05-27 Sharp Corp Semiconductor device and stacked semiconductor device
JP2006270098A (en) * 2005-03-24 2006-10-05 Memsic Inc Wafer level package for integrated circuit
JP2007514299A (en) * 2003-10-31 2007-05-31 インテル コーポレイション Use of an external radiator with an electroosmotic pump to cool integrated circuits.
JP2009507426A (en) * 2005-09-02 2009-02-19 ノースロップ グラマン コーポレイション 3DMMIC balun and manufacturing method thereof
JP2009512215A (en) * 2005-10-13 2009-03-19 インテル・コーポレーション Integrated microchannel for 3D through silicon architecture
WO2009119166A1 (en) * 2008-03-24 2009-10-01 日本電気株式会社 Semiconductor optical interconnection device and semiconductor optical interconnection method
JP2010153799A (en) * 2008-12-24 2010-07-08 Internatl Business Mach Corp <Ibm> Bonded semiconductor structure containing cooling mechanism, and forming method of the same
JP2011097008A (en) * 2009-10-28 2011-05-12 Headway Technologies Inc Method of manufacturing layered chip package
JP2012009808A (en) * 2010-06-28 2012-01-12 Headway Technologies Inc Laminated semiconductor substrate, laminated chip package and method of manufacturing the same
JP2013098212A (en) * 2011-10-28 2013-05-20 Fujitsu Ltd Semiconductor device and manufacturing method of the same
JP2015073128A (en) * 2008-09-18 2015-04-16 国立大学法人 東京大学 Semiconductor device manufacturing method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5948950A (en) * 1982-09-13 1984-03-21 Agency Of Ind Science & Technol Manufacture of three-dimensional integrated circuit structure
JPS6079763A (en) * 1983-10-07 1985-05-07 Hitachi Ltd Semiconductor device
JPS60206058A (en) * 1984-03-30 1985-10-17 Fujitsu Ltd Manufacture of multilayer semiconductor device
JPS61288456A (en) * 1985-06-17 1986-12-18 Fujitsu Ltd Manufacture of multilayer semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5948950A (en) * 1982-09-13 1984-03-21 Agency Of Ind Science & Technol Manufacture of three-dimensional integrated circuit structure
JPS6079763A (en) * 1983-10-07 1985-05-07 Hitachi Ltd Semiconductor device
JPS60206058A (en) * 1984-03-30 1985-10-17 Fujitsu Ltd Manufacture of multilayer semiconductor device
JPS61288456A (en) * 1985-06-17 1986-12-18 Fujitsu Ltd Manufacture of multilayer semiconductor device

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426566A (en) * 1991-09-30 1995-06-20 International Business Machines Corporation Multichip integrated circuit packages and systems
US5502667A (en) * 1993-09-13 1996-03-26 International Business Machines Corporation Integrated multichip memory module structure
US5561622A (en) * 1993-09-13 1996-10-01 International Business Machines Corporation Integrated memory cube structure
US5783870A (en) * 1995-03-16 1998-07-21 National Semiconductor Corporation Method for connecting packages of a stacked ball grid array structure
JP2004152810A (en) * 2002-10-28 2004-05-27 Sharp Corp Semiconductor device and laminated semiconductor device
JP2004152812A (en) * 2002-10-28 2004-05-27 Sharp Corp Semiconductor device and stacked semiconductor device
JP2007514299A (en) * 2003-10-31 2007-05-31 インテル コーポレイション Use of an external radiator with an electroosmotic pump to cool integrated circuits.
JP2006270098A (en) * 2005-03-24 2006-10-05 Memsic Inc Wafer level package for integrated circuit
JP2009507426A (en) * 2005-09-02 2009-02-19 ノースロップ グラマン コーポレイション 3DMMIC balun and manufacturing method thereof
JP2009512215A (en) * 2005-10-13 2009-03-19 インテル・コーポレーション Integrated microchannel for 3D through silicon architecture
WO2009119166A1 (en) * 2008-03-24 2009-10-01 日本電気株式会社 Semiconductor optical interconnection device and semiconductor optical interconnection method
US8363989B2 (en) 2008-03-24 2013-01-29 Nec Corporation Semiconductor optical interconnection device and semiconductor optical interconnection method
JP2015073128A (en) * 2008-09-18 2015-04-16 国立大学法人 東京大学 Semiconductor device manufacturing method
JP2010153799A (en) * 2008-12-24 2010-07-08 Internatl Business Mach Corp <Ibm> Bonded semiconductor structure containing cooling mechanism, and forming method of the same
JP2011097008A (en) * 2009-10-28 2011-05-12 Headway Technologies Inc Method of manufacturing layered chip package
JP2012009808A (en) * 2010-06-28 2012-01-12 Headway Technologies Inc Laminated semiconductor substrate, laminated chip package and method of manufacturing the same
JP2013098212A (en) * 2011-10-28 2013-05-20 Fujitsu Ltd Semiconductor device and manufacturing method of the same

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