JP5617405B2 - DATA REPRODUCING CIRCUIT, STATION-SIDE OPTICAL TRANSMITTER / RECEIVER AND DATA REPRODUCING METHOD - Google Patents

Description

  The present invention relates to a data recovery circuit, a station-side optical transmitter / receiver, and a data recovery method for sampling and reproducing input burst data.

  In an access optical transmission system in which an optical fiber is connected to a station side optical transceiver (OLT) and a subscriber side optical transceiver (ONU) using an optical fiber, there are many OLTs using an optical splitter. By accommodating the ONU, the apparatus cost per subscriber can be reduced.

  The form of such an access optical transmission system is called PON (Passive Optical Network) and has become mainstream in recent FTTH (Fiber To The Home) systems (for example, see Non-Patent Document 1).

  In the PON network, in order to accommodate upstream signals from a plurality of ONUs in one OLT, a TDMA (Time Division Multiplex Access) system in which optical signals from each ONU are temporally multiplexed is applied. For this reason, the optical signal from each ONU is a burst signal that is intermittent in time, and the distance of the transmission line fiber connecting the ONT to each ONU is not uniform, so that the phase information of each burst optical signal is different. .

  The data recovery (CDR: Clock and Data Recovery) circuit in the OLT receiver extracts the phase information from the burst signal as a clock signal within a desired overhead time at high speed from the burst signal, and inputs it using the extracted clock. It is required to replay data with retiming. For example, the CDR overhead time defined as a standard specification in Non-Patent Document 1 is 400 ns or less, which corresponds to a frequency / phase information amount of 500 bits or less with respect to an input data bit rate of 1.25 Gbps.

  In a general feedback control type PLL (Phase Locked Loop), it is difficult to accurately extract a clock signal from such a small amount of frequency / phase information. Therefore, a conventional technique for extracting a clock signal from such a burst signal at high speed and reproducing the data has been proposed (for example, Non-Patent Document 2).

  A conventional data reproduction circuit described in Non-Patent Document 2 will be described. FIG. 14 is a configuration diagram of a conventional data reproduction circuit. The conventional data reproduction is composed of a reference clock generation means 10, an N phase clock generation means 20, a sampling means 30, and a phase selection logic circuit 40. The phase selection logic circuit 40 includes a change phase detection means 401, An identification phase determination unit 402 and a data selection unit 403 are provided. Hereinafter, N represents a positive integer.

  The reference clock generation means 10 generates a continuous reference clock, and the N-phase clock generation means 20 generates N-phase clocks having different phases by 1 / N period synchronized with the reference clock. The sampling unit 30 samples the burst input data output from the optical receiver (not shown in FIG. 12) with the N phase clock generated by the N phase clock generating unit.

  The change phase detection unit 401 detects a change in the rising and falling phases of the pulse of the sampling data output from the sampling unit 30. The identification phase determination unit 402 determines the identification phase at the position closest to the center of the bit width of the input data based on the information on the change phase detected by the change phase detection unit 401. The data selection means 403 selects the data sampled with the clock of the phase determined by the identification phase determination means 402 from the sampling data output from the sampling means 30, performs retiming with the reference clock, and outputs it as reproduction data I do.

  By doing so, a data recovery circuit is provided that can extract a clock signal from an input burst signal at high speed and perform data recovery.

IEEE Standard 802.3av, (2009). H. Tagami et al., "Burst-mode Bit-synchronization IC with Large tolerance for Pulse-width Distortion for Gigabit Ethernet® PON", IEEE JOURNAL OF SOLID-STATE CIRCUIT, Vol.41, No.11, ( 2006).

  However, in order to realize high-speed clock extraction and data recovery, the above-described conventional data recovery circuit determines the identification phase at intervals of about 10 bits with respect to the input data bit rate of 1.25 Gbps (non-delayed). (See TABLE 1 in Patent Document 2). That is, it is necessary to perform an identification phase determination operation every very short time interval of about 8 ns. Therefore, there is a problem that the amount of data processing in the phase selection logic circuit 40 is large and the power consumption becomes high.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a data reproduction circuit, a station-side optical transmission / reception apparatus, and a data reproduction method that are high speed and low in power consumption.

  A data recovery circuit according to the present invention includes a multi-phase clock generation unit that generates a plurality of clocks frequency-synchronized with a reference clock, a sampling unit that samples input data using the plurality of clocks, and outputs a plurality of sampling data. A change phase detection means for detecting a change phase representing a rise or fall of a pulse of the sampling data, and an identification phase for sampling the input data based on the change phase information detected by the change phase detection means An identification phase determining means for determining, data selecting means for selecting data sampled by the clock of the identification phase and outputting reproduction data among the plurality of sampling data, and fluctuations in the identification phase within a predetermined range Convergence to indicate that it has converged. Convergence determining means for outputting an intelligent signal, detection operation control means for stopping the change phase detection operation of the change phase detection means for a predetermined time based on the convergence notification signal, and based on the convergence notification signal Identification phase holding means for holding a convergence phase that is a phase when converged on the identification phase determination means for the predetermined time, and stopping the change phase detection operation. During the predetermined time, data sampled at the convergence phase is selected from the plurality of sampling data, and reproduction data is output.

  According to the data recovery circuit of the present invention, there are effects that clock extraction and data recovery can be performed at high speed from input data that is intermittent in bursts and different in phase information, and power consumption can be reduced.

1 shows a schematic configuration diagram of a data reproduction circuit according to a first embodiment of the present invention. FIG. The input data sampled by the N phase clock when N = 8 is shown. The horizontal axis shows the jitter superposition amount, and the vertical axis shows the power penalty. 2 shows an operation timing chart of the data reproduction circuit according to the first embodiment of the present invention. 1 is a flowchart of a data reproduction circuit according to Embodiment 1 of the present invention. FIG. 3 shows a schematic configuration diagram of a data reproduction circuit according to a second embodiment of the present invention. FIG. 4 shows a diagram representing isolated 1-bit sampling in input data. FIG. 5 is a schematic configuration diagram of a data reproduction circuit according to a third embodiment of the present invention. The figure showing the identification phase information signal when the first speed data is input or when the second speed data is input is shown. The figure showing sampling when the 1st speed data is inputted or the 2nd speed data is inputted is shown. The table in which the hold value regarding an identification phase change is stored is shown. 6 shows an operation timing chart of the data reproduction circuit according to the third embodiment of the present invention. The schematic block diagram of OLT which concerns on Embodiment 4 of this invention is shown. The schematic block diagram of the conventional data reproduction circuit is shown.

Embodiment 1 FIG.
FIG. 1 shows a schematic configuration diagram of a data reproduction circuit according to Embodiment 1 of the present invention. The data recovery circuit includes a reference clock generating means 3 for generating a reference clock, an N phase clock generating means 2 for generating N clocks (N phase clock) frequency-synchronized with the reference clock, and burst input data (a). Sampling means 1 for sampling with N phase clocks and outputting N sampling data sampled with each clock, and data sampled with an identification phase at a position closest to the center of the bit width of the input data among the sampling data And a phase selection logic circuit 4 that outputs and outputs reproduced data. Note that the N phase clock divides the 1-bit width of the input data into N parts. Further, the N phase clock generation means 2 may be expressed as a multi-phase clock generation means.

  The phase selection logic circuit 4 includes a change phase detection unit 4-1, an identification phase determination unit 4-2, a data selection unit 4-3, a convergence determination unit 4-4, a detection operation control unit 4-5, It comprises an identification phase holding means 4-6 and a timer means 4-7.

  The change phase detector 4-1 detects a change in phase from the rise and fall of the pulse of the sampling data output from the sampling unit 1. An example of the phase detection operation will be described with reference to FIG. FIG. 2 shows input data sampled with 8-phase clocks # 0 to # 7 when N = 8.

  In FIG. 2, the data sampled in the adjacent phases # 0, # 1, # 2,..., # 7 is “001111000”, and # 2 that changes from 0 to 1 changes from 1 to 0. # 6 is the falling change phase. Then, sampling is performed for a certain number of bits (identification phase determination interval), and the change phase is determined from the integration result by a method such as majority decision. In the conventional example of Non-Patent Document 2, this identification phase determination interval is 10 bits.

  The identification phase determination means 4-2 is an identification that is closest to the center of the bit width of the input data based on the change phase information signal (d) that is the phase information detected by the change phase detection means 4-1. Determine the phase. The closer the identification phase is to the center of the bit, the more accurately the data can be reproduced. In FIG. 2, when the rising change phase is # 2 and the falling change phase is # 6, for example, it is possible to determine # 4 as the identification phase by taking the interval. Alternatively, the identification phase may be determined using only either the rising change phase or the falling change phase. For example, based on the information of the rising change phase # 2, the position shifted by the two phases (phase # 4) may be determined as the identification phase. Note that the identification phase is not necessarily located closest to the center of the bit width of the input data, as long as the input data can be reproduced without error.

  The data selection unit 4-3 includes N sampling data output from the sampling unit 1 based on the identification phase information signal (h) that is information about the phase determined by the identification phase determination unit 4-2. Data sampled with the clock having the phase determined by the identification phase determining means 4-2 is selected. Then, the sampling data is retimed with the reference clock generated by the reference clock generating means 3 and outputted as reproduced data.

  The convergence determination unit 4-4 receives the identification phase information signal (h) from the identification phase determination unit 4-2, and determines whether the variation of the identification phase has converged within a predetermined range. Note that the range can be arbitrarily adjusted. Regarding the convergence determination, for example, during a predetermined time (the number of bits), it may be determined that convergence is achieved if the continuous identification phase determination result is within a range of fluctuation within plus or minus one phase. Alternatively, it may be determined that the signals have converged if the same identification phase continues for a predetermined time. And when it determines with having converged, the detection operation | movement control means 4-5, the identification phase holding | maintenance means 4-6 which mention the determination result containing the information about the identification phase (convergence phase) determined to have converged, and The timer means 4-7 is notified in the form of a convergence notification signal.

  The detection operation control means 4-5 controls the phase detection operation of the change phase detection means 4-1. When the detection operation control means 4-5 receives the start signal (b) from the PON control LSI which is a higher-level system side circuit (not shown in FIG. 1), the change phase detection means 4-1 is turned ON and the phase detection operation starts. . The phase detector 4-1 detects the change phase at every identification phase determination interval.

  When the detection operation control unit 4-5 receives the convergence notification signal from the convergence determination unit 4-4, the detection operation control unit 4-5 turns off the change phase detection unit 4-1, and stops the phase detection operation for a predetermined time. Outputs signal (f). Meanwhile, the change phase information (d) is not output from the change phase detection means 4-1 to the identification phase determination means 4-2. This time is defined as the identification phase holding time. Details of the method for determining the identification phase holding time will be described later.

  Upon receiving the convergence notification signal (e) from the convergence determination unit 4-4, the identification phase holding unit 4-6 receives the identification phase holding signal (g), which is information about the phase determined to be converged, as the identification phase determination unit 4 Output to -2. Upon receipt of the identification phase holding signal (g), the identification phase determining means 4-2 determines the phase (convergence phase) determined to converge during the identification phase holding time as the identification phase and outputs the identification phase information signal (h). . The selection means 4-3 that has received the identification phase information signal (h) selects data sampled with a clock having a phase determined to converge during the identification phase holding time. Note that the identification phase holding signal (g) does not necessarily include information on the convergence phase, and the identification phase determination means 4-2 can receive the identification phase holding signal (g) and hold the convergence phase. That's fine.

  When the convergence notifying signal (e) is notified from the convergence determining unit 4-4, the timer unit 4-7 receives the reference clock from the reference clock generating unit 3 and starts counting time. When a preset identification phase holding time elapses, a timer signal is output to the detection operation control means 4-5 and the identification phase holding means 4-6.

  Upon receiving the timer signal, the detection operation control means 4-5 stops outputting the detection stop signal (f), and the change phase detection means 4-1 restarts the change phase detection operation.

  The identification phase holding means 4-6 that has received the timer signal stops outputting the identification phase holding signal (g), and the identification phase determination means 4-2 is input from the change phase detection means 4-1 that has restarted the phase detection operation. The identification phase is determined based on the change phase information (d). The timer means 4-7 can be easily realized by a counter circuit for counting the number of clocks, for example.

  When the input of the burst input data is completed, a data end signal (c) (not shown in FIG. 1) is output from the PON control LSI to the phase selection logic circuit 4, and the determination operation of the identification phase is stopped. Then, almost simultaneously with the next burst input data being input, the start signal (b) is output from the PON control LSI to the detection operation control means 4-5, and the phase detection / identification phase determination operation is performed again.

  The timing at which the start signal (b) is output from the PON control LSI may be any timing before or after the input of the burst input data.

  Next, the operation of the present invention will be described with reference to FIGS. FIG. 4 shows an operation timing chart of the present invention, and (a) to (i) in FIG. 4 correspond to those in FIG. FIG. 5 shows an operation flowchart of the present invention. In FIG. 4, the following description will be made assuming that there is ideally no circuit delay in order to facilitate understanding of the circuit operation. Further, the Hi and Low logic levels of each signal are for convenience of explanation and do not limit the circuit operation.

  The N phase clock generation means 2 generates an N phase clock synchronized with the reference clock, and the sampling means 3 samples the burst input data (a) with the N phase clock.

  When a start signal (b) indicating the input of burst input data (a) is input from the PON control LSI to the detection operation control means 4-5 at time t1, a loop is started (step S1). In response to the input of the start signal (b), the detection operation control means 4-5 turns on the change phase detection means 4-1, and the change phase detection means 4-1 is a change phase information signal (a signal including change phase information). d) is output (step S2).

  The identification phase determination means 4-2 determines the identification phase based on the change phase information (d), and outputs an identification phase information signal (h) that is a signal including information on the determined identification phase (step S3). . Then, the identification phase is determined again every identification phase determination interval. For example, if the identification phase determination interval is a time corresponding to 10 bits, phase # 1 is determined by looking at the first 10 bits starting from time t1 in FIG. Determine 0. Next, as in # 2, phase determination is repeated until it is determined that the variation of the identification phase has converged within a certain range.

  The data selection unit 4-3 selects data sampled based on the phase based on the identification phase information signal (h) notified to the identification phase determination unit 4-2, and outputs reproduction data (step S4).

  When it is determined that the phase fluctuation has converged within a certain range at time t2 (step S5-Yes), the convergence determination unit 4-4, the detection operation control unit 4-5, the identification phase holding unit 4-6, and A convergence notification signal (e), which is a signal including information on the convergence phase, is output to the timer means 4-7.

  The timer means 4-7 receives the convergence notification signal (e) and starts counting time (step S6).

  The detection operation control means 4-5 receives the convergence notification signal (e) and outputs a detection stop signal (f) to the phase detection means 4-1, and the change phase detection means 4-1 stops detecting the change phase. (Step S7).

  The identification phase holding means 4-6 receives the convergence notification signal (e), and outputs an identification phase holding signal (g), which is a signal including information for holding the convergence phase, to the identification phase determination means 4-2. The phase determination unit 4-2 outputs identification phase information (h) based on the convergence phase (step S8). In the example of FIG. 4 (h), since the phase determined to have converged is # 2, phase # 2 is held as the identification phase for the subsequent identification phase holding time (t4−t2).

  When it is determined that the phase fluctuation has not converged (step S5-No), the change phase detection / identification phase determination operation is repeatedly performed.

  When the identification phase holding time has elapsed at time t4 (step S9-Yes), the timer unit 4-7 outputs a timer signal to the detection operation control unit 4-5 and the identification phase holding unit 4-6 to detect the detection stop signal. (f) and the identification phase holding signal (g) are Low (step S10). When the data end signal (c) is not input, that is, when the burst signal is continuously input (step S11-No), the change phase information signal (d) becomes High again, and the phase detection operation is resumed. .

  When such an operation is repeated and the data end signal (c) indicating the end of the burst input data (a) is input at time t8 (step S11-Yes), the loop processing ends and the phase selection logic circuit 4 operates. Exit.

  The operation flow chart shown in FIG. 5 represents the processing of the data recovery circuit for one burst input data. When the second and third burst signals are input, the processing in FIG. 4 is performed again. That is, when a burst signal is input at time t9 in FIG. 4, this corresponds to step S1 in the flow chart of FIG. 5, and thereafter, steps S2 and S3 and the processing described above are performed again.

  In the operation flow diagram of FIG. 5, the loop is ended when the data end signal (c) is input in step S11. However, even during each process such as change phase detection and identification phase determination, If the data end signal (c) is input, the processing operation is forcibly ended.

  In this embodiment, the start signal (b) and the data end signal (c) from the PON control LSI are output to the detection operation control means 4-5. 1 may be used to turn the phase detection operation ON / OFF.

  In addition, when the identification phase holding time has elapsed, the timer means 4-7 outputs a timer signal to the change phase detection means 4-1 and the identification phase holding means 4-6, and the change phase detection operation is resumed. The operation control means 4-5, the identification phase holding means 4-6, the change phase detection means 4-1, and the identification phase determination means 4-2 may be provided with a timer function.

  That is, for example, if the detection operation control means 4-5 has a timer function, the detection operation control means 4-5 receives the convergence notification signal (e) from the convergence determination means 4-4 and counts the time. Start. When the identification phase holding time elapses, the detection operation control means 4-5 stops outputting the detection stop signal (f) to the change phase detection means 4-1, and the change phase detection means 4-1 performs the phase detection operation. To resume. Also, the timer signal is output to the identification phase holding means 4-6, and the identification phase holding means 4-6 stops outputting the identification phase holding signal (g), and the identification phase holding operation is ended.

  An example of a method for determining the identification phase holding time will be described. During the identification phase holding time, the sampling result is always selected and output at the held phase, so that the signal phase fluctuation due to the jitter superimposed on the burst input data is accumulated. As time passes, reception sensitivity deterioration (hereinafter referred to as power penalty) occurs due to a timing error with the identification phase held. Therefore, the identification phase holding time must be determined so that the power penalty is within the range allowed by the system.

  FIG. 3 is a graph showing an example of the jitter superposition amount on the horizontal axis and an example of the power penalty on the vertical axis. The unit of jitter superposition amount is UI (Unit Interval), and the unit of power penalty is dB (Decibel). These relational expressions are expressed by the following expressions (1) and (2). B in Formula (1) is represented by Formula (2).

In Expression (1), Q is an index representing an input error rate BER (Bit Error Rate), and here, as an example, it is assumed that the Q value is BER = 10 ⁻³ . B represents a bit rate (bps), and τj represents an RMS (Root Mean Square) of jitter amplitude fluctuation. The jitter superimposition amount on the horizontal axis in FIG. 3 corresponds to B · τj in equation (2).

  Further, the relational expression between the jitter superposition amount and the identification phase holding time is expressed by the following expression (3).

  In Expression (3), Aj is the jitter amplitude (RMS), fj is the jitter frequency (MHz), and the jitter model is, for example, a stressed eye generation condition of a GE (Gigabit Ethernet (registered trademark))-PON system or the like. It can be a commonly used Sinusoidal model.

  The power penalty allowed for the system is 1 dB, the power penalty at the moment when the discrimination phase is held is 0 dB, that is, the discrimination phase holding time is derived when the discrimination phase is at the ideal center of the data bit. In the case of this condition, the amount of jitter superimposition needs to be 0.18 UI or less from FIG.

  From equation (3), when the jitter amplitude is 0.3 UI and the jitter frequency is 4 MHz, the time for the jitter superposition amount to be 0.18 UI or less is approximately 90 us (microseconds) or less. Therefore, under the above conditions, if the identification phase holding time is about 90 us, clock extraction and data recovery are performed at a high speed, and the longest time-varying phase detection means 4-1 allowed by the system is turned off to reduce power consumption. It is possible to reduce the maximum.

  Note that the above calculation example is an example, and the specific identification phase holding time may be obtained according to the reception sensitivity and power penalty conditions required by the system. When a system that satisfies the jitter tolerance mask that defines the jitter tolerance is required, the identification phase holding time may be determined based on the required specifications.

  Further, when the system is required to satisfy both the power penalty and the jitter tolerance mask, the longest time among the times satisfying both of these may be determined as the identification phase holding time.

  According to the above configuration, when it is determined that the phase fluctuation has converged within a certain range, the variation phase detection operation can be stopped by turning off the variation phase detection means 4-1 for a certain period of time. Power consumption can be reduced. In addition, since the identification phase is held while the change phase detection operation is stopped, the clock extraction / data reproduction from the input data is performed without being stopped. That is, it is possible to perform clock extraction and data recovery at high speed from the input burst signal and reduce power consumption.

Embodiment 2. FIG.
FIG. 6 is a schematic configuration diagram of a data reproduction circuit according to the second embodiment. Parts corresponding to those of the first embodiment are denoted by the same reference numerals as those in FIG. The second embodiment has a configuration in which pulse width detecting means 4-8 is added as compared with the first embodiment.

  The pulse width detection unit 4-8 includes, for example, a counter circuit and a comparator circuit, and detects a 1-bit pulse width of input data based on the change phase information (d) received from the change phase detection unit 4-1. The detection result is output as a pulse width information signal (k).

  The detection operation of the 1-bit pulse width of the input data will be described with reference to FIG. FIG. 7A shows sampling when the pulse width is narrow, that is, when the pulse width of 1-bit data “1” is narrow. FIG. 7B shows sampling when the pulse width is wide, that is, when the pulse width of 1-bit data “1” is wide (when the width of data “0” is narrow). Note that the narrow pulse width means that the pulse width is narrower than a normal pulse width without pulse distortion. A wide pulse width means that the pulse width is wider than a normal pulse width without pulse distortion. In FIG. 7, sampling is performed with an 8-phase clock with N = 8, but the present invention is not limited to this.

  If the width of the 1-bit pulse “1” of the input data is narrow, the falling change phase is detected within one clock cycle (phase difference is within one clock time) after the rising change phase is detected. It becomes a landmark. In the example of FIG. 7A, the falling change phase is detected in the phase # 5 within one clock cycle after the rising phase # 3 is detected.

  When the width of 1-bit pulse “0” of the input data is narrow, the rising change phase is detected within one clock cycle (phase difference is within one clock time) after the falling change phase is detected. It becomes a landmark. In the example of FIG. 7B, the rising change phase is detected in phase # 6 within one clock cycle after the falling change phase # 4 is detected.

  The pulse width detection unit 4-8 determines the pulse width from the rising / falling change phase for the detected 1-bit data. For example, in FIG. 7, since the rising change phase is # 3 and the falling change phase is # 5, the pulse width is determined to be a length corresponding to the clocks for these two phases. Then, a pulse width information signal (k), which is information about the pulse width determined in this way, is output to the identification phase determining means 4-2.

  The identification phase determination unit 4-2 determines the identification phase based on the received pulse width information signal (k). For example, as shown in FIG. 7A, when the pulse width detection unit 4-8 outputs information indicating that the pulse width is narrow to the identification phase determination unit 4-2, a signal having a wide pulse width among the input data is “11”. "Determining and determining the identification phase. On the other hand, as shown in FIG. 7B, when the pulse width detection unit 4-8 outputs information indicating that the pulse width is wide to the identification phase determination unit 4-2, a signal having a wide pulse width among the input data is displayed. Determine 1 "and determine the identification phase.

  Note that operations such as convergence determination and identification phase holding after determination of the identification phase are the same as those in the first embodiment.

  According to the above configuration, even when data with a distorted pulse width is input, the accuracy of detecting the distortion and selecting the phase closest to the center of the bit width can be improved. Then, by improving the accuracy of selecting such an identification phase, it is possible to shorten the time until the identification phase fluctuation converges compared to the first embodiment. The power consumption can be increased, and power consumption can be further reduced.

Embodiment 3 FIG.
The data recovery circuit according to the third embodiment includes data having the same reference frequency component as the clock speed generated by the N-phase clock generation means 2 (hereinafter referred to as first speed data) and a reference different from the clock speed. Regardless of whether data having frequency components (hereinafter referred to as second speed data) is input, clock input and data recovery are performed at high speed from each input data, and the change phase detection operation is stopped for a certain period of time. Thus, it is possible to operate at high speed while reducing power consumption.

  FIG. 8 is a schematic configuration diagram of a data reproduction circuit according to the third embodiment. Parts corresponding to those of the first embodiment are denoted by the same reference numerals as those in FIG. Compared with the first embodiment, the third embodiment does not have the identification phase holding unit 4-6, and the selection unit 4-9, the first identification phase holding unit 4-10, and the second identification phase holding unit 4-11. The frequency adjusting unit 4-12 and the speed converting unit 4-13 are added. Note that the timer means 4-7 is omitted from FIG.

  The selection means 4-9 receives a speed information signal (l) about the speed of the input data from the ONU, which is input from a PON control LSI (not shown in FIG. 8), and based on the speed information, the first identification phase A holding means selection signal (m) for selecting either the holding means 4-10 or the second identification phase holding means 4-11 is output. When the first speed data is input, the first identification phase holding means 4-10 is selected, and when the second speed data is input, the second identification phase holding means 4-11 is selected.

  The first identification phase holding means 4-10 is turned on when the holding means selection signal (m) is input from the selection means 4-9, and the convergence notification signal (e) is input from the convergence determination means 4-4. Then, the first identification phase holding signal (o) is output to the identification phase determining means 4-2.

  Similarly to the first identification phase holding means 4-10, the second identification phase holding means 4-11 is turned ON when the holding means selection signal (m) is input from the selection means 4-9, and the convergence determination means. When the convergence notification signal (e) is input from 4-4, the second identification phase holding signal (p) is output to the identification phase determining means 4-2.

  The identification phase information signal (h) when the first speed data or the second speed data is input will be described with reference to FIG. 9A shows an identification phase information signal (h) when the first velocity data is input, that is, when the first identification phase holding signal (o) is input to the identification phase determination means 4-2. ). FIG. 9B shows an identification phase information signal (h) when the second velocity data is input, that is, when the second identification phase holding signal (p) is input to the identification phase determination means 4-2. ).

  When the first velocity data is input, the same phase is always selected during the identification phase holding time as in the first embodiment. For example, as shown in (a) of FIG. 9, when the initial value of the identification phase to be held is the phase #N, the phase #N is always selected during the identification phase holding time.

  When the second speed data is input, it is necessary to change the identification phase according to the speed difference between the first speed data and the second speed data. The reason for the change will be described using FIG. 10 as an example. In FIG. 10, the numbers surrounded by circles represent the identification phases. For example, when the first velocity data in the upper part of FIG. 10 is input, it is assumed that the identification phase does not change as # 2, # 2, # 2, # 2,. However, when the second speed data in the lower part of FIG. 10 is input, the second speed data is sampled with a clock synchronized with the first speed data, so that a timing shift occurs and the identification phase is changed to the first. If # 2, # 2, # 2, # 2,... Are determined in the same manner as when the input data is input, a bit error occurs and the data cannot be accurately reproduced. Therefore, when the second speed data is input, it is necessary to change the identification phase when the first speed data is input. In the example of FIG. 10, the identification phase changes as # 2, # 2, # 3, # 3,.

  When the m bits in the first speed data and the n bits in the second speed data are the same, that is, the first speed data and the second speed data have the relationship of the following equation (4), (b ), The held identification phase has a period corresponding to n bits in the second speed data.

  For example, in FIG. 9B, when the initial value of the identification phase to be held is the phase #N, as the time elapses, # N-1, # N-2,. When the time (cycle) corresponding to n bits in the second speed data comes, phase # 0 is set as the identification phase again. These operations are repeated during the identification phase holding time.

  In FIG. 9, the identification phase holding time when the first velocity data is input and the identification phase holding time when the second velocity data is input are shown as the same time, but they are not necessarily the same. There is no need, for example, the bit rate of the second speed data is substituted into B of the above equation (2), and the identification phase holding time is determined from the relationship of the above equations (1), (2), and (3) as described above. You may decide. In this case, the time for stopping the change phase detection operation differs between when the first speed data is input and when the second speed data is input.

  Note that the change in the identification phase when the second velocity data is input is not limited to (b) in FIG. 9, and it is sufficient that the phase change is performed according to the gradient A in the figure.

  The second identification phase holding means 4-11 has the identification phase change corresponding to the speed difference in the form of a table as a holding value in advance, and information about the phase change is stored in the second identification phase holding signal. (g) is output to the identification phase determining means 4-2.

  The table is expressed, for example, in the form as shown in FIG. 11, and information on the convergence phase at the elapsed time is stored based on the convergence phase to be held notified by the convergence notification signal (e) from the convergence determination means 4-4. Has been. In the case 1 as an example, the convergence notification signal (e) notifies that # 0 is the convergence phase. Therefore, the convergence phase at t = 0 is # 0. Then, after a certain time has elapsed (t = ta), phase # 1 is held, and phase #N is held at time (period) T corresponding to n bits in the second speed data. In case 2, the convergence phase # 1 is notified, the holding phase at t = 0 is # 1, the holding phase at t = t1 is # 2, and the phase # 0 is held at t = T. As described above, the holding phase with respect to the passage of time is stored in the table based on the notified holding phase, and the phase is held based on the stored information.

  The frequency adjusting unit 4-12 generates the second speed data sampled data output from the data selecting unit 4-3 according to the speed difference between the first speed data and the second speed data. Frequency adjustment is performed by deleting redundant bits. For example, it can be realized by thinning out bits using a buffer.

  For example, if the first speed data is 10.3125 GHz clock and the second speed data 10 Gbps data (speed component of 10 GHz frequency clock) is sampled and then frequency adjustment is performed, the ratio of 10.3125 and 10 is Since it is 32 to 33, it is possible to thin out 1 bit from 33 bit data sampled by 10.3125 GHz clock and output it as 32 bit data.

  The speed converter 4-13 converts the reference clock speed output from the reference clock generator 3 into the reference clock speed of the second speed data. The speed conversion unit 4-13 can be realized by using, for example, a PLL (Phase Locked Loop) circuit.

  The operation of the invention according to Embodiment 3 will be described with reference to FIGS. FIG. 12 is an operation timing chart of the invention according to the third embodiment. When the first speed data is input, the PON control LSI outputs a start signal (b) to the change phase detection means 4-1, and the change phase is detected at every discrimination phase determination interval. Further, the speed information signal (l) is output to the selection means 4-9, the selection means 4-9 recognizes that the first speed data has been inputted, and the holding means selection signal (m) is first identified. Output to phase holding means 4-10.

  In FIG. 12, the holding means selection signal (m) is shown to be notified at the same timing (t = t1) as the data input. However, the present invention is not limited to this, and the first identification phase is not limited to this. Time (t) when the holding unit 4-10 or the second identification phase holding unit 4-11 acquires the convergence notification signal (e) from the convergence determination unit 4-4 and issues the first identification phase holding signal (o) = t2) or the time (t = t10) when the second identification phase holding signal (p) is issued.

  When the phase change converges, the convergence determination unit 4-4 outputs a convergence notification signal (e) to the detection operation control unit 4-5 and the first identification phase holding unit 4-10. The detection operation control means 4-5 outputs the detection stop signal (f) to the change phase detection means 4-1, and turns off detection of the change phase, and the first identification phase holding means 4-10 outputs the first identification phase. The holding signal (o) is output to the identification phase determining means 4-2 to hold the identification phase.

  The change phase detection means 4-2 restarts the change phase detection operation again when the identification phase holding time elapses, and the data end signal (c) indicating the end of the first speed data is subjected to these processes. Repeat until 4 is output. The data selection means 4-3 retimes the data sampled at the identification phase based on the identification phase information signal (h) with the reference clock and outputs it as reproduced data (i).

  Next, when the second speed data is input, the start signal (b) and the speed information signal (l) are input in the same manner as described above, and the change phase detection operation is performed. The selection means 4-9 to which the speed information signal (l) is input recognizes that the second speed data has been input, and sends the holding means selection signal (m) to the second identification phase holding means 4-10. Output.

  When the phase change converges, the convergence determination unit 4-4 outputs a convergence notification signal (e) to the detection operation control unit 4-5 and the second identification phase holding unit 4-11. The detection operation control means 4-5 outputs a detection stop signal (f) to the change phase detection means 4-1, and turns off detection of the change phase, and the second identification phase holding means 4-11 stores the above table information. The included second identification phase holding signal (p) is output to the identification phase determining means 4-2. The identification phase determination unit 4-2 determines the identification phase based on the table information included in the second identification phase holding signal (p).

  The change phase detection means 4-2 restarts the change phase detection operation again when the identification phase holding time elapses, and the data end signal (c) indicating the end of the second speed data is subjected to these processes. Repeat until 4 is output.

  The data selection unit 4-3 outputs data sampled at the identification phase based on the identification phase information signal (h). The output sampling data is frequency-adjusted by the frequency adjusting means 4-12, retimed with the clock subjected to speed conversion by the speed converting means 4-13, and outputted as reproduction data (n).

  In this case, the reproduction data (i) output from the data selection means 4-3 is useless data, but both the reproduction data (i) and the reproduction data (n) are output to the PON control LSI, Only valid data may be acquired by the PON control LSI. Alternatively, a signal related to speed information is sent from the PON control LSI to the data selecting means 4-3 at the same timing as the data input, and the data selecting means 4-3 sends the frequency adjusting means 4-12 to the frequency adjusting means 4-12 based on the notified speed information. Only the sampling data may be output and the reproduction data (i) may not be output.

  According to the above configuration, even when either the first speed data or the second speed data having different speeds is input, the clock is extracted from each input data and the data is reproduced at a high speed, and the change phase is detected. By stopping the operation for a fixed time, it is possible to operate at high speed while reducing power consumption.

  Further, the above-described pulse width detection unit 4-8 may be applied to the data reproduction circuit according to the present embodiment. By applying the pulse width detection means 4-8, even when either the first speed data or the second speed data having different speeds and distorted pulse widths are input, the distortion is detected, The accuracy of selecting a phase close to the center of the bit width can be improved. Then, by improving the accuracy of selecting such an identification phase, it is possible to shorten the time until the identification phase fluctuation converges compared to the first embodiment. The power consumption can be increased, and power consumption can be further reduced.

Embodiment 4 FIG.
FIG. 13 is a schematic diagram of an OLT according to the fourth embodiment. The OLT 7 is connected to a plurality of ONUs 5 by an optical fiber 6 to form a PON system. The OLT 7 is a WDM (Wavelength Division Multiplexing) filter 7-1 that performs multiplexing / demultiplexing of transmission / reception light, an optical receiver 7-2 that converts an optical signal from the ONU 5 into an electrical signal, and an electrical signal that is transmitted to the ONU 5 It has an optical transmitter 7-4 that converts it into a signal, a data recovery circuit 7-4 that performs clock extraction and data recovery from input data, and a PON control LSI 7-5 that performs processing for data transmission and reception. Here, the data reproduction circuit 7-4 is a data reproduction circuit according to any of Embodiments 1-3.

  The operation of the OLT 7 that has received the data transmitted from the ONU 5 will be described. The OLT 7 that has received the burst input data from the ONU 5 converts the optical signal into an electrical signal by the optical receiver 7-2, and outputs it to the data recovery circuit 7-4.

  The data reproduction circuit 7-4 extracts the clock from the received data at high speed and reproduces the data. Thereby, timing adjustment is performed on data from the ONU 5, and the ONU 5 and the OLT 7 can be synchronized.

  The PON control LSI 7-5 processes the data whose timing is adjusted by the data reproduction circuit 7-4. When data is transmitted to the ONU 5, the electrical signal sent from the PON control LSI 7-5 is converted into an optical signal by the optical transmitter 7-3 and transmitted to the ONU 5.

  According to the above configuration, the OLT 7 can reduce power consumption while performing clock extraction and data recovery at high speed from burst data output from the ONU 5.

DESCRIPTION OF SYMBOLS 1 Sampling means 2 N phase clock generation means 3 Reference clock generation means 4 Phase selection logic circuit 4-1 Change phase detection means 4-2 Identification phase determination means 4-3 Data selection means 4-4 Convergence determination means 4-5 Detection operation Control means 4-6 Identification phase holding means 4-7 Timer means 4-8 Pulse width detection means 4-9 Selection means 4-10 First identification phase holding means 4-11 Second identification phase holding means 4-12 Frequency Adjustment means 4-13 Speed conversion means 5 ONU
6 Optical fiber 7 OLT
7-1 WDM filter 7-2 Optical receiver 7-3 Optical transmitter 7-4 Data recovery circuit 7-5 PON control LSI

Claims (8)

A multi-phase clock generation means for generating a plurality of clocks frequency-synchronized with a reference clock; a sampling means for sampling input data using the plurality of clocks and outputting a plurality of sampling data;
Change phase detection means for detecting a change phase representing a change in rising or falling of the pulse of the sampling data; and
An identification phase determining means for determining an identification phase for sampling input data based on information on the changed phase detected by the changed phase detecting means;
Data selection means for selecting data sampled with the clock of the identification phase from the plurality of sampling data and outputting reproduction data;
Convergence determining means for determining whether the variation of the identification phase has converged within a predetermined range, and outputting a convergence notification signal indicating convergence when the convergence has converged,
Detection operation control means for stopping the change phase detection operation of the change phase detection means for a predetermined time based on the convergence notification signal;
Identification phase holding means for holding a convergence phase that is a phase when the identification phase determination means converges for the predetermined time based on the convergence notification signal;
A data reproduction characterized by selecting data sampled at the convergence phase from the plurality of sampling data and outputting reproduction data during the predetermined time during which the change phase detection operation is stopped circuit. Timer means for outputting a timer signal when the predetermined time has elapsed;
The detection operation control means receives the timer signal and causes the change phase detection means to restart the change phase detection operation,
2. The data reproduction circuit according to claim 1, wherein the identification phase holding means receives the timer signal and causes the identification phase determination means to stop holding the convergence phase. A multi-phase clock generation means for generating a plurality of clocks frequency-synchronized with a reference clock; a sampling means for sampling input data using the plurality of clocks and outputting a plurality of sampling data;
Change phase detection means for detecting a change phase representing a change in rising or falling of the pulse of the sampling data; and
An identification phase determining means for determining an identification phase for sampling input data based on information on the changed phase detected by the changed phase detecting means;
Data selection means for selecting data sampled with the clock of the identification phase from the plurality of sampling data and outputting reproduction data;
Convergence determining means for determining whether the variation of the identification phase has converged within a predetermined range, and outputting a convergence notification signal indicating convergence when the convergence has converged,
Detection operation control means for obtaining the convergence notification signal and stopping the change phase detection operation of the change phase detection means for a predetermined time;
When the first speed data having the same speed as the reference clock speed is input, the first phase determined by the convergence determination means is held by the identification phase determination means based on the convergence notification signal. 1 identification phase holding means;
When the second speed data having a speed different from the reference clock speed is input, the speed of the first speed data and the second speed data is input to the identification phase determination means based on the convergence notification signal. Second identification phase holding means for holding a second phase that changes according to the difference,
During the predetermined time during which the change phase detection operation is stopped, when the first velocity data is input among the plurality of sampling data, the second phase is changed to the second phase. When the speed data is input, the sampled data is selected and the reproduction data is output in the second phase. Timer means for outputting a timer signal when the predetermined time has elapsed;
The detection operation control means acquires the timer signal and causes the change phase detection means to restart the change phase detection operation,
The first identification phase holding means acquires the timer signal and causes the identification phase determination means to stop holding the first phase;
4. The data reproduction circuit according to claim 3, wherein the second identification phase holding means acquires the timer signal and causes the identification phase determination means to stop holding the second phase. When the second speed data is input,
Frequency adjusting means for adjusting the frequency of the sampling data output from the data selecting means so as to be the frequency of the first speed data;
Speed conversion means for converting the speed of the reference clock into the speed of the second speed data, and retiming the frequency-adjusted sampling data with the converted clock and outputting it as reproduction data. The data reproduction circuit according to claim 3 or 4. Pulse width detection means for detecting the pulse width of the input data by detecting the 1-bit rising phase and falling phase of the input data based on the change phase information and outputting a signal about the pulse width information is provided. And
6. The data reproduction circuit according to claim 1, wherein the identification phase determination unit determines the identification phase based on the pulse width information. An optical receiver for photoelectrically converting transmission data from a plurality of subscriber side optical transceivers;
The data recovery circuit according to any one of claims 1 to 6, wherein a clock is extracted from the converted data and data is recovered.
A station-side optical transceiver having a PON control LSI that receives and processes the reproduction data output from the data reproduction circuit. A sampling step for sampling input data with a plurality of clocks synchronized with a reference clock; and
An identification phase determining step for detecting a change phase representing a change in rising or falling of a pulse of the sampled data and determining an identification phase for sampling input data based on the information on the change phase;
A convergence determination step for determining whether the variation of the identification phase has converged within a predetermined range;
A change phase detection operation stop step for stopping the change phase detection operation for a predetermined time when the variation of the identification phase converges within a predetermined range;
An identification phase maintaining step of selecting sampling data at the convergence phase and outputting reproduction data while the change phase detection operation is stopped.

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