JP3355261B2 - Bit synchronization circuit and bit synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization circuit and a bit synchronization method corresponding to burst transmission for reproducing a signal in synchronization with the phase of a burst signal, and more particularly to an optical transmission system of a point-to-multipoint system. The present invention relates to a bit synchronization circuit and a bit synchronization method which are preferably applied to a case where a burst signal from a multipoint side is received on a point side.

[0002]

2. Description of the Related Art As a prior art relating to a bit synchronization system for a burst transmission signal, a point-to-multipoint communication system in which one communication device and a plurality of communication devices are connected via an optical distribution device (star coupler). 2. Description of the Related Art There is known a bit synchronization system in a system optical transmission system.

FIG. 9 is a block diagram showing a configuration example of such a point-to-multipoint optical transmission system according to the prior art, and FIG. 10 shows a case where one communication device receives information cells from a plurality of communication devices. FIG. 11 is a diagram illustrating a situation. Hereinafter, a bit synchronization method according to the related art will be described with reference to FIGS. In FIG. 9, 100,
101-1 and 101-2 are communication devices, and 102 is a star coupler.

[0004] The illustrated optical transmission system has one communication device 1.
00 and a plurality of communication devices 101-1 to 101-2 are connected via a star coupler 102 to form a point-to-multipoint optical transmission system. In the optical transmission system thus configured, the communication device 101
When transmitting an information cell from one of -1 to 101-2 to the communication device 100, the communication device 100 and each communication device 101-
Each communication device 101
The information cells transmitted from -1 to 101-2 to the communication device 100 have different optical levels and different phase differences from the device internal system clock of the communication device 100, respectively.
The data is transmitted in a burst and arrives at the communication device 100.

FIG. 10 shows an optical level of a burst signal when the communication device 100 as described above receives information cells from the communication devices 101-1 to 101-2. As can be seen from this figure, the light levels of the burst signals of the information cells from the communication devices 101-1 to 101-2 arriving at the communication device 100 are largely different from each other. Although not shown, these burst signals are respectively
The phase difference between the communication device 100 and the device internal system clock is different.

The communication device 100 performs bit synchronization after converting the arriving burst signal into an electric signal by an optical / electrical conversion device. For the bit synchronization in the communication device 100, a bit synchronization byte composed of an alternating signal of 1/0 is provided near the head of the burst signal. But,
Since only a limited number of bytes can be provided for a bit synchronization byte in consideration of transmission efficiency, the communication device 100 needs to perform bit synchronization within a section of a few bytes of the bit synchronization byte.

As a prior art relating to a bit synchronization circuit for a burst transmission signal as described above, for example, "P
A technique described in "Bit Synchronization Circuit Corresponding to Burst Signal in DS Optical Subscriber System" (Shingaku Zendai (Autumn) B-830, 1993) is known.

In this prior art, a received burst signal is polyphased, and bit synchronization is performed by a DPLL circuit that retiming is performed at a phase position shifted by a half phase from a change point of the received burst signal. In this prior art, a transmission speed of about 60 Mbps is assumed.

[0009]

In the system as shown in FIG. 9 described above, high-speed transmission (155.52 Mb
(approximately ps), the fluctuation of the duty ratio of the input data becomes remarkable due to a delay in follow-up of automatic threshold control in the optical / electrical conversion of the burst signal received by the communication device 100.

FIG. 11 is a diagram showing the relationship between the time change of the threshold value and the identified signal for explaining this.

FIG. 11A shows a received optical signal, FIG. 11B shows a threshold signal for identifying the optical signal, and FIG. 11C shows a signal identified by the threshold. From this figure, it can be seen that when the temporal change of the threshold value is remarkable, the duty ratio of the received signal changes.

In general, when trying to perform high-speed transmission, the ideal position of retiming when synchronizing is further limited due to the influence of jitter, electrical distortion, and the like. For this reason, when the above-described synchronization method using the PLL circuit is applied to the system as shown in FIG. 9, the phase shifted by a fixed phase from the change point of the reception data is set as the ideal position of the retiming as in the related art. The method adopted has a problem that the resistance to the duty fluctuation as described above is small.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a bit synchronizing circuit and a bit synchronizing method having high tolerance to duty fluctuation.

[0014]

According to the present invention, it is an object of the present invention to provide a data sampling unit which samples a received burst input signal and converts it into an n-sequence (where n is an integer of 2 or more) signal. And a selection output unit that selects and outputs a signal synchronized with the received burst input signal from the n-sequence signals sampled by the data sampling unit,
Furthermore, n sampled in the data sample section
A change point detection unit that detects a rising and falling change point of each of the series signals, a holding unit that holds a detection result detected by the change point detection unit at a certain timing, the change point detection unit and the holding A clock determination unit that determines a signal to be selected by the selection output unit based on one or both of the output results from the unit, and a determination result holding unit that holds the output result of the clock determination unit only at a certain timing. It is achieved by comprising.

The data sampling section includes a sampling means for generating a multi-phase clock composed of a plurality of n-sequences having mutually different phases, sampling the received burst input signal using the multi-phase clock, and outputting the signal as an n-sequence signal. Can be.

The change point detecting section detects the rising and falling change points of the received burst signal, and determines the phase position of the changed point and the number of the changed points at the same time period as the received burst signal. Can be included.

The holding unit may include holding processing means for holding the change point detection result of the change point detection unit for one cycle of the same time cycle as the data cycle of the received burst signal.

The clock determination unit determines, as determination logic, based on the phase position of the change point of the received burst signal transmitted from one or both of the change point detection unit and the holding unit.
A determination processing means for determining a reception burst signal sampled at an intermediate phase position between two rising and falling points of the reception burst signal as a signal to be selected by the selection output unit can be included.

As the decision logic in the clock decision section,
Further, the phase position of the rising or falling transition point of the reception burst signal and the number of transition points within the same time period as the data period of the reception burst signal output from the transition point detection unit, and the data of the reception burst signal in the holding unit Judgment processing means for judging a signal to be selected by the selection output unit based on one or both of the phase position and the number of change points from the change point detection unit held for one cycle of the same time cycle as the cycle Can be included. The specific logic of this determination processing means is as follows.

The number of rising or falling transition points of the received burst signal within the same time period as the data period of the received burst signal output from the transition point detection section is 1, and the holding section has the same data cycle as the received burst signal. When the number of change points from the change point detection unit held for one cycle of the same time period is 0, the phase position shifted by a certain fixed timing with respect to the phase position of the change point output from the change point detection unit Is determined as a signal to be selected by the selection output unit.

The number of rising or falling transition points of the received burst signal within the same time period as the data cycle of the received burst signal output from the transition point detection section is 1, and the holding section has the data cycle of the received burst signal. When the number of change points from the change point detection unit held for one period of the same time period is 1, the phase position of the change point output from the change point detection unit and the change position output from the storage unit The received burst signal sampled at an intermediate phase position with respect to the phase position of the point is determined as a signal to be selected by the selection output unit.

The number of rising or falling transition points of the received burst signal within the same time period as the data period of the received burst signal output from the transition point detection unit is 1, and the data period of the received burst signal is determined by the holding unit. When the number of change points from the change point detection unit held for one period of the same time period is 2, the phase position of the change point output from the change point detection unit and the 2 A reception burst signal sampled at an intermediate phase position with respect to the phase position of the trailing edge of the three transition points is determined as a signal to be selected by the selection output unit.

When the number of rising or falling transition points of the received burst signal within the same time period as the data cycle of the received burst signal output from the transition point detection section is 2, the signal is output from the transition point detection section. A reception burst signal sampled at an intermediate phase position between the two transition points is determined as a signal to be selected by the selection output unit.

The determination result holding unit is configured to, when a rising or falling transition point of the received burst signal is not detected within the same time period as the data period of the received burst signal, determine the determination result of the clock determining unit that has been determined so far. May be provided only for a certain timing.

Further, the information from the judgment result holding unit can be averaged within a certain period of time and used as selection information of the selection output unit.

[0026]

According to the present invention, a rising and falling transition point is detected by sampling a reception burst signal, and the result is delayed to determine a signal synchronized with the reception burst signal together with transition point information from the past. Therefore, it is possible to determine the synchronization of the received burst signal in consideration of the duty fluctuation.

As means for sampling the received burst signal, a multi-phase clock composed of a plurality of n-sequences having different phases from each other is generated. Since the signal is output as a signal, the operation at high speed can be adapted.

Further, the present invention detects not only the position of a change point but also the number of change points in one cycle as the change point detection information, and delays the information by one cycle to obtain the delayed information and The information before the delay, that is, the position and the number of the change points in the past two cycles can be used as the information for determining the signal synchronized with the received burst signal.

As a logic for judging a signal synchronized with the received burst signal, a point shifted by a fixed value from a rising change point of the signal is not used as a retiming position as in the case of the prior art, but a rising change is performed. Since the midpoint between the point and the falling transition point is set as the retiming position, the retiming can always be performed at the ideal retiming position even when the above-described duty fluctuation occurs. .

Further, as a logic for determining a signal synchronized with the received burst signal in consideration of the number of change points, it is possible to use a logic classified according to the number of change points in the past two cycles.

FIG. 8 is a diagram showing an example of the phase relationship between the internal clock of the device and the received burst signal for explaining the logic for judging the signal synchronized with the received burst signal. Hereinafter, referring to FIG. A method of determining a signal synchronized with a received burst signal by logic divided according to the number of transition points in two periods will be described. In the following, a set of the number of change points in the past two cycles will be described with a symbol (current number of change points, number of past change points). In FIG. 8, FIG. 8A shows an example of an internal clock of a device in which the bit synchronization circuit according to the present invention is mounted, and FIGS. 8B to 8F show examples of a reception burst signal.

In the case of (1, 0), for example, as shown in FIG. 8 (b), this corresponds to the case where the beginning of the bit synchronization signal is detected in the current cycle, and the fixed value shifts from the current change point. Let the point be the retiming position.

In the case of (1, 1), for example, as shown in FIG. 8C, the head of the bit synchronization signal is detected in the past cycle, and the end of the bit synchronization signal is detected in the current cycle. This corresponds to a case where the phase difference between the received burst signal and the internal clock of the device is close to 180 °, and an intermediate point between two changing points within two periods is calculated and set as a retiming position. Thereby, it is possible to cope with the duty fluctuation of the received burst signal.

In the case of (1, 2), for example, as shown in FIG. 8D, when the phase difference between the received burst signal and the internal clock of the apparatus is close to 0 ° and the duty is fluctuated. Correspondingly, an intermediate point between the trailing edge of the previous cycle and the change point in the current cycle is calculated and set as the retiming position. Thereby, it is possible to cope with the duty fluctuation of the received burst signal.

When the number of change points in the current cycle is 2, for example, as shown in FIG. 8 (e), the phase difference between the received burst signal and the internal clock of the device is close to 0 ° and the duty is fluctuated. This corresponds to the case where two change points are detected after the pattern of FIG. 8 (f) to be described later, or the case where the end of the bit synchronization signal is detected. Retiming position. Thereby, it is possible to cope with the duty fluctuation of the received burst signal.

When the number of change points in the current cycle is 0, for example, as shown in FIG. 8 (f), the phase difference between the received burst signal and the internal clock of the apparatus is close to 0 ° and the duty is fluctuated. This corresponds to a case where no change point is detected after the pattern of FIG. 8 (e) or a case where the end of the bit synchronization signal is detected. Retiming position. Also in this case, it is possible to cope with the case of duty fluctuation. Further, it is possible to cope with a case where a change point is lost due to a bit identification error or the like.

Further, by averaging the information from the judgment result holding unit within a certain period of time and using the information as selection information of the selection output unit, the detection change point position suddenly becomes an abnormal value due to a bit identification error or the like. The effect can be reduced.

[0038]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a bit synchronization circuit and a bit synchronization method according to the present invention.

FIG. 1 is a block diagram showing the configuration of the bit synchronization circuit according to the first embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of the bit synchronization circuit shown in FIG. 1, and FIG. Block diagram showing a configuration example of a point detection unit,
FIG. 4 is a block diagram showing a configuration example of the data sampling unit in FIG. 1, and FIG. 5 is a block diagram showing a configuration example of the multiphase clock generation unit in FIG. 1, 3 to 5, 1 is a data sampling unit, 2 is a selection output unit, 3 is a change point detection unit, 4 is a holding unit, 5 is a clock judgment unit, 6 is a judgment result holding unit, and 20 is a latch. , 21 is a transition point pulse detection section, 22 is a transition point encoder section, 30 is a polyphase sampling section, 31 is a polyphase clock generation section, 32 is a shift register, 33-1 to 33-7 are delay sections, 34 is This is the frequency divider.

The bit synchronizing circuit shown in FIG. 1 samples a received burst input signal and converts it into an n-sequence (where n is an integer of 2 or more) signal. and a selection output unit 2 for selecting and outputting a signal synchronized with the received burst input signal from the n-sequence signals.

A feature of the embodiment of the present invention lies in means for judging a signal synchronized with the received burst input signal. This judging means includes an n-sequence sampled by the data sampling unit 1. A change point detection unit 3 for detecting each rising and falling change point of the signal; a holding unit 4 for holding a detection result detected by the change point detection unit 3 at a certain timing; a change point detection unit 3 and a holding unit Either of the output results from 4 or
It comprises a clock determination unit 5 for determining a signal to be selected by the selection output unit 2 based on both, and a determination result holding unit 6 for holding the output result of the clock determination unit 5 at a certain timing.

In the following description, the number of phases n of a multiphase clock which is an n-sequence signal for sampling is represented by n = 8.
It is assumed that Further, for each of the eight series of signals sampled by the data sampling unit 1,
The description will be made by assigning numbers in order according to the phase positions at which they are sampled. Further, a clock having the same frequency as the frequency of the input data, such as a system clock of a device having the bit synchronization circuit according to the embodiment of the present invention, is referred to as a master clock.

The data sampling section 1 may be configured as shown in FIG. 4A or 4B. FIG. 4 (a)
The configuration example shown in (1) comprises a multi-phase sampling unit 30 and a multi-phase clock generation unit 31, and samples a received burst signal with the multi-phase clock generated by the multi-phase clock generation unit 31.

Assuming that the number of phases n of the multi-phase clock is n = 8, the multi-phase clock generator 31 has the following configuration as shown in FIG.
A reference clock having the same frequency as the received signal is (n-1)
= 7 delay units 33-1 to 33-7 respectively
What is necessary is to delay from the timing of / 8 cycle to the timing of (× cycle) × 7 and generate a multi-phase clock having a phase difference of ８ cycle. Further, as shown in FIG. 5B, the multi-phase clock generator 31 divides the high-speed clock having a frequency n = 8 times the received signal by the frequency divider 34 by eight, or By dividing the frequency by 4 using the rising transition point of a high-speed clock having a frequency of n / 2 = 4 times as a trigger by the section 34 and dividing the frequency by 4 using the falling transition point as a trigger, a phase difference of 1/8 cycle is obtained. Can be configured to generate an eight-phase polyphase clock having

The configuration example shown in FIG. 4B of the data sampling section 1 of the received burst signal uses the shift register 32. The shift register 32 converts the received burst signal into n = 8 times or n / 2 of the received signal. = 4 times sampling with a high-speed clock having a frequency and outputting it as an n-sequence signal.

As shown in FIG. 3, the change point detecting section 3 includes a latch section 20, a change point pulse transmitting section 21, and a change point encoder section 22. The latch unit 20 of the change point detection unit 3 configured as described above latches the eight series of signals sampled by the data sampling unit 1 using the master clock. The change point pulse sending unit 21 outputs H when the latched eight-phase signal is different from the state of the signal latched by the previous clock, that is, the state of the signal of the previous number. L is output to generate an eight-phase pulse train. The number of the signal in the H state in the pulse train generated in this manner is a number corresponding to the phase position where the rising or falling change point of the received burst signal exists.

The change point encoder unit 22 detects the number of the pulse in the H state in the eight-phase pulse train obtained from the change point pulse transmission unit 21 for each cycle of the master clock. The lowest number among them (hereafter,
Number A) and the oldest number (hereinafter number B)
) Is detected and output. The output number indicates the phase position of the rising or falling transition point of the received burst signal within one cycle of the master clock, indicating the phase in units of the phase difference between the multiphase clock phases. Equivalent to.

The holding unit 4 holds the above-mentioned output from the change point detecting unit 3 for a period of one master clock cycle. As a result, the result output from the holding unit 4 is the change point number output from the change point detection unit 3 one cycle before the master clock. However, the holding unit 4 is a change point detecting unit 3
Hold the change point is not detected during one cycle of the master clock (the number of the position held up to now + the length 8 of the cycle).

The clock judging unit 5 outputs one or both of the number of the change point output from the change point detection unit 3 and the number of the change point one cycle before the master clock output from the holding unit 4. Based on the information, a number in the middle of the two change points is calculated. More specifically, when the number A and the number B do not match, the clock determination unit 5
The number C of the intermediate point between the number A and the number B of the change point output from the change point detection unit 3 is calculated.

When the number A and the number B match and a change point is detected one cycle before the master clock, the clock judging section 5 outputs the number B and the output from the holding section 4. The number C of an intermediate point with the number B (hereinafter, referred to as B ′) of a change point one cycle before the master clock is calculated, and the number A matches the number B, and If the transition point is not detected before the period, as described above, the holding unit 4 outputs the master clock 2
Since the number B (hereinafter referred to as B ″) + 8 of the change point before the cycle is supplied, an intermediate point between the (number B ″ +8) and the number B is calculated and output as the number C.

The judgment result holding section 6 holds the number C which has been judged so far when no change point output from the change point detection section 3 is detected.

The selection output section 2 selects and outputs a signal corresponding to the same number as the number C from the eight series of signals sampled by the data sampling section 1.

FIG. 2 is a time chart showing the operation of the first embodiment of the present invention.

In FIG. 2, (a) is a master clock,
(B) is a received burst input signal, (c0) to (c7) are polyphase clocks, (d0) to (d7) are input signals sampled by the data sampling unit 1, (e1) and (e).
2) is the number A and the number B in the change point detecting unit 3;
(F) shows the number C selected by the selection output unit 2, respectively.

In the first embodiment of the present invention, the intermediate point between the numbers A and B is selected in the period 1 of the master clock in FIG. 2, and the result in the period 1 is held in the period 2 of the master clock. And
In cycle 3, an intermediate point between number B and cycle 1 number B (number B ″) is selected, and in cycle 4, an intermediate point between number B and cycle 3 number B (number B ′) is selected.

Next, a bit synchronization circuit according to a second embodiment of the present invention will be described. In the second embodiment of the present invention, the clock determination is made based on the phase position of the change point of the input data and the number of the change points, and the block shown in FIG. 1 similar to the first embodiment of the present invention. The detailed configuration of the change point detection unit 3, the holding unit 4, and the clock determination unit 5 is different.

Change point detector 3 according to the second embodiment of the present invention
Detects the number A and the number B corresponding to the phase position of the change point, similarly to the change point detection unit 3 of the first embodiment,
Further, it is configured to detect and output the number of change points within one cycle of the master clock.

Similarly to the holding unit 4 of the first embodiment, the holding unit 4 holds the output from the change point detection unit 3 for a time corresponding to one cycle of the master clock. When the change point is not detected in step 3, the special operation as in the case of the first embodiment is not performed.

The clock judging section 5 calculates the number A and the number B supplied from the change point detecting section 3, the number of change points, and the number one cycle before the master clock supplied from the holding section 4. A, the number B, or the number of change points, or a number in the middle of two change points is calculated based on both information.

FIG. 6 is a diagram for explaining the decision logic in the clock decision unit 5. Hereinafter, the decision logic in the clock decision unit 5 will be specifically described with reference to FIG.

When the number of transition points in one cycle of the master clock is 0, the number A one cycle before the held master clock is output (FIG. 6A). If the number of transition points in one cycle of the master clock is 1 and the number of transition points one cycle before the master clock is 0, the number A (or the number B) is n / 1/2 of one cycle of the master clock. The judgment number C is output by adding 2 = 4 [FIG. 6 (b)]. If the number of transition points in one cycle of the master clock is one and the number of transition points one cycle before the master clock is one and two, the number A
(Or number B) and an intermediate point between the number B (number B ') one cycle before the master clock is calculated and output as a determination number C [FIGS. 6 (c) and 6 (d)]. When the number of transition points in one master clock cycle is two, the number A plus 3 is output as the determination number C [FIG.
(E)].

The judgment result holding section 6 has been judging when the change point output from the change point detection section 3 is not detected, as in the case of the above-described first embodiment of the present invention. The number C is retained. Also, the selection output unit 2
Is the same as in the first embodiment of the present invention, out of the eight series of signals sampled by the data sampling unit 1,
The signal corresponding to the same number as the number C is selected.

FIG. 7 is a block diagram showing a configuration of a bit synchronization circuit according to a third embodiment of the present invention. In FIG. 7, reference numeral 7 denotes an integrating section, and other reference numerals are the same as those in FIG.

FIG. 7 shows a third embodiment of the present invention.
1 is different from the circuit shown in FIG. 1 in that the output of the determination result holding unit 6 is provided to the selection output unit 6 via the integration unit 7 in the bit synchronization circuit described above. Is configured.

In the third embodiment of the present invention, the integrator 7 performs a moving average of two cycles of the master clock on the judgment result supplied from the judgment result holding part 6 and selects and outputs the result.
Output to By this averaging, even when the detected change point position suddenly becomes an abnormal value due to a bit identification error or the like, the abnormality can be mitigated.

The section to be averaged is not limited to two cycles of the master clock, but may be three cycles or more.

[0067]

As described above, according to the present invention, the retiming phase determination is performed by using both the rising and falling transition points of the received burst signal, so that the high-speed transmission is performed. , It is possible to perform synchronization in a short section with respect to a received burst signal in which a duty change has occurred.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a bit synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart illustrating the operation of the bit synchronization circuit shown in FIG.

FIG. 3 is a block diagram illustrating a configuration example of a change point detection unit in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration example of a data sampling unit in FIG. 1;

FIG. 5 is a block diagram illustrating a configuration example of a multiphase clock generation unit in FIG. 4;

FIG. 6 is a diagram illustrating a determination logic of a clock determination unit according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a bit synchronization circuit according to a third embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of a phase relationship between a device internal clock and a received burst signal for explaining logic for determining a signal synchronized with the received burst signal.

FIG. 9 is a block diagram showing a configuration example of a point-to-multipoint optical transmission system according to a conventional technique.

FIG. 10 is a diagram illustrating a situation in which one communication device receives information cells from a plurality of communication devices.

FIG. 11 is a diagram illustrating a relationship between a time change of a threshold and an identified signal.

[Explanation of symbols]

 Reference Signs List 1 data sampling unit 2 selection output unit 3 change point detection unit 4 holding unit 5 clock judgment unit 6 judgment result holding unit 7 integration unit 20 latch unit 21 change point pulse detection unit 22 change point encoder unit 30 multiphase sampling unit 31 multiphase Clock generator 32 Shift register 33-1 to 33-7 Delay unit 34 Divider 100, 101-1, 101-2 Communication device 102 Star coupler

Continuing from the front page (72) Inventor, Yoshihiro Ashi 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. Hitachi, Ltd. Information and Communication Division (72) Inventor Tadashi Akiwa 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Japan Within Telegraph and Telephone Corporation (72) Inventor Yasuyuki Okumura 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-8-256137 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04L 7/02 H03K 5/00 H04L 7/00

Claims (18)

(57) [Claims] 1. A data sampling section for sampling a received burst input signal and outputting the signal as an n-series (where n is an integer of 2 or more) signal, and an n-series signal sampled by the data sampling section. And a selection output section for selecting and outputting a signal synchronized with the received burst input signal, wherein a change point of a rising edge and a change point of a falling edge of each of the n-sequence signals sampled by the data sampling section. A change point detection unit that detects a point, a holding unit that holds the detection result detected by the change point detection unit at a certain timing, and one or both of the output result from the change point detection unit and the holding unit A clock determination unit that determines a signal to be selected by the selection output unit based on E Bei a determination result holding unit for holding only the timing, the change point detection unit is sampled received burst
Detects rising and falling transition points of signal
And at the same time period as the data period of the received burst signal.
Judgment processing means for judging the phase position of the change point and the number of the change points
The holding unit receives a change point detection result from the change point detection unit.
One cycle of the same time cycle as the data cycle of the burst signal
And the clock determination unit receives the output from the change point detection unit.
The reception buffer within the same time period as the data period of the
Change point of the rising edge or falling edge of the
The number of the phase position and the changing point of the
One cycle of the same time cycle as the data cycle of the received burst signal
The phase position of the change point from the change point detection unit held by
And / or numbers.
A determination processing means for determining a signal to be selected by the selection output unit;
A bit synchronization circuit characterized in that the bit synchronization circuit is configured as follows. 2. The data sampling section generates a multi-phase clock composed of a plurality of n-sequences having different phases from each other, and uses the multi-phase clock to sample a received burst input signal and output it as an n-sequence signal. 2. The bit synchronization circuit according to claim 1, wherein said bit synchronization circuit comprises means. 3. The clock judging section, based on a phase position of a change point of the received burst signal transmitted from one or both of the change point detecting section and the holding section, includes two rising and falling edges of the received burst signal. 3. The apparatus according to claim 1, further comprising a determination processing unit configured to determine a received burst signal sampled at a phase position closest to the intermediate phase of the change point as a signal to be selected by the selection output unit. Bit synchronization circuit. 4. The clock judging section, wherein the number of rising or falling transition points of the reception burst signal within the same time period as the data cycle of the reception burst signal output from the transition point detection section is one. In the case where the number of change points from the change point detection unit held for one period of the same time period as the data period of the received burst signal in the holding unit is 0, the change point output from the change point detection unit is The selection output unit is configured to determine a reception burst signal sampled at a phase position closest to the phase shifted by a certain fixed timing with respect to the phase position as a signal to be selected by the selection output unit. bit synchronization circuit according to claim 1 or 2 wherein. 5. The clock judging section, wherein the number of rising transition points or falling transition points of the reception burst signal within the same time period as the data cycle of the reception burst signal output from the transition point detection section is one. In the case where the number of change points from the change point detection unit held by the holding unit for one period of the same time period as the data period of the received burst signal is one, the number of the change points output from the change point detection unit is Phase position, the received burst signal sampled at an intermediate phase position between the phase position of the change point output from the holding unit,
3. The bit synchronization circuit according to claim 1, wherein the selection output unit includes a determination processing unit that determines a signal to be selected. 6. The clock judging section, wherein the number of rising transition points or falling transition points of the received burst signal within the same time period as the data cycle of the received burst signal output from the transition point detecting section is one. In the case where the number of change points from the change point detection unit held by the holding unit for one period of the same time period as the data period of the reception burst signal is two, the number of change points output from the change point detection unit is Judgment processing for determining a reception burst signal sampled at an intermediate phase position between a phase position and a phase position of a trailing edge of two transition points output from the holding unit as a signal to be selected by the selection output unit 3. The bit synchronization circuit according to claim 1, wherein said bit synchronization circuit comprises means. 7. The clock judging section, wherein the number of rising transition points or falling transition points of the reception burst signal within the same time period as the data cycle of the reception burst signal output from the transition point detection section is two. In this case, the selection output unit is configured to determine a reception burst signal sampled at an intermediate phase position between the two transition points output from the transition point detection unit as a signal to be selected by the selection output unit. 3. The bit synchronization circuit according to claim 1, wherein: 8. The determination result holding unit, when the transition point detection unit does not detect a rising transition point or a falling transition point of the received burst signal within the same time period as the data period of the received burst signal, bit synchronization circuit as claimed in any one of claims 1 to 7, characterized in only a certain timing determination result of the decision to have the clock determination unit to be configured with a holding means for holding up. Wherein said determination result by averaging information is within time from the holding unit, any one of the claims 1 to 8, characterized by further comprising an averaging means for the selection information of the selection output section Bit synchronization circuit as described. 10. A received burst input signal is sampled to obtain an n-sequence (where n is an integer of 2 or more) signal, and a signal synchronized with the received burst input signal is selected from the sampled n-sequence signals. In the bit synchronization method of outputting the sampled reception burst signal, a rising transition point and a falling transition point of the sampled reception burst signal are detected, the transition point detection result is delayed by a certain timing, and Synchronized with the received burst input signal from the sampled signals based on one or both of the detection result of the rising transition point and the falling transition point and the detection result of the transition point delayed by the certain timing The signal is judged, the judgment result is held for a certain timing , and polyphase sampling is performed. Rise of receive burst signal
And the falling transition point are detected, and the received burst signal
Phase position and change of change point every time period same as data period
Including the process of determining the number of points, the rising edge of the sampled received burst signal and
The detection result detected a falling change point, the received burst
Holds one cycle of the same time cycle as the signal data cycle
Comprises that process, received in the same time period as the data period of the received burst signal
The position of the rising or falling transition point of the burst signal
The number of phase positions and transition points, and the data cycle of the received burst signal
In the past time period by one period of the same time period as the period
One or both of the phase position and the number of
Based on the received bar
A bit synchronization method including a process of determining a signal synchronized with a strike input signal . 11. A multi-phase clock comprising a plurality of n-phase clocks having mutually different phases, a process of sampling a received burst input signal using the multi-phase clock and outputting the same as an n-series signal. The bit synchronization method according to claim 10 . 12. A reception burst signal sampled at an intermediate phase position between two rising and falling transition points of the reception burst signal based on the phase position of the transition point of the reception burst signal, and synchronized with the reception burst input signal. 12. The bit synchronization method according to claim 10 , further comprising a determination process of determining that the signal has been obtained. 13. The number of rising or falling transition points of the received burst signal within the same time period as the data period of the received burst signal is one, and the number of transition points in the past by one period of the same time period as the data period of the received burst signal is 13. When the number of transition points in the time period is 0, the reception burst signal sampled at a phase position shifted by a certain fixed timing with respect to the phase position of the rising or falling transition point of the reception burst signal in the one period. 12. The bit synchronization method according to claim 10 , further comprising a process of determining that the signal is synchronized with a received burst input signal. 14. The number of rising or falling transition points of the received burst signal within the same time period as the data period of the received burst signal is one, and the number of the transition points in the past is one period of the same time period as the data period of the received burst signal. When the number of transition points in the time period is 1, sampling is performed at an intermediate phase position between the phase position of the rising or falling transition point of the received burst signal in the one cycle and the phase position of the transition point one cycle before. 12. The bit synchronization method according to claim 10 , further comprising the step of determining the received burst signal as a signal synchronized with the received burst input signal. 15. The number of rising or falling transition points of the received burst signal within the same time period as the data period of the received burst signal is one, and the number of points in the past corresponding to one period of the same time period as the data period of the received burst signal is 1. When the number of transition points in the time period is 2, the phase position of the rising or falling transition point of the received burst signal in the one cycle and the phase position of the trailing edge of the two transition points one cycle before The received burst signal sampled at the intermediate phase position between
12. The bit synchronization method according to claim 10 , further comprising a process of determining a signal synchronized with the received burst input signal. 16. When the number of rising or falling transition points of the received burst signal within the same time period as the data cycle of the received burst signal is 2, an intermediate phase position between the phase positions of the two transition points within the one period. 11. The method according to claim 10 , further comprising the step of: determining the received burst signal sampled in the step ( b ) as a signal synchronized with the received burst input signal.
Or the bit synchronization method according to 11 . 17. When a rising or falling transition point of the received burst signal within the same time period as the data cycle of the received burst signal is not detected, a signal synchronized with the received burst input signal determined so far is set at a certain timing. the preceding claims 10, characterized in that only hold 1
6. The bit synchronization method according to any one of 6 . 18. An averaging process for averaging information for selecting a signal synchronized with the received burst signal from among the sampled n-sequence received burst signals within a certain time period. Item 18. The bit synchronization method according to any one of Items 10 to 17 .